ST7MDT1-DVP2

ST72104G STMICROELECTRONICS | Alldatasheet

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Rev. 2.2 February 2000 1/135 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. ST72104G, ST72215G, ST72216G, ST72254G 8-BIT MCU WITH SINGLE VOLT AGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, I2C INTERFACES PRELIMINARY DATA n Memories – 4K or 8K bytes Program memory (ROM and single voltage FLASH) with read-out protec- tion and in-situ programming (remote ISP) – 256 bytes RAM n Clock, Reset and Supply Management – Enhanced reset system – Enhanced low voltage supply supervisor with 3 programmable levels – Clock sources: crystal/ceramic resonator os- cillators or RC oscillators, external clock, backup Clock Security System – Clock-out capability – 3 Power Saving Modes: Halt, Wait and Slow n Interrupt Management – 7 interrupt vectors plus TRAP and RESET – 22 external interrupt lines (on 2 vectors) n 22 I/O Ports – 22 multifunctional bidirectional I/O lines – 14 alternate function lines – 8 high sink outputs n 3 Timers – Configurable watchdog timer – Two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input on one tim- er, PWM and Pulse generator modes (one only on ST72104Gx and ST72216G1) n 2 Communications Interfaces – SPI synchronous serial interface – I2C multimaster interface (only on ST72254Gx) n 1 Analog peripheral – 8-bit ADC with 6 input channels (except on ST72104Gx) n Instruction Set – 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation n Development Tools – Full hardware/software development package Device Summary SDIP32 SO28 Features ST72104G1 ST72104G2 ST72216G1 ST72215G2 ST72254G1 ST72254G2 Program memory - bytes 4K 8K 4K 8K 4K 8K RAM (stack) - bytes 256 (128) Peripherals Watchdog timer, One 16-bit timer, SPI Watchdog timer, One 16-bit timer, SPI, ADC Watchdog timer, Two 16-bit timers, SPI, ADC Watchdog timer, Two 16-bit timers, SPI, I C, ADC Operating Supply 3.0V to 5.5V CPU Frequency Up to 8 MHz (with oscillator up to 16 MHz) Operating Temperature -40 °C to +85°C (-40°C to +105/125°C optional)

ST72104G, ST72215G, ST72216G, ST72254G

ST72104G, ST72215G, ST72216G, ST72254G

1 INTRODUCTION

applications but without I C interface. not need ADC and I C peripherals. Figure 1. General Block Diagram

2 PIN DESCRIPTION

Figure 2. 28-Pin SO Package Pinout Figure 3. 32-Pin SDIP Package Pinout

Refer to Section 9 ”I/O PORTS” on page 30 for more details on the software configuration of the I/O ports. Table 1. Device Pin Description

ST72104G, ST72215G, ST72216G, ST72254G Notes: 1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V DD are not implemented). See Section 9 ”I/O PORTS” on page 30 and Section 13.8 ”I/O PORT PIN CHAR- ACTERISTICS” on page 114 for more details. 3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 2 ”PIN DESCRIPTION” on page 7 and Section 13.5 ”CLOCK AND TIM- ING CHARACTERISTICS” on page 104 for more details. 18 16 PC1/OCMP1_B/AIN1 I/O C T X ei0/ei1 X X X Port C1 Timer B Output Compare 1 or ADC Analog Input 1 19 17 PC0/ICAP1_B/AIN0 I/O C T X ei0/ei1 X X X Port C0 Timer B Input Capture 1 or ADC Analog Input 0 20 18 PA7 I/O C T HS X ei0 X X Port A7 21 19 PA6 /SDAI I/O C T HS X ei0 T Port A6 I2C Data 22 20 PA5 I/O C T HS X ei0 X X Port A5 23 21 PA4 /SCLI I/O C T HS X ei0 T Port A4 I2C Clock 24 NC Not Connected 25 NC 26 22 PA3 I/O C T HS X ei0 X X Port A3 27 23 PA2 I/O C T HS X ei0 X X Port A2 28 24 PA1 I/O C T HS X ei0 X X Port A1 29 25 PA0 I/O C T HS X ei0 X X Port A0 30 26 ISPSEL I C X In situ programming selection (Should be tied low in standard user mode). 31 27 V SS S Ground 32 28 V DD S Main power supply Pin n° Pin Name Type Level Port / Control Main Function (after reset) Alternate Function SDIP32 SO28 Input Output Input Output float wpu int ana OD PP

3 REGISTER & MEMORY MAP

Figure 4. Memory Map

4 KBytes

8 KBytes

Table 2. Hardware Register Map

ST72104G, ST72215G, ST72216G, ST72254G Legend : x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh TIMER A TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0040h MISCR2 Miscellaneous Register 2 00h R/W 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh TIMER B TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0050h to 006Fh Reserved (32 Bytes) 0070h 0071h ADC ADCDR ADCCSR Data Register Control/Status Register 00h 00h Read Only R/W 0072h to 007Fh Reserved (14 Bytes) Address Block Register Label Register Name Reset Status Remarks

4 FLASH PROGRAM MEMORY

4.1 INTRODUCTION

4.2 MAIN FEATURES

4.3 STRUCTURAL ORGANISATION

for storing both code and data constants. the reset and interrupt user vector area .

4.4 IN-SITU PROGRAMMING (ISP) MODE

ter the device is mounted on the application board. the ST7 Programming Specification. quence on the dedicated ISPSEL pin. cillator and application crystal circuit for example). board through a pull-down resistor. Figure 5. Typical Remote ISP Interface

4.5 MEMORY READ-OUT PROTECTION

5 CENTRAL PROCESSING UNIT

5.1 INTRODUCTION

5.2 MAIN FEATURES

5.3 CPU REGISTERS

temporary storage areas for data manipulation. (Program Counter High which is the MSB). Figure 6. CPU Registers

ST72104G, ST72215G, ST72216G, ST72254G CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions. These bits can be individually tested and/or con- trolled by specific instructions. Bit 4 =H Half carry. This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines. Bit 3 =IInterrupt mask. This bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET in- structions and is tested by the JRM and JRNM in- structions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware when you en- ter it and reset by the IRET instruction at the end of the interrupt routine. If the I bit is cleared by soft- ware in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. Bit 2 =N Negative. This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- tions. Bit 1 =Z Zero. This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 =C Carry/borrow. This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. 111HINZC

ways pointing to the next free location in the stack. popped from the stack (see Figure 7). mented and the context is pushed on the stack. and the context is popped from the stack. terrupt five locations in the stack area. Figure 7. Stack Manipulation Example

0 SP6 SP5 SP4 SP3 SP2 SP1 SP0

6 SUPPLY, RESET AND CLOCK MANAGEMENT

nents. An overview is shown in Figure 8. TICS” on page 96 for more details. Figure 8. Clock, Reset and Supply Block Diagram

6.1 LOW VOLTAGE DETECTOR (LVD)

well as the power-down keeping the ST7 in reset. ning and sinks current on the supply (hysteresis). The LVD function is illustrated in the Figure 9.

1. The LVD allows the device to be used without

any external RESET circuitry.

1. Three different reference levels are selectable

generated and cleared by software (writing zero). Figure 9. Low Voltage Detector vs Reset

6.2 RESET SEQUENCE MANAGER (RSM)

6.2.1 Introduction

ways kept low during the delay phase. dresses FFFEh-FFFFh in the ST7 memory map. taken place from the Reset state. Figure 10. RESET Sequence Phases Figure 11. Reset Block Diagram

4096 CLOCK CYCLES

6.2.2 Asynchronous External RESET pin

output with integrated RON weak pull-up resistor. electrical characteristics section for more details.

6.2.3 Internal Low Voltage Detection RESET

VDD <V IT-(falling edge) as shown in Figure 12.

6.2.4 Internal Watchdog RESET

Watchdog counter overflow is shown in Figure 12. Figure 12. RESET Sequences

6.3 MULTI-OSCILLATOR (MO)

electrical characteristics section for more details. the OSC1 pin while the OSC2 pin is tied to ground. cording to the selected oscillator. is fixed by the resistor and the capacitor values. frequency is in the range of several MHz. Table 3. ST7 Clock Sources

6.4 CLOCK SECURITY SYSTEM (CSS)

6.4.1 Clock Filter Control

frequency spikes on the ST7 main clock.

6.4.2 Safe Oscillator Control

quency back-up clock source (see Figure 13). SIE bit has been previously set.

6.4.3 Low Power Modes

6.4.4 Interrupts

Figure 13. Clock Filter Function and Safe Oscillator Function device to exit from Wait mode.

6.5 CLOCK RESET AND SUPPLY REGISTER DESCRIPTION (CRSR)

Bit 7:5 =Reserved, always read as 0. Bit 3 =Reserved, always read as 0. set). It is set and cleared by software. CSSD bit value is forced to 0. flag description is given by the following table. software while an external reset can not. Table 4. Clock, Reset and Supply Register Map and Reset Values

000 LVD

6.6 MAIN CLOCK CONTROLLER (MCC)

clock for the ST7 CPU and its internal peripherals. the MISCR1: CP1, CP0 and SMS. TERS” on page 36 for more details. Figure 14. Main Clock Controller (MCC) Block Diagram

ST72104G, ST72215G, ST72216G, ST72254G

7 INTERRUPTS

The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 15. The maskable interrupts must be enabled clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsec- tion). When an interrupt has to be serviced: – Normal processing is suspended at the end of the current instruction execution. – The PC, X, A and CC registers are saved onto the stack. – The I bit of the CC register is set to prevent addi- tional interrupts. – The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector address- es). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority management By default, a servicing interrupt cannot be inter- rupted because the I bit is set by hardware enter- ing in interrupt routine. In the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the Interrupt Map- ping Table). Interrupts and Low power mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifi- cally mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT“ column in the Interrupt Mapping Ta- ble).

7.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc- tion is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 15.

7.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same inter- rupt vector, are configured as interrupts, their sig- nals are logically ANDed before entering the edge/ level detection block. Caution:The type of sensitivity defined in the Mis- cellaneous or Interrupt register (if available) ap- plies to the ei source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity.

7.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: – The I bit of the CC register is cleared. – The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status register or – Access to the status register while the flag is set followed by a read or write of an associated reg- ister. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed.

Figure 15. Interrupt Processing Flowchart Table 5. Interrupt Mapping

1. Configurable by option byte.

2 CSS Clock Filter Interrupt CRSR

3 SPI SPI Peripheral Interrupts SPISR FFF4h-FFF5h

4 TIMER A TIMER A Peripheral Interrupts TASR FFF2h-FFF3h

5 Not used FFF0h-FFF1h

6 TIMER B TIMER B Peripheral Interrupts TBSR no FFEEh-FFEFh

7 Not used FFECh-FFEDh

8 Not used FFEAh-FFEBh

9 Not used FFE8h-FFE9h

10 Not used FFE6h-FFE7h

11 I C I C Peripheral Interrupt I2CSRx no FFE4h-FFE5h

12 Not Used FFE2h-FFE3h

13 Not Used FFE0h-FFE1h

8 POWER SAVING MODES

8.1 INTRODUCTION

Figure 16. Power Saving Mode Transitions

8.2 SLOW MODE

the available supply voltage. Figure 17. SLOW Mode Clock Transitions

8.3 WAIT MODE

sumption mode by stopping the CPU. “WFI” ST7 software instruction. address of the interrupt or Reset service routine. or an Interrupt occurs, causing it to wake up. Figure 18. WAIT Mode Flow-chart

1. Before servicing an interrupt, the CC register is

4096 CPU CLOCK CYCLE

8.4 HALT MODE

ST7 HALT instruction (see Figure 20).

4096 CPU cycle delay is used to stabilize the os-

the reset vector which woke it up (see Figure 19). cluding the operation of the on-chip peripherals. Figure 19. HALT Mode Timing Overview Figure 20. HALT Mode Flow-chart

1. WDGHALT is an option bit. See option byte sec-
2. Peripheral clocked with an external clock source
3. Only some specific interrupts can exit the MCU
4. Before servicing an interrupt, the CC register is

ST72104G, ST72215G, ST72216G, ST72254G

9 I/O PORTS

9.1 INTRODUCTION

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre- sponding register bits in the DDR and OR regis- ters: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not pro- vide this register refer to the I/O Port Implementa- tion section). The generic I/O block diagram is shown in Figure 21

9.2.1 Input Modes

The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external inter- rupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Mis- cellaneous register. Each external interrupt vector is linked to a dedi- cated group of I/O port pins (see pinout description and interrupt section). If several input pins are se- lected simultaneously as interrupt source, these are logically ANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configura- tion, special care must be taken when changing the configuration (see Figure 22). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellane- ous register must be modified.

9.2.2 Output Modes

The output configuration is selected by setting the corresponding DDR register bit. In this case, writ- ing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR reg- ister returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:

9.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip periph- eral, the I/O pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. DR Push-pull Open-drain 0V SS Vss 1V DD Floating

Figure 21. I/O Port General Block Diagram Table 6. I/O Port Mode Options vice against positive stress.

Table 7. I/O Port Configurations

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

1. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

9.3 I/O PORT IMPLEMENTATION

such as spurious interrupt generation. Figure 22. Interrupt I/O Port State Transitions Table 8. Port Configuration

ST72104G, ST72215G, ST72216G, ST72254G I/O PORTS (Cont’d)

9.4 LOW POWER MODES

9.5 INTERRUPTS

The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and the I-bit in the CC reg- ister is reset (RIM instruction).

9.6 REGISTER DESCRIPTION

DATA REGISTER (DR) Port x Data Register PxDR with x = A, B or C. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 =D[7:0]Data register 8 bits. The DR register has a specific behaviour accord- ing to the selected input/output configuration. Writ- ing the DR register is always taken into account even if the pin is configured as an input; this allows always having the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B or C. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 =DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B or C. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 =O[7:0]Option register 8 bits. For specific I/O pins, this register is not implement- ed. In this case the DDR register is enough to se- lect the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: Floating input 1: Pull-up input with or without interrupt Output mode: 0: Output open drain (with P-Buffer unactivated) 1: Output push-pull (when available) Mode Description WAIT No effect on I/O ports. External interrupts cause the device to exit from WAIT mode. HALT No effect on I/O ports. External interrupts cause the device to exit from HALT mode. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt External interrupt on selected external event - DDRx ORx Yes Yes D7 D6 D5 D4 D3 D2 D1 D0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 O7 O6 O5 O4 O3 O2 O1 O0

Table 9. I/O Port Register Map and Reset Values

10 MISCELLANEOUS REGISTERS

terrupts or the I/O alternate functions.

10.1 I/O PORT INTERRUPT SENSITIVITY

bit) as shown in Figure 23 and Figure 24.

10.2 I/O PORT ALTERNATE FUNCTIONS

function while the SPI is active. deactivated while the SPI is active. activated while the SPI is active. Figure 23. Ext. Interrupt Sensitivity (EXTIT=0) Figure 24. Ext. Interrupt Sensitivity (EXTIT=1)

ST72104G, ST72215G, ST72216G, ST72254G MISCELLANEOUS REGISTERS (Cont’d)

10.3 MISCELLANEOUS REGISTER DESCRIPTION

MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h) Bit 7:6 =IS1[1:0]ei1 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the ei1 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked). ei1: Port B (C optional) Bit 5 =MCO Main clock out selection This bit enables the MCO alternate function on the PC2 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fCPU on I/O port) Bit 4:3 =IS0[1:0]ei0 sensitivity The interrupt sensitivity, defined using the IS0[1:0] bits, is applied to the ei0 external interrupts. These two bits can be written only when the I bit of the CC register is set to 1 (interrupt masked). ei0: Port A (C optional) Bit 2:1 =CP[1:0]CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software Bit 0 =SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC /2 1: Slow mode. fCPU is given by CP1, CP0 See low power consumption mode and MCC chapters for more details. IS11 IS10 MCO IS01 IS00 CP1 CP0 SMS External Interrupt Sensitivity IS11 IS10 Falling edge & low level 0 0 Rising edge only 0 1 Falling edge only 1 0 Rising and falling edge 1 1 External Interrupt Sensitivity IS01 IS00 Falling edge & low level 0 0 Rising edge only 0 1 Falling edge only 1 0 Rising and falling edge 1 1 f CPU in SLOW mode CP1 CP0 fOSC /4 0 0 fOSC /8 1 0 fOSC /1 6 0 1 fOSC /3 2 1 1

disables the SPI Master (MOSI) output signal. 0: SPI Master Output enabled. 1: SPI Master Output disabled. disable the SPI Slave (MISO) output signal. 0: SPI Slave Output enabled. 1: SPI Slave Output disabled. This bit is set and cleared by software. input from the external SS pin. Table 10. Miscellaneous Register Map and Reset Values

11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

11.1.2 Main Features

n Hardware Watchdog selectable by option byte.

11.1.3 Functional Description

programmed by the user in 64 increments. Figure 25. Watchdog Block Diagram

Table 11. Watchdog Timing (fCPU = 8 MHz) set (the WDGA bit is set and the T6 bit is cleared).

11.1.4 Hardware Watchdog Option

11.1.5 Low Power Modes

11.1.5.1 Using Halt Mode with the WDG (option)

when the watchdog is enabled. generated, the WDG is disabled (reset state). wake up the microcontroller from Halt mode. the wake-up event (reset or external interrupt).

11.1.6 Interrupts

11.1.7 Register Description

watchdog can generate a reset. Bit 6:0 =T[6:0]7-bit timer (MSB to LSB).

Table 12. Watchdog Timer Register Map and Reset Values

ST72104G, ST72215G, ST72216G, ST72254G 11.2 16-BIT TIMER

11.2.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals (input capture) or generation of up to two out- put waveforms (output compareand PWM ). Pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequen- cies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).

11.2.2 Main Features

n Programmable prescaler: fCPU dividedby2, 4or 8. n Overflow status flag and maskable interrupt n External clock input (must be at least 4 times slower thanthe CPUclock speed) with the choice of active edge n Output compare functions with – 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt n Input capture functions with – 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt n Pulse width modulation mode (PWM) n One pulse mode n 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 26. *Note:Some timer pins may not available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be ‘1’.

11.2.3 Functional Description

11.2.3.1 Counter

The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): – Counter High Register (CHR) is the most sig- nificant byte (MS Byte). – Counter Low Register (CLR) is the least sig- nificant byte (LS Byte). Alternate Counter Register (ACR) – Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). – Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit tim- er). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 13 Clock Control Bits. The value in the counter register re- peats every 131.072, 262.144 or 524.288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be f CPU /2, fCPU /4, fCPU /8 or an external frequency.

Figure 26. Timer Block Diagram

ST72104G, ST72215G, ST72216G, ST72254G 16-BIT TIMER(Cont’d) 16-bit read sequence:(from either the Counter Register or the Alternate Counter Register). The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they re- turn the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, out- put compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: – The TOF bit of the SR register is set. – A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes:The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

11.2.3.2 External Clock

The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the exter- nal clock pin EXTCLK that will trigger the free run- ning counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the CPU clock frequency. is buffered Read At t0 Read Returns the buffered LS Byte value at t0At t0 +Δt Other instructions Beginning of the sequence Sequence completed LS Byte LS Byte MS Byte

ST72104G, ST72215G, ST72216G, ST72254G 16-BIT TIMER(Cont’d)

11.2.3.3 Input Capture

In this section, the index,i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter after a transition detected by the ICAP ipin (see figure 5). ICiR register is a read-only register. The active transition is software programmable through the IEDGibit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU /CC[1:0]). Procedure: To use the input capture function select the follow- ing in the CR2 register: – Select the timer clock (CC[1:0]) (see Table 13 Clock Control Bits). – Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input). And select the following in the CR1 register: – Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input). When an input capture occurs: – ICFibit is set. – The ICiR register contains the value of the free running counter on the active transition on the ICAP ipin (see Figure 31). – A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Other- wise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICF ibit) is done in two steps: 1. Reading the SR register while the ICFibit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One pulse Mode and PWM mode only the input capture 2 can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input cap- ture function. Moreover if one of the ICAP ipin is configured as an input and the second one as an output, an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set. This can be avoided if the input capture func- tion iis disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with interrupt in order to measure event that go beyond the timer range (FFFFh). MS Byte LS Byte ICiR IC iHR IC iLR

ST72104G, ST72215G, ST72216G, ST72254G 16-BIT TIMER(Cont’d)

11.2.3.4 Output Compare

In this section, the index,i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Com- pare register and the free running counter, the out- put compare function: – Assigns pins with a programmable value if the OCIE bit is set – Sets a flag in the status register – Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC iR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/ CC[1:0]). Procedure: To use the output compare function, select the fol- lowing in the CR2 register: – Set the OCiE bit if an output is needed then the OCMP ipin is dedicated to the output comparei signal. – Select the timer clock (CC[1:0]) (see Table 13 Clock Control Bits). And select the following in the CR1 register: – Select the OLVLibit to applied to the OCMPipins after the match occurs. – Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: – OCF ibit is set. – The OCMP ipin takes OLVLibit value (OCMPi pin latch is forced low during reset). – A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: Δt = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 de- pending on CC[1:0] bits, see Table 13 Clock Control Bits) If the timer clock is an external clock, the formula is: Where: Δt = Output compare period (in seconds) fEXT = External timer clock frequency (in hertz) Clearing the output compare interrupt request (i.e. clearing the OCFibit) is done by: 1. Reading the SR register while the OCFibit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to pre- vent the OCFibit from being set between the time it is read and the write to the OCiR register: – Write to the OCiHR register (further compares are inhibited). – Read the SR register (first step of the clearance of the OCFibit, which may be already set). – Write to the OCiLR register (enables the output compare function and clears the OCFibit). MS Byte LS Byte OC iRO C iHR OC iLR Δ OC iR= Δt* fCPU PRESC Δ OC iR= Δ t* fEXT

1. After a processor write cycle to the OCiHR reg-

until the OCiLR register is also written.

1. If the OCiE bit is not set, the OCMPipin is a

could be generated if the OCIE bit is set.

1. When the timer clock is fCPU /2, OCFi and

ter value plus 1 (see Figure 34 on page 49).

1. The output compare functions can be used both
2. The value in the 16-bit OC

waveform or establish a new elapsed timeout. Figure 32. Output Compare Block Diagram

16 BIT FREE RUNNING

ST72104G, ST72215G, ST72216G, ST72254G 16-BIT TIMER(Cont’d)

11.2.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use one pulse mode: 1. Load the OC1R register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded- icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 13 Clock Control Bits). Then, on a valid event on the ICAP1 pin, the coun- ter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the val- ue FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the Input Capture interrupt request (i.e. clearing the ICF ibit) is done in two steps: 1. Reading the SR register while the ICFibit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the fol- lowing formula: Where: t = Pulse period (in seconds) f CPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depend- ing on the CC[1:0] bits, see Table 13 Clock Control Bits) If the timer clock is an external clock the formula is: Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 35). Notes: 1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When one pulse mode is used OC1R is dedi- cated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an out- put waveform because the level OLVL2 is dedi- cated to the one pulse mode. event occurs Counter = OC1R OCMP1 = OLVL1 When When on ICAP1 One pulse mode cycle OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set OC iR Value = t*fCPU PRESC OC iR= t* fEXT -5

ST72104G, ST72215G, ST72216G, ST72254G 16-BIT TIMER(Cont’d)

11.2.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The pulse width modulation mode uses the com- plete Output Compare 1 function plus the OC2R register, and so these functionality can not be used when the PWM mode is activated. Procedure To use pulse width modulation mode: 1. Load the OC2R register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corre- sponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the oppo- site column. 3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after a successful comparison with OC1R register. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat- ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 13 Clock Control Bits). If OLVL1=1 and OLVL2=0 the length of the posi- tive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OC iR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depend- ing on CC[1:0] bits, see Table 13 Clock Control Bits) If the timer clock is an external clock the formula is: Where: t = Signal or pulse period (in seconds) f EXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 36) Notes: 1. After a write instruction to the OC iHR register, the output compare function is inhibited until the OC iLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the coun- ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is discon- nected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. Counter OCMP1 = OLVL2 Counter = OC2R OCMP1 = OLVL1 When When = OC1R Pulse Width Modulation cycle Counter is reset to FFFCh ICF1 bit is set OC iR Value = t*fCPU PRESC OC iR= t* fEXT -5

ST72104G, ST72215G, ST72216G, ST72254G 16-BIT TIMER(Cont’d)

11.2.4 Low Power Modes

11.2.5 Interrupts

Note:The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap- ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 2) See note 5 in Section 11.2.3.5 ”One Pulse Mode” on page 50 3) See note 4 in Section 11.2.3.6 ”Pulse Width Modulation Mode” on page 52 Mode Description WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. HALT 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAP ipin, the input capture detection circuitry is armed. Consequent- ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFibit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE Yes No Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 OCIE Yes No Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes No MODES AVAILABLE RESOURCES Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) Yes Yes Yes Yes One Pulse Mode No Not Recommended 1) No Partially 2) PWM Mode No Not Recommended 3) No No

ST72104G, ST72215G, ST72216G, ST72254G 16-BIT TIMER(Cont’d)

11.2.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) Bit 7 =ICIEInput Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 =OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 =TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 =FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 =FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no suc- cessful comparison. Bit 2 =OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg- ister and OCxE is set in the CR2 register. This val- ue is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode. Bit 1 =IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 =OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin when- ever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Output Compare 1 Pin Enable. free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Output Compare 2 Pin Enable. free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. 0: One Pulse Mode is not active. contents of the OC1R register. Table 13. Clock Control Bits on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

ST72104G, ST72215G, ST72216G, ST72254G 16-BIT TIMER(Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. Bit 7 =ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 =OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) reg- ister. Bit 5 =TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR reg- ister, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 =ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 =OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) reg- ister. Bit 2-0 = Reserved, forced by hardware to 0. INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. ICF1 OCF1 TOF ICF2 OCF2 0 0 0 70 MSB LSB MSB LSB MSB LSB MSB LSB

ST72104G, ST72215G, ST72216G, ST72254G 16-BIT TIMER(Cont’d) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit. ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register. INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event). INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the In- put Capture 2 event). MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

Table 14. 16-Bit Timer Register Map and Reset Values

11.3 SERIAL PERIPHERAL INTERFACE (SPI)

11.3.1 Introduction

which devices may be either masters or slaves.

11.3.2 Main Features

n Maximum slave mode frequency = fCPU/2. n Master mode fault protection capability.

11.3.3 General description

must be programmed with the same timing mode. Figure 37. Serial Peripheral Interface Master/Slave

Figure 38. Serial Peripheral Interface Block Diagram

ST72104G, ST72215G, ST72216G, ST72254G SERIAL PERIPHERAL INTERFACE (Cont’d)

11.3.4 Functional Description

Figure 37 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer to the CR, SR and DR registers in Section 11.3.7for the bit definitions.

11.3.4.1 Master Configuration

In a master configuration, the serial clock is gener- ated on the SCK pin. Procedure – Select the SPR0 & SPR1 bits to define the se- rial clock baud rate (see CR register). – Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 40). – The SS pin must be connected to a high level signal during the complete byte transmit se- quence. – The MSTR and SPE bits must be set (they re- main set only if the SS pin is connected to a high level signal). In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is writ- ten the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A write or a read of the DR register. Note:While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.

ST72104G, ST72215G, ST72216G, ST72254G SERIAL PERIPHERAL INTERFACE (Cont’d)

11.3.4.2 Slave Configuration

In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – For correct data transfer, the slave device must be in the same timing mode as the mas- ter device (CPOL and CPHA bits). See Figure 40. – The SS pin must be connected to a low level signal during the complete byte transmit se- quence. – Clear the MSTR bit and set the SPE bit to as- sign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2. A write or a read of the DR register. Notes:While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 11.3.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 11.3.4.4).

11.3.4.3 Data Transfer Format

ed do not interfere with the SPI transfer. by software, using the CPOL and CPHA bits. master and the slave device. be driven by the master device. clock edge before the capture clock edge. the occurrence of the second clock transition. currence of the first clock transition. each byte transmitted (see Figure 39). Figure 39. CPHA / SS Timing Diagram

Figure 40. Data Clock Timing Diagram Note:This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

11.3.4.4 Write Collision Error

the software write will be unsuccessful. nal MISO pin of the slave device. (SCK) is in the process of transfer. is set (the WCOL bit is a status flag only). Figure 41. Clearing the WCOL bit (Write Collision Flag) Software Sequence

ST72104G, ST72215G, ST72216G, ST72254G SERIAL PERIPHERAL INTERFACE (Cont’d)

11.3.4.5 Master Mode Fault

Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. – The SPE bit is reset. This blocks all output from the device and disables the SPI periph- eral. – The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes:To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing se- quence of the MODF bit. The SPE and MSTR bits may be restored to their original state during or af- ter this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine.

11.3.4.6 Overrun Condition

An overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripher- al.

11.3.4.7 Single Master and Multimaster Configurations

the four SS pins of the slave devices. that time, thus disabling the slave devices. through the serial peripheral interface system. Figure 42. Single Master Configuration

ST72104G, ST72215G, ST72216G, ST72254G SERIAL PERIPHERAL INTERFACE (Cont’d)

11.3.5 Low Power Modes

11.3.6 Interrupts

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Transfer Event SPIF SPIE Yes No Master Mode Fault Event MODF Yes No

11.3.7 Register Description

Serial peripheral interrupt enable. This bit is set and cleared by software. Bit 6 =SPE Serial peripheral output enable. eral is not initially connected to the external pins. set the baud rate. Refer to Table 15. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. This bit is set and cleared by software. Bit 1:0 =SPR[1 :0]Serial peripheral rate. These 2 bits have no effect in slave mode. Table 15. Serial Peripheral Baud Rate

ST72104G, ST72215G, ST72216G, ST72254G SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) Bit 7 =SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a soft- ware sequence (an access to the SR register fol- lowed by a read or write to the DR register). 0: Data transfer is in progress or has been ap- proved by a clearing sequence. 1: Data transfer between the device and an exter- nal device has been completed. Note:While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 =WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 41). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 =MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 11.3.4.5 ”Master Mode Fault” on page 66). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An ac- cess to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused. DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/re- ception of another byte. Notes:During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A write to the the DR register returns the value lo- cated in the buffer and not the contents of the shift register (See Figure 38 ). SPIF WCOL - MODF - - - - D7 D6 D5 D4 D3 D2 D1 D0

Table 16. SPI Register Map and Reset Values

11.4 I2C BUS INTERFACE (I2C)

11.4.1 Introduction

11.4.2 Main Features

11.4.3 General Description

bus by a data pin (SDAI) and by a clock pin (SCLI). By default, it operates in slave mode. generated in master mode by software. tection may be enabled or disabled by software. Figure 43. I

dress can be selected by software. controller to write the byte in the Data Register. read the byte in the Data Register. used depends on the application. ports revert to being standard I/O port pins. Figure 44. I2C Interface Block Diagram

ST72104G, ST72215G, ST72216G, ST72254G I2C BUS INTERFACE (Cont’d)

11.4.4 Functional Description

Refer to the CR, SR1 and SR2 registers in Section 11.4.7. for the bit definitions. By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register.

11.4.4.1 Slave Mode

As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software). Note:In 10-bit addressing mode, the comparision includes the header sequence (11110xx0) and the two most significant bits of the address. Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set. Address not matched : the interface ignores it and waits for another Start condition. Address matched: the interface generates in se- quence: – Acknowledge pulse if the ACK bit is set. – EVF and ADSL bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 reg- ister,holding the SCL line low(see Figure 45 Transfer sequencing EV1). Next, in 7-bit mode read the DR register to deter- mine from the least significant bit (Data Direction Bit) if the slave must enter Receiver or Transmitter mode. In 10-bit mode, after receiving the address se- quence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1) . Slave Receiver Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the inter- nal shift register. After each byte the interface gen- erates in sequence: – Acknowledge pulse if the ACK bit is set – EVF and BTF bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 reg- ister followed by a read of the DR register,holding the SCL line low(see Figure 45 Transfer se- quencing EV2). Slave Transmitter Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave waits for a read of the SR1 register fol- lowed by a write in the DR register,holding the SCL line low(see Figure 45 Transfer sequencing EV3). When the acknowledge pulse is received: – The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Closing slave communication After the last data byte is transferred a Stop Con- dition is generated by the master. The interface detects this condition and sets: – EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 reg- ister (see Figure 45 Transfer sequencing EV4). Error Cases – BERR : Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop then the interface discards the data, released the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus. – AF : Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an inter- rupt if the ITE bit is set. Note: In both cases, SCL line is not held low; how- ever, SDA line can remain low due to possible «0» bits transmitted last. It is then necessary to release both lines by software.

ST72104G, ST72215G, ST72216G, ST72254G I2C BUS INTERFACE (Cont’d) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte.

11.4.4.2 Master Mode

To switch from default Slave mode to Master mode a Start condition generation is needed. Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condi- tion. Once the Start condition is sent: – The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. Then the master waits for a read of the SR1 regis- ter followed by a write in the DR register with the Slave address,holding the SCL line low(see Figure 45 Transfer sequencing EV5). Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. In 7-bit addressing mode, one address byte is sent. In 10-bit addressing mode, sending the first byte including the header sequence causes the follow- ing event: – The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 regis- ter followed by a write in the DR register,holding the SCL line low(see Figure 45 Transfer se- quencing EV9). Then the second address byte is sent by the inter- face. After completion of this transfer (and acknowledge from the slave if the ACK bit is set): – The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 regis- ter followed by a write in the CR register (for exam- ple set PE bit),holding the SCL line low(see Fig- ure 45 Transfer sequencing EV6). Next the master must enter Receiver or Transmit- ter mode. Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set (11110xx1). Master Receiver Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR reg- ister via the internal shift register. After each byte the interface generates in sequence: – Acknowledge pulse if if the ACK bit is set – EVF and BTF bits are set by hardware with an in- terrupt if the ITE bit is set. Then the interface waits for a read of the SR1 reg- ister followed by a read of the DR register,holding the SCL line low(see Figure 45 Transfer se- quencing EV7). To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Note:In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.

ST72104G, ST72215G, ST72216G, ST72254G I2C BUS INTERFACE (Cont’d) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the inter- nal shift register. The master waits for a read of the SR1 register fol- lowed by a write in the DR register,holding the SCL line low(see Figure 45 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets: – EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication: after writing the last byte to the DR register, set the STOP bit to gener- ate the Stop condition. The interface goes auto- matically back to slave mode (M/SL bit cleared). Error Cases – BERR : Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set. – AF : Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit. – ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared). Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible «0» bits transmitted last. It is then neces- sary to release both lines by software.

Figure 45. Transfer Sequencing EV1: EVF=1, ADSL=1, cleared by reading SR1 register. EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. STOP=1, STOP=0, the subsequent EV4 is not seen. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.

11.4.5 Low Power Modes

11.4.6 Interrupts

Figure 46. Event Flags and Interrupt Generation the same interrupt vector (see Interrupts chapter). ister is reset (RIM instruction). WAIT No effect on I2C interface. I2C interrupts cause the device to exit from WAIT mode. resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability. *EVF can also be set by EV6 or an error from the SR2 register.

ST72104G, ST72215G, ST72216G, ST72254G I2C BUS INTERFACE (Cont’d)

11.4.7 Register Description

I2C CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h) Bit 7:6 = Reserved. Forced to 0 by hardware. Bit 5 =PE Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Notes: – When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0 – When PE=1, the corresponding I/O pins are se- lected by hardware as alternate functions. – To enable the I 2C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). Bit 4 =ENGC Enable General Call. This bit is set and cleared by software. It is also cleared by hardware when the interface is disa- bled (PE=0). The 00h General Call address is ac- knowledged (01h ignored). 0: General Call disabled 1: General Call enabled Bit 3 =START Generation of a Start condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disa- bled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). – In master mode: 0: No start generation 1: Repeated start generation – In slave mode: 0: No start generation 1: Start generation when the bus is free Bit 2 =ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disa- bled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received Bit 1 =STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). – In master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. – In slave mode: 0: No stop generation 1: Release the SCL and SDA lines after the cur- rent byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software. Bit 0 =ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 46 for the relationship between the events and the interrupt. SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See Figure 45) is de- tected. 0 0 PE ENGC START ACK STOP ITE

ST72104G, ST72215G, ST72216G, ST72254G I2C BUS INTERFACE (Cont’d) I2C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) Bit 7 =EVF Event flag. This bit is set by hardware as soon as an event oc- curs. It is cleared by software reading SR2 register in case of error event or as described in Figure 45. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: – BTF=1 (Byte received or transmitted) – ADSL=1 (Address matched in Slave mode while ACK=1) – SB=1 (Start condition generated in Master mode) – AF=1 (No acknowledge received after byte transmission) – STOPF=1 (Stop condition detected in Slave mode) – ARLO=1 (Arbitration lost in Master mode) – BERR=1 (Bus error, misplaced Start or Stop condition detected) – ADD10=1 (Master has sent header byte) – Address byte successfully transmitted in Mas- ter mode. Bit 6 =ADD10 10-bit addressing in Master mode. This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when the pe- ripheral is disabled (PE=0). 0: No ADD10 event occurred. 1: Master has sent first address byte (header) Bit 5 =TRA Transmitter/Receiver. When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after de- tection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disa- bled (PE=0). 0: Data byte received (if BTF=1) 1: Data byte transmitted Bit 4 =BUSY Bus busy. This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. This information is still updat- ed when the interface is disabled (PE=0). 0: No communication on the bus 1: Communication ongoing on the bus Bit 3 =BTF Byte transfer finished. This bit is set by hardware as soon as a byte is cor- rectly received or transmitted with interrupt gener- ation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR reg- ister. It is also cleared by hardware when the inter- face is disabled (PE=0). – Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 45). BTF is cleared by reading SR1 register followed by writ- ing the next byte in DR register. – Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded Bit 2 =ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received slave address matched with the OAR register con- tent or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software read- ing SR1 register or by hardware when the inter- face is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched EVF ADD10 TRA BUSY BTF ADSL M/SL SB

ST72104G, ST72215G, ST72216G, ST72254G I2C BUS INTERFACE (Cont’d) Bit 1 =M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0 =SB Start bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disa- bled (PE=0). 0: No Start condition 1: Start condition generated I 2C STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h) Bit 7:5 = Reserved. Forced to 0 by hardware. Bit 4 =AF Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while AF=1. 0: No acknowledge failure 1: Acknowledge failure Bit 3 =STOPF Stop detection (Slave mode). This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected Bit 2 =ARLO Arbitration lost. This bit is set by hardware when the interface los- es the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by soft- ware reading SR2 register or by hardware when the interface is disabled (PE=0). After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Bit 1 =BERR Bus error. This bit is set by hardware when the interface de- tects a misplaced Start or Stop condition. An inter- rupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the in- terface is disabled (PE=0). The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Bit 0 =GCAL General Call (Slave mode). This bit is set by hardware when a general call ad- dress is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0). 0: No general call address detected on bus 1: general call address detected on bus 0 0 0 AF STOPF ARLO BERR GCAL

ST72104G, ST72215G, ST72216G, ST72254G I2C BUS INTERFACE (Cont’d) I2C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) Bit 7 =FM/SM Fast/Standard I2C mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I 2C mode 1: Fast I2C mode Bit 6:0 =CC6-CC0 7-bit clock divider. These bits select the speed of the bus (FSCL ) de- pending on the I2C mode. They are not cleared when the interface is disabled (PE=0). – Standard mode (FM/SM=0): FSCL <= 100kHz FSCL =F CPU /(2x([CC6..CC0]+2)) – Fast mode (FM/SM=1): FSCL > 100kHz FSCL =F CPU /(3x([CC6..CC0]+2)) Note: The programmed FSCL assumes no load on SCL and SDA lines. I2C DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h) Bit 7:0 =D7-D0 8-bit Data Register. These bits contain the byte to be received or trans- mitted on the bus. – Transmitter mode: Byte transmission start auto- matically when the software writes in the DR reg- ister. – Receiver mode: the first data byte is received au- tomatically in the DR register using the least sig- nificant bit of the address. Then, the following data bytes are received one by one after reading the DR register. FM/SM CC6 CC5 CC4 CC3 CC2 CC1 CC0 D7 D6 D5 D4 D3 D2 D1 D0

ST72104G, ST72215G, ST72216G, ST72254G I2C BUS INTERFACE (Cont’d) I2C OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h) 7-bit Addressing Mode Bit 7:1 =ADD7-ADD1 Interface address. These bits define the I2C bus address of the inter- face. They are not cleared when the interface is disabled (PE=0). Bit 0 =ADD0 Address direction bit. This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). Note: Address 01h is always ignored. 10-bit Addressing Mode Bit 7:0 =ADD7-ADD0 Interface address. These are the least significant bits of the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). I 2C OWN ADDRESS REGISTER (OAR2) Read / Write Reset Value: 0100 0000 (40h) Bit 7:6 =FR1-FR0 Frequency bits. These bits are set by software only when the inter- face is disabled (PE=0). To configure the interface to I2C specifed delays select the value corre- sponding to the microcontroller frequency FCPU . Bit 5:3 = Reserved Bit 2:1 =ADD9-ADD8 Interface address. These are the most significant bits of the I2C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE=0). Bit 0 = Reserved. ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 FR1 FR0 0 0 0 ADD9 ADD8 0 FCPU Range (MHz) FR1 FR0 2.5 - 6 0 0 6 -10 0 1 10 - 14 1 0 14 - 24 1 1

Table 17. I2C Register Map and Reset Values

11.5.1 Introduction

levels from up to 16 different sources. through a Control/Status Register.

11.5.2 Main Features

The block diagram is shown in Figure 47.

11.5.3 Functional Description

11.5.3.1 Analog Power Supply

loaded or badly decoupled power supply lines. Figure 47. ADC Block Diagram CH2 CH1CH3COCO 0 ADON 0 CH0 ADCCSR

11.5.3.2 Digital A/D Conversion Result

and never increases if the analog input does not. scale) without overflow indication. version result in the DR register is 00h. the conversion is stored in the ADCDR register.

11.5.3.3 A/D Conversion Phases

analog to digital conversion accuracy. pin in case of single input channel measurement.

11.5.3.4 Software Procedure

tions and to Figure 48 for the timings. clock periods (1/fADC =2/fCPU ). sion of the selected channel. – The COCO bit is set by hardware. – No interrupt is generated. valid until the next conversion has ended. Figure 48. ADC Conversion Timings

11.5.4 Low Power Modes

and between single shot conversions.

11.5.5 Interrupts

curate conversions can be performed.

ST72104G, ST72215G, ST72216G, ST72254G 8-BIT A/D CONVERTER (ADC) (Cont’d)

11.5.6 Register Description

CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) Bit 7 =COCO Conversion Complete This bit is set by hardware. It is cleared by soft- ware reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register Bit 6 =Reserved. must always be cleared. Bit 5 =ADON A/D Converter On This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bit 4 =Reserved. must always be cleared. Bit 3:0 =CH[3:0]Channel Selection These bits are set and cleared by software. They select the analog input to convert. *Note: The number of pins AND the channel selec- tion varies according to the device. Refer to the de- vice pinout. DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h) Bit 7:0 =D[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Note: Reading this register reset the COCO flag. COCO 0 ADON 0 CH3 CH2 CH1 CH0 Channel Pin* CH3 CH2 CH1 CH0 AIN0 0 0 0 0 AIN1 0 0 0 1 AIN2 0 0 1 0 AIN3 0 0 1 1 AIN4 0 1 0 0 AIN5 0 1 0 1 AIN6 0 1 1 0 AIN7 0 1 1 1 AIN8 1 0 0 0 AIN9 1 0 0 1 AIN10 1 0 1 0 AIN11 1 0 1 1 AIN12 1 1 0 0 AIN13 1 1 0 1 AIN14 1 1 1 0 AIN15 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0

Table 18. ADC Register Map and Reset Values

12 INSTRUCTION SET

12.1 ST7 ADDRESSING MODES

Table 19. ST7 Addressing Mode Overview

ST72104G, ST72215G, ST72216G, ST72254G ST7 ADDRESSING MODES (Cont’d)

12.1.1 Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation.

12.1.2 Immediate

Immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value.

12.1.3 Direct

In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub- modes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF address- ing space. Direct (long) The address is a word, thus allowing 64 Kbyte ad- dressing space, but requires 2 bytes after the op- code.

12.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte ad- dressing space and requires 2 bytes after the op- code.

12.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (point- er). The pointer address follows the opcode. The indi- rect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations

12.1.6 Indirect Indexed (Short, Long)

er address follows the opcode. and requires 1 byte after the opcode. and requires 1 byte after the opcode. Table 20. Instructions Supporting Direct,

12.1.7 Relative mode (Direct, Indirect)

The offset follows the opcode.

ST72104G, ST72215G, ST72216G, ST72254G

12.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available op- codes for an 8-bit CPU (256 opcodes), three differ- ent prebyte opcodes are defined. These prebytes modify the meaning of the instruction they pre- cede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the ef- fective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a Y one. PIX 92 Replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed ad- dressing mode to an instruction using indirect X in- dexed addressing mode. PIY 91 Replace an instruction using X in- direct indexed addressing mode by a Y one. Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Code Condition Flag modification SIM RIM SCF RCF

ST72104G, ST72215G, ST72216G, ST72254G INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >

ST72104G, ST72215G, ST72216G, ST72254G INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2’s compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z

13 ELECTRICAL CHARACTERISTICS

13.1 PARAMETER CONDITIONS

13.1.1 Minimum and Maximum values

times the standard deviation (mean±3Σ).

13.1.2 Typical values

guidelines and are not tested.

13.1.3 Typical curves

given only as design guidelines and are not tested.

13.1.4 Loading capacitor

measurement are shown in Figure 49. Figure 49. Pin loading conditions

13.1.5 Pin input voltage

vice is described in Figure 50. Figure 50. Pin input voltage

ST72104G, ST72215G, ST72216G, ST72254G

13.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

13.2.1 Voltage Characteristics

13.2.2 Current Characteristics

13.2.3 Thermal Characteristics

Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to V DD or VSS according to their reset configuration. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN)specification. A positive injection is induced by VIN>V DD while a negative injection is induced by VIN<V SS . 3. All power (VDD ) and ground (VSS ) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. When several inputs are submitted to a current injection, the maximumΣI INJ(PIN)is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterisation withΣ IINJ(PIN)maxi- mum current injection on four I/O port pins of the device. 6. True open drain I/O port pins do not accept positive injection. Symbol Ratings Maximum value Unit VDD -V SS Supply voltage 6.5 V VIN Input voltage on any pin1) & 2) V SS -0.3 to VDD +0.3 VESD(HBM) Electro-static discharge voltage (Human Body Model)see Section 13.7.2 ”Absolute Elec- trical Sensitivity” on page 110V ESD(MM) Electro-static discharge voltage (Machine Model) Symbol Ratings Maximum value Unit IVDD Total current into VDD power lines (source)3) 80 mA IVSS Total current out of VSS ground lines (sink)3) 80 IIO Output current sunk by any standard I/O and control pin 25 Output current sunk by any high sink I/O pin 50 Output current source by any I/Os and control pin - 25 I INJ(PIN) 2) & 4) Injected current on ISPSEL pin ± 5 Injected current on RESET pin ± 5 Injected current on OSC1 and OSC2 pins ± 5 Injected current on any other pin5) & 6) ± 5 ΣIINJ(PIN)2) Total injected current (sum of all I/O and control pins)5) ± 20 Symbol Ratings Value Unit TSTG Storage temperature range -65 to +150 °C TJ Maximum junction temperature (see Section 14.2 ”THERMAL CHARACTERISTICS” on page 127 )

13.3 OPERATING CONDITIONS

13.3.1 General Operating Conditions

Figure 51. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for ROM devices2) Figure 52. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for FLASH devices2)

1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
2. Operating conditions with T
3. FLASH programming tested in production at maximum TA with two different conditions: VDD =5.5V, fCPU =8MHz and

1 Suffix Version 0 70

6 Suffix Version -40 85

7 Suffix Version -40 105

3 Suffix Version -40 125

13.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for VDD ,fOSC , and TA . Figure 53. High LVD Threshold Versus VDD and fOSC for FLASH devices3) Figure 54. Medium LVD Threshold Versus VDD and fOSC for FLASH devices3) Figure 55. Low LVD Threshold Versus VDD and fOSC for FLASH devices2)

1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2. Data based on characterization results, not tested in production.
3. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.

13.4 SUPPLY CURRENT CHARACTERISTICS

13.4.1 RUN and SLOW Modes

Figure 59. Typical I

1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals

in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.

1. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or

V SS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.

13.4.2 WAIT and SLOW WAIT Modes

Figure 61. Typical IDD in WAIT vs. fCPU Figure 62. Typical IDD in SLOW-WAIT vs. fCPU

1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1)

driven by external square wave, CSS and LVD disabled.

1. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at

ST72104G, ST72215G, ST72216G, ST72254G SUPPLY CURRENT CHARACTERISTICS (Cont’d)

13.4.3 HALT Mode

13.4.4 Supply and Clock Managers

The previous current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- vice consumption, the two current values must be added (except for HALT mode).

13.4.5 On-Chip Peripherals

Notes: 1. Typical data are based on TA=25°C. 2. All I/O pins in input mode with a static value at VDD or VSS (no load), CSS and LVD disabled. Data based on charac- terization results, tested in production at VDD max. and fCPU max. 3. Data based on characterization results, not tested in production. 4. Data based on characterization results done with the external components specified in Section 13.5.3 and Section 13.5.4, not tested in production. 5. As the oscillator is based on a current source, the consumption does not depend on the voltage. 6. Data based on a differential IDD measurement between reset configuration (timer counter running at fCPU /4) and timer counter stopped (selecting external clock capability). Data valid for one timer. 7. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica- tion (data sent equal to 55h). 8. Data based on a differential IDD measurement between reset configuration and I2C peripheral enabled (PE bit set). 9. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. Symbol Parameter Condition s Typ 1) Max Unit IDD Supply current in HALT mode2) VDD =5.5V -40°C ≤TA≤+85°C µA-40°C ≤TA≤+125°C5 0 VDD =3.6V -40°C ≤TA≤+85°C6 Symbol Parameter Conditions Typ 1) Max 3) Unit IDD(CK) Supply current of internal RC oscillator 500 750 µA Supply current of external RC oscillator4) 525 750 Supply current of resonator oscillator4) & 5) LP: Low power oscillator MP: Medium power oscillator MS: Medium speed oscillator HS: High speed oscillator 200 300 450 700 400 550 750 1000 Clock security system supply current 150 350 I DD(LVD) LVD supply current HALT mode 100 150 Symbol Parameter Conditions Typ Unit IDD(TIM) 16-bit Timer supply current6) fCPU =8MHz VDD =3.3V 50 µA VDD =5.0V 150 IDD(SPI) SPI supply current7) fCPU =8MHz VDD =3.3V 250 VDD =5.0V 350 IDD(I2C) I2C supply current8) fCPU =8MHz VDD =3.3V 250 VDD =5.0V 350 IDD(ADC) ADC supply current when converting9) fADC =4MHz VDD =3.3V 800 VDD =5.0V 1100

13.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD ,fOSC , and TA .

13.5.1 General Timings

13.5.2 External Clock Source

Figure 63. Typical Application with an External Clock Source

1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch.Δtc(INST)is the number of tCPU cycles needed to finish

the current instruction execution.

1. Data based on design simulation and/or technology characteristics, not tested in production.

13.5.3 Crystal and Ceramic Resonator Oscillators

Figure 64. Typical Application with a Crystal or Ceramic Resonator

1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. tSU(OSC) is the typical oscillator start-up time measured between VDD =2.8V and the fetch of the first instruction (with a

quick VDD ramp-up from 0 to 5V (<50µs).

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.

Refer to crystal/ceramic resonator manufacturer for more details.

2 OSC2 driving current

13.5.4 RC Oscillators

Figure 65. Typical Application with RC oscillator Figure 66. Typical Internal RC Oscillator Figure 67. Typical External RC Oscillator

1. Data based on characterization results.
2. Guaranteed frequency range with the specified CEX and REX ranges taking into account the device process variation.

Data based on design simulation.

1. Data based on characterization results done with VDD nominal at 5V, not tested in production.
2. REX must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.

trying out several resistor values.

13.5.5 Clock Security System (CSS)

Figure 68. Typical Safe Oscillator Frequencies

1. Data based on characterization results, tested in production between 90KHz and 500KHz.
2. Filtered glitch on the fOSC signal. See functional description in Section 6.5 on page 23 for more details.

ST72104G, ST72215G, ST72216G, ST72254G

13.6 MEMORY CHARACTERISTICS

Subject to general operating conditions for VDD ,fOSC , and TA unless otherwise specified.

13.6.1 RAM and Hardware Registers

13.6.2 FLASH Program Memory

Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in in HALT mode or under RESET) or in hardware registers (only in HALT mode). Guaranteed by construction, not tested in production. 2. Data based on characterization results, tested in production at TA=25°C. 3. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block (then up to 32 bytes at a time for an 8k device) 4. The data retention time increases when the T A decreases. 5. Data based on reliability test results and monitored in production. Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode1) HALT mode (or RESET) 1.6 V Symbol Parameter Conditions Min Typ Max Unit TA(prog) Programming temperature range2) 02 5 7 0 °C tprog Programming time for 1~16 bytes3) TA =+25°C8 2 5 ms Programming time for 4 or 8kBytesTA =+25°C 2.1 6.4 sec tret Data retention5) TA =+55°C 4) 20 years N RW Write erase cycles5) TA =+25°C 100 cycles

13.7 EMC CHARACTERISTICS

sis during product characterization.

13.7.1 Functional EMS

until a failure occurs (indicated by the LEDs). conforms with the IEC 1000-4-2 standard. Figure 69. EMC Recommended star network power supply connection

1. Data based on characterization results, not tested in production.
2. The suggested 10nF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC

dations are given in other sections (I/Os, RESET, OSCx pin characteristics).

13.7.2 Absolute Electrical Sensitivity

fer to the AN1181 ST7 application note.

13.7.2.1 Electro-Static Discharge (ESD)

conforms to the JESD22-A114A/A115A standard. See Figure 70 and the following test sequences. – S1 switches position from generator to R. prior to the delivery of the next pulse. – S1 switches position from generator to ST7. prior to the delivery of the next pulse. sures a slow discharge of the ST7. Figure 70. Typical Equivalent ESD Circuits

1. Data based on characterization results, not tested in production.

13.7.2.2 Static and Dynamic Latch-Up

on 10 parts to assess the latch-up performance. refer to the AN1181 ST7 application note. Figure 71. Simplified Diagram of the ESD Generator for DLU

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-

JEDEC criteria (international standard).

1. Schaffner NSG435 with a pointed test finger.

13.7.3 ESD Pin Protection Strategy

or heating within their structure. Figure 72. Positive Stress on a Standard Pad vs. VSS Figure 73. Negative Stress on a Standard Pad vs. VDD

13.8 I/O PORT PIN CHARACTERISTICS

13.8.1 General Characteristics

Subject to general operating conditions for VDD ,fOSC , and TA unless otherwise specified. Figure 77. Two typical Applications with unused I/O Pin Figure 78. Typical IPU vs. VDD with VIN=VSS

1. Unless otherwise specified, typical data are based on TA=25°C and VDD =5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

characteristics, not tested in production. scribed in Figure 78). This data is based on characterization results, tested in production at VDD max.

1. Data based on characterization results, not tested in production.
2. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

13.8.2 Output Driving Current

Subject to general operating conditions for VDD ,fOSC , and TA unless otherwise specified. Figure 79. Typical VOL at VDD =5V (standard) Figure 80. Typical VOL at VDD =5V (high-sink) Figure 81. Typical VDD -VOH at VDD =5V

1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS .

1. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of

IIO (I/O ports and control pins) must not exceed IVDD . True open drain I/O pins does not have VOH .

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD ,fOSC , and TA unless otherwise specified. Figure 85. Typical Application with RESET pin8)

1. Unless otherwise specified, typical data are based on TA=25°C and VDD =5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS .

1. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-

scribed in Figure 86). This data is based on characterization results, not tested in production.

1. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin.
2. All short pulse applied on RESET pin with a duration below th(RSTL)incan be ignored.
3. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
4. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

13.9.2 ISPSEL Pin

Subject to general operating conditions for VDD ,fOSC , and TA unless otherwise specified. Figure 89. Two typical Applications with ISPSEL Pin2)

1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When the ISP Remote mode is not required by the application ISPSEL pin must be tied to VSS .

ST72104G, ST72215G, ST72216G, ST72254G

13.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for VDD , fOSC , and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).

13.10.1 Watchdog Timer

13.10.2 16-Bit Timer Symbol Parameter Conditions Min Typ Max Unit tw(WDG) Watchdog time-out duration 12,288 786,432 t CPU fCPU =8MHz 1.54 98.3 ms Symbol Parameter Conditions Min Typ Max Unit tw(ICAP)in Input capture pulse time 1 t CPU tres(PWM) PWM resolution time 2t CPU fCPU =8MHz 250 ns fEXT Timer external clock frequency 0 f CPU /4 MHz fPWM PWM repetition rate 0 f CPU /4 MHz ResPWM PWM resolution 16 bit

13.11 COMMUNICATION INTERFACE CHARACTERISTICS

13.11.1 SPI - Serial Peripheral Interface

fOSC , and TA unless otherwise specified. Figure 90. SPI Slave Timing Diagram with CPHA=03)

1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD .

13.11.2 I2C - Inter IC Control Interface

fOSC , and TA unless otherwise specified. protocol described in the following table. Figure 93. Typical Application with I2C Bus and Timing Diagram4)

1. Data based on standard I2C protocol requirement, not tested in production.
2. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined

region of the falling edge of SCL.

1. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of
2. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD .

Subject to general operating conditions for VDD ,fOSC , and TA unless otherwise specified. Figure 94. Typical Application with ADC

1. Unless otherwise specified, typical data are based on TA=25°C and VDD -VSS =5V. They are given only as design guide-
2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS .
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ ). Data

based on characterization results, not tested in production.

1. The stabilization time of the AD converter is masked by the first tLOAD . The first conversion after the enable is then

Figure 95. ADC Accuracy Characteristics

1. ADC Accuracy vs. Negative Injection Current:

DD supply, and worst case temperature.

1. Data based on characterization results over the whole temperature range, monitored in production.

1 LSBIDEAL

between the actual and the ideal transfer curves. transition and the first ideal one. transition and the last actual one. between actual steps and the ideal one.

14 PACKAGE CHARACTERISTICS

14.1 PACKAGE MECHANICAL DATA

Figure 96. 32-Pin Shrink Plastic Dual In Line Package Figure 97. 28-Pin Plastic Small Outline Package, 300-mil Width

ST72104G, ST72215G, ST72216G, ST72254G

14.2 THERMAL CHARACTERISTICS

Notes: 1. The power dissipation is obtained from the formula PD =P INT+P PORT where PINT is the chip internal power (IDD xVDD ) and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ =T A +P D x RthJA. Symbol Ratings Value Unit R thJA Package thermal resistance (junction to ambient) SDIP32 SO28 °C/W PD Power dissipation1) 500 mW TJmax Maximum junction temperature2) 150 °C

14.3 SOLDERING AND GLUEABILITY INFORMATION

as design guidelines in Figure 98 and Figure 99. Figure 98. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) Figure 99. Recommended Reflow Soldering Oven Profile (MID JEDEC)

14.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL

Table 21. Suggested List of SDIP32 Socket Types Table 22. Suggested List of SO28 Socket Types

15 DEVICE CONFIGURATION AND ORDERING INFORMATION

15.1 OPTION BYTES

ration of the microcontroller to be selected. Bit 7:2 =Reserved, must always be 1. External Interrupt Configuration. ping to be configured as shown in Table 23. Table 23. External Interrupt Configuration Bit 0 =FMP Full memory protection. of the whole memory (including the option byte). main oscillator as shown in Table 24. lected threshold as shown in Table 25. This option bit selects the watchdog type. Table 24. Main Oscillator Configuration Table 25. LVD Threshold Configuration

0 LVD1 LVD0 WDG

15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE

Figure 100. ROM Factory Coded Device Types Figure 101. FLASH User Programmable Device Types

ST72104G, ST72215G, ST72216G, ST72254G TRANSFER OF CUSTOMER CODE (Cont’d) MICROCONTROLLER OPTION LIST STMicroelectronics references Device: [ ] ST72104G1 [ ] ST72215G2 [ ] ST72254G1 [ ] ST72104G2 [ ] ST72216G1 [ ] ST72254G2 [ ] SO28 with Tape & Reel conditionning External Interrupt: [ ] IT0 interrupt vector Port A, IT1 interrupt vector Port B & C [ ] IT0 interrupt vector Port A & C, IT1 interrupt vector Port B Temperature Range: [ ] 0 °Ct o+7 0°C[ ] - 4 0 °C to + 105°C Clock Source Selection: [ ] Resonator: [ ] LP: Low power resonator (1 to 2 MHz) [ ] MP: Medium power resonator (2 to 4 MHz) [ ] MS: Medium speed resonator (4 to 8 MHz) [ ] HS: High speed resonator (8 to 16 MHz) [ ] RC Network: [ ] Internal [ ] External [ ] External Clock Clock Security System: [ ] Disabled [ ] Enabled Watchdog Selection: [ ] Software Activation [ ] Hardware Activation Halt when Watchdog on: [ ] Reset [ ] No reset Readout Protection: [ ] Disabled [ ] Enabled LVD Reset [ ] Disabled [ ] Enabled: [ ] Highest threshold (4.05V/4.30V) [ ] Medium threshold (3.65V/3.90V) [ ] Lowest threshold (3.10V/3.35V)

15.3 DEVELOPMENT TOOLS

ers, emulators and gang programmers. port: see Table 26 and Table 27 for more details. Table 26. STMicroelectronic Tool Features Table 27. Dedicated STMicroelectronics Development Tools

1. In-Situ Programming (ISP) interface for FLASH devices.

ST72104G, ST72215G, ST72216G, ST72254G

15.4 ST7 APPLICATION NOTES

15.5 TO GET MORE INFORMATION

To get the latest information on this product please use the ST web server.ß http://mcu.st.com/ Identification Description PROGRAMMING AND TOOLS AN985 Executing code in ST7 RAM AN986 Using the ST7 indirect addressing mode AN987 ST7 in-circuit programming AN988 Starting with ST7 assembly tool chain AN989 Starting with ST7 Hiware C AN1039 ST7 math utility routines AN1064 Writing optimized hiware C language for ST7 AN1179 Programming ST7 Flash Microcontrollers in Remote ISP Mode (In-Situ Programming) EXAMPLE DRIVERS AN969 ST7 SCI communication between the ST7 and a PC AN970 ST7 SPI communication between the ST7 and E PROM AN971 ST7 I C communication between the ST7 and E PROM AN972 ST7 software SPI master communication AN973 SCI software communication with a PC using ST72251 16-bit timer AN974 Real time clock with the ST7 timer output compare AN976 Driving a buzzer using the ST7 PWM function AN979 Driving an analog keyboard with the ST7 ADC AN980 ST7 keypad decoding techniques, implementing wake-up on keystroke AN1017 Using the ST7 USB microcontroller AN1041 Using ST7 PWM signal to generate analog output (sinusoid) AN1042 ST7 routine for I C slave mode management AN1044 Multiple interrupt sources management for ST7 MCUs AN1045 ST7 software implementation of I C bus master AN1047 Managing reception errors with the ST7 SCI peripheral AN1048 ST7 software LCD driver AN1048 ST7 timer PWM duty cycle switch for true 0% or 100% duty cycle PRODUCT OPTIMIZATION AN982 Using ceramic resonators with the ST7 AN1014 How to minimize the ST7 power consumption AN1070 ST7 checksum selfchecking capability PRODUCT EVALUATION AN910 ST7 and ST9 performance benchmarking AN990 ST7 benefits versus industry standard AN1181 Electrostatic discharge sensitivity measurement APPLICATION EXAMPLES AN1086 ST7 / ST10U435 CAN-Do solutions for car multiplexing

ST72104G, ST72215G, ST72216G, ST72254G

16 SUMMARY OF CHANGES

Description of the changes between the current release of the specification and the previous one. Rev. Main changes Date 2.2 Power saving mode corrected in Figure 18 on page 28 and Figure 20 on page 29. Feb-00

ST72104G, ST72215G, ST72216G, ST72254G Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics  2000 STMicroelectronics - All Rights Reserved. Purchase of I 2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http:// www.st.com