ST7LITEUS5

8-bit MCU with single voltage Flash memory, ADC, timers

Document overview

• Manufacturer or author: STMICROELECTRONICS
• PDF pages: 136

Technical content

Datasheet sections

• 1 Introduction
• 2 Pin description
• 3 Register and memory map
• 4 Flash program memory
• 4.1 Introduction
• 4.2 Main features
• 4.3 Programming modes
• 4.3.1 In-circuit programming (ICP)
• 4.3.2 In application programming (IAP)
• 4.4 I 2C interface
• 4.5 Memory protection
• 4.5.1 Readout protection
• 4.5.2 Flash Write/Erase protection
• 4.6 Related documentation
• 4.7 Register description
• 4.7.1 Flash Control/Status register (FCSR)
• 5 Central processing unit
• 5.1 Introduction
• 5.2 Main features
• 5.3 CPU registers
• 5.3.1 Accumulator (A)
• 5.3.2 Index registers (X and Y)
• 5.3.3 Program counter (PC)
• 5.3.4 Condition Code register (CC)
• 5.3.5 Stack Pointer (SP)
• 6 Supply, reset and clock management
• 6.1 Main features
• 6.2 Internal RC oscillator adjustment

Features

■ Memories – 1 Kbytes single-voltage Flash Program memory with readout protection, ICP and IAP)

10 K write/erase cycles guaranteed

data retention: 20 years at 55 °C – 128 bytes RAM ■ Clock, Reset and Supply management – 3-level low-voltage supervisor (LVD) and auxiliary voltage detector (AVD) for safe power-on/off – Clock sources: internal trimmable 8 MHz RC oscillator, internal low power, low frequency RC oscillator or external clock – Five power saving modes: Halt, Auto- wakeup from Halt, Active-halt, Wait, Slow ■ Interrupt management – 11 interrupt vectors plus TRAP and RESET – 5 external interrupt lines (on 5 vectors) ■ I/O ports – 5 multifunctional bidirectional I/O lines – 1 additional Output line – 6 alternate function lines – 5 high sink outputs ■ 2 Timers – One 8-bit Lite timer (LT) with prescaler including: watchdog, one realtime base and one 8-bit input capture. – One 12-bit auto-reload timer (AT) with output compare function and PWM ■ A/D Converter – 10-bit resolution for 0 to V DD – 5 input channels ■ Instruction Set – 8-bit data manipulation – 63 basic instructions with illegal opcode detection – 17 main addressing modes – 8x8 unsigned multiply instruction ■ Development Tools – Full hardware/software development package – Debug module Plastic DIP8 SO8 150” DFN8 Plastic DIP16 Table 1. Device summary

1. For development or tool prototyping purpos es only. Not orderable in production quantities.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Contents Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Contents ST7LITEUS2, ST7LITEUS5 Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Contents Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Contents ST7LITEUS2, ST7LITEUS5 Obsolete Product(s) - Obsolete Product(s)

Table 39. Instructions supporting direct, indexed, indi rect and indirect indexed addressing modes . 87

Table 71. 8-pin plastic small outline package, 150-mil width, package mechanical Table 73. 16-pin plastic dual in-line package, 300-mil width, package mechanical

1 Introduction

Programming (ICP) and In-Application Programming (IAP) capability. Halt mode, reducing power consumption when the application is in idle or standby state. feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data are located in Section 12 on page 92. The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD). 2C protocol reference manual. Figure 1. General block diagram

1 KByte

2 Pin description

Figure 2. 8-pin SO and Pl astic DIP package pinout

1. HS: High sink capability.
2. eix : associated external interrupt vector

Figure 3. 8-pin DFN package pinout

1. HS: High sink capability.
2. eix : associated external interrupt vector

Figure 4. 16-pin package pinout

1. Reserved pins must be tied to ground.
2. The differences versus the 8- pin packages are listed below:

The I2C signals (ICCCLK and ICCDATA) are mapped on dedicated pins. The RESET signal is mapped on a dedicated pin. It is not multiplexed with PA3.

• Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog
• Output: OD = open drain, PP = push-pull The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 2. Device pin description

2 PA5/AIN4/CLKIN I/

4 PA3/RESET (1) O X X X Port A3 RESET (1)

5 PA2/AIN2/LTIC I/

6 PA1/AIN1/

mandatory in noisy environment).

7 PA0/AIN0/ATPW

1. After a reset, the multiplexed PA3/RESET pin will act as RESET. To configure this pin as output (Port A3), write 55h to

MUXCR0 and AAh to MUXCR1. For further details, please refer to Section 6.5 on page 37.

3 Register and memory map

The highest address bytes contain the user reset and interrupt vectors. addressing space so the reset and interrupt vectors are located in Sector 0 (FE00h-FFFFh). The size of Flash Sector 0 and other device options are configurable by option byte. Figure 5. Memory map

1. See Section 6.2 on page 28 for the description of RCCRHx registers.

0.5 Kbytes

Table 3. Hardware register map (1)

1. Legend: x=undefined, R/W=read/write
2. The contents of the I/O port DR registers are readable only in out put configuration. In input configuration, the values of the

I/O pins are returned instead of the DR register contents.

1. The bits associated with unavailable pi ns must always keep their reset value.
2. For a description of the DM registers, see the ST7 I 2C Protocol Reference Manual.

Table 3. Hardware register map (continued) (1)

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Flash program memory ST7LITEUS2, ST7LITEUS5

4 Flash program memory

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on- board using in-circuit programming or in-application programming. The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main features

• ICP (in-circuit programming)
• IAP (in-application programming)
• ICT (in-circuit testing) for downloading and executing user application test patterns in RAM
• Sector 0 size configurable by option byte
• Readout and write protection

4.3 Programming modes

The ST7 can be programmed in three different ways:

• Insertion in a programming tool In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased.
• In-circuit programming In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board.
• In-application programming In this mode, sector 1 can be programmed or erased without removing the device from the application board and while the application is running.

4.3.1 In-circuit programming (ICP)

ICP uses a protocol called I2C (in-circuit communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps:

• Switch the ST7 to I2C mode. This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters I2C mode, it fetches a specific RESET vector which points to the ST7 system memory containing Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Flash program memory the I2C protocol routine. This routine enables the ST7 to receive bytes from the I2C interface.

• Download ICP driver code in RAM from the ICCDATA pin
• Execute ICP driver code in RAM to program the FLASH memory Depending on the ICP driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In application programming (IAP)

This mode uses an IAP driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc). IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation.

4.4 I 2C interface

ICP needs a minimum of 4 and up to 6 pins to be connected to the programming tool. These pins are:

• RESET: device reset
• VSS: device power supply ground
• ICCCLK: I2C output serial clock pin
• ICCDATA: I2C input serial data pin
• CLKIN: main clock input for external source
• VDD: application board power supply Refer to Figure 6 for a description of the I2C interface. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the programming tool is plugged to the board, even if an I2C session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the programming tool documentation for recommended resistor values. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5 mA at high level (push pull output or pull-up resistor<1 kΩ). A schottky diode can be used to isolate the application RESET circuit in this case. When using a classical RC network with R>1 kΩ or a reset management IC with open drain output and pull-up resistor>1 kΩ, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the I 2C session. The use of Pin 7 of the I2C connector depends on the programming tool architecture. This pin must be connected when using most ST programming tools (it is used to monitor the application power supply). Please refer to the programming tool manual. Obsolete Product(s) - Obsolete Product(s)

selected, the AWU RC oscillator is provided. PA3 for application reasons. reset will put it back in input pull-up. Figure 6. Typical I

4.5 Memory protection

Protection which can be applied individually.

4.5.1 Readout protection

general purpose microcontroller. Program memory is protected.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Flash program memory In flash devices, this protection is removed by reprogramming the option. In this case, program memory is automatically erased, and the device can be reprogrammed. Readout protection selection depends on the device type:

• In Flash devices it is enabled and removed through the FMP_R bit in the option byte.
• In ROM devices it is enabled by mask option specified in the option list.

4.5.2 Flash Write/Erase protection

Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6 Related documentation

For details on Flash programming and I2C protocol, refer to the ST7 Flash programming reference manual and to the ST7 I2C protocol reference manual. Obsolete Product(s) - Obsolete Product(s)

4.7 Register description

4.7.1 Flash Control/St atus register (FCSR)

00000 O P T L A T P G M

Table 4. FLASH register map and reset values

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Central processing unit

5 Central processing unit

5.1 Introduction

This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation.

5.2 Main features

• 63 basic instructions
• Fast 8-bit by 8-bit multiply
• 17 main addressing modes
• Two 8-bit index registers
• 16-bit stack pointer
• Low power modes
• Maskable hardware interrupts
• Non-maskable software interrupt

5.3 CPU registers

The six CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions.

5.3.1 Accumulator (A)

The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.

5.3.2 Index registers (X and Y)

In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (The cross-assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).

5.3.3 Program counter (PC)

The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (program counter low which is the LSB) and PCH (program counter high which is the MSB). Obsolete Product(s) - Obsolete Product(s)

Figure 7. CPU registers

5.3.4 Condition Co de register (CC)

These bits can be individually tested and/or controlled by specific instructions.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Central processing unit Bit 7:5 Set to ‘1’ Bit 4 H Half carry This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 3 I Interrupt mask This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. Bit 2 N Negative This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instructions. Bit 1 Z Zero This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Central processing unit ST7LITEUS2, ST7LITEUS5

5.3.5 Stack Pointer (SP)

Reset value: 00 FFh The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 64 bytes deep, the 10 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP5 to SP0 bits are set) which is the stack higher address. The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP . Then the other registers are stored in the next locations as shown in Figure 8.

• When an interrupt is received, the SP is decremented and the context is pushed on the stack.
• On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call is located at two locations and an interrupt five locations in the stack area. 15 8 00000000 Read/write 7 0 1 1 SP5 SP4 SP3 SP2 SP1 SP0 Read/write Obsolete Product(s) - Obsolete Product(s)

Figure 8. Stack manipulation example

1. Stack higher address = 00FFh.
2. Stack lower address = 00C0h.

6 Supply, reset and clock management

6.1 Main features

• Clock management – 8 MHz internal RC oscillator (enabled by option byte) – External clock Input (enabled by option byte)
• Reset sequence manager (RSM)
• System integrity management (SI) – Main supply low voltage detection (LVD) with reset generation (enabled by option byte) – Auxiliary voltage detector (AVD) with interr upt capability for monitoring the main supply

6.2 Internal RC oscillator adjustment

RCCR (RC Control register) and in the bits [6:5] in the SICSR (SI Control Status register). as shown in the following table. Table 5. Predefined RC oscillator calibration values

1. DEE0h, DEE1h, DEE2h and DEE3h are located in a reserved area butare special bytes containing also

calibration values can still be obtained through these two addresses.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Supply , reset and clock management Note: 1 In I 2C mode, the internal RC oscillator is forced as a clock source, regardless of the selection in the option byte. Refer to note 5 in Section 4.4 on page 19 for further details. 2S e e Section 12: Electrical characteristics for more information on the frequency and accuracy of the RC oscillator.

3 To improve clock stability and frequency accura cy, it is recommended to place a decoupling

capacitor, typically 100nF , between the VDD and VSS pins as close as possible to the ST7 device. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN2326 for information on how to calibrate the RC frequency using an external reference signal. The ST7LITEUS2 and ST7LITEUS5 also contain an Auto-wakeup RC oscillator. This RC oscillator should be enabled to enter Auto-wakeup from Halt mode. The Auto-wakeup RC oscillator can also be configured as the startup clock through the CKSEL[1:0] option bits (see Section 14.1 on page 123). This is recommended for applications where very low power consumption is required. Switching from one startup clock to another can be done in run mode as follows (see Figure 9): Case 1 Switching from internal RC to AWU: 1. Set the RC/AWU bit in the CKCNTCSR register to enable the AWU RC oscillator 2. The RC_FLAG is cleared and the clock output is at 1. 3. Wait 3 AWU RC cycles till the AWU_FLAG is set 4. The switch to the AWU clock is made at the positive edge of the AWU clock signal 5. Once the switch is made, the internal RC is stopped Case 2 Switching from AWU RC to internal RC: 1. Reset the RC/AWU bit to enable the internal RC oscillator 2. Using a 4-bit counter, wait until 8 intern al RC cycles have elapsed. The counter is running on internal RC clock. 3. Wait till the AWU_FLAG is cleared (1AW U RC cycle) and the RC_FLAG is set (2 RC cycles) 4. The switch to the internal RC clock is made at the positive edge of the internal RC clock signal 5. Once the switch is made, the AWU RC is stopped Note: 1 When the internal RC is not selected, it is stopped so as to save power consumption.

2 When the internal RC is selected, the AWU RC is turned on by hardware when entering

Auto-wakeup from Halt mode. 3 When the external clock is selected , the AWU RC oscillator is always on. Obsolete Product(s) - Obsolete Product(s)

Figure 9. Clock switching

6.3 Register description

6.3.1 Main Clock Control/ Status register (MCCSR)

000000 M C O S M S

Bits 7:2 Reserved, mu st be kept cleared. allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general purpose I/O.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Supply , reset and clock management

6.3.2 RC Control register (RCCR)

Reset value: 1111 1111 (FFh)

6.3.3 System Integrity (SI) Co ntrol/status register (SICSR)

Reset value: 0000 0x00 (0xh) 7 0 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 Read / Write Bits 7:0 CR[9:2] RC Oscillator Frequency Adjustment Bits These bits, as well as CR[1:0] bits in the SICSR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy. The application can store the correct value for each voltage range in Flash memory and write it to this register at startup. 00h = maximum available frequency FFh = lowest available frequency Note: To tune the oscillator, write a series of different values in the register until the correct frequency is reached. The fastest method is to use a dichotomy starting with 80h. 7 0

0 CR1 CR0 0 0 LVDRF AVDF AVDIE

Bit 7 Reserved, must be kept cleared. Bits 6:5 CR[1:0] RC Oscillator Frequency Adjustment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain the required accuracy. Refer to Section 6.2 on page 28. Bits 4:3 Reserved, must be kept cleared. Bits 2:0 System Integrity bits. Refer to Section 7.4 on page 43. Obsolete Product(s) - Obsolete Product(s)

6.3.4 AVD Threshold Select ion register (AVDTHCR)

6.3.5 Clock Controller Contro l/Status register (CKCNTCSR)

Bits 4:2 Reserved, must be kept cleared. Table 6. Internal RC prescaler selection bits (1)

1. If the internal RC is used with a supply operating range below 3.3 V, a division ratio of at least 2 must be

enabled in the RC prescaler.

0000 A W U _ F L A G RC_

Bits 7:4 Reserved, mu st be kept cleared.

Bit 1 = Reserved, must be kept cleared. Table 7. Clock register map and reset values

Figure 10. Clock management block diagram

6.4 Reset sequence manager (RSM)

6.4.1 Introduction

• External RESET source pulse
• Internal LVD reset (low voltage detection)
• Internal WATCHDOG reset Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Figure 12. These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic reset sequence consists of 3 phases as shown in Figure 11:
• Active phase depending on the reset source
• 64 CPU clock cycle delay
• RESET vector fetch Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. The 64 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles.

Figure 11. Reset sequence phases

64 CLOCK CYCLES

Figure 12. Reset block diagram

1. Section 11.2.1: Illegal opcode reset for more details on illegal opcode reset conditions

6.4.2 Asynchronous external RESET pin

therefore the MCU can enter reset state even in Halt mode.

6.4.3 External Power-on reset

the minimum level specified for the selected fCLKIN frequency. RC network connected to the RESET pin.

6.4.4 Internal low voltage detector (LVD) reset

• Power-on reset
• Voltage Drop reset The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or VDD<VIT - (falling edge) as shown in Figure 13. The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets. RESET RON VDD INTERNAL RESET PULSE GENERATOR FILTER LVD RESET WATCHDOG RESET ILLEGAL OPCODE RESET 1) Obsolete Product(s) - Obsolete Product(s)

6.4.5 Internal watchdog reset

is pulled low during at least tw(RSTL)out. Figure 13. Reset sequences

6.5 Register description

6.5.1 Multiplexed I/O Reset Co ntrol register 1 (MUXCR1)

6.5.2 Multiplexed I/O Reset Co ntrol register 0 (MUXCR0)

output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1. These registers are one-time writable only.

• To configure PA3 as general purpose output: After power-on / reset, the application program has to configure the I/O port by writing to these registers as described above. Once the pin is configured as an I/O output, it cannot be changed back to a reset pin by the application code.
• To configure PA3 as RESET: An internally generated reset (such as POR, LVD, WDG, illegal opcode) will clear the two registers and the pin will act again as a reset function. Otherwise, a power-down is required to put the pin back in reset configuration.

Table 8. Multiplexed IO register map and reset values

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Interrupts

7 Interrupts

The ST7 core may be interrupted by one of two different methods: Maskable hardware interrupts as listed in the “interrupt mapping” table and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 14. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced:

• Normal processing is suspended at the end of the current instruction execution.
• The PC, X, A and CC registers are saved onto the stack.
• The I bit of the CC register is set to prevent additional interrupts.
• The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table for vector addresses). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit is cleared and the main program resumes. Priority management By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine. In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see Table 9: Interrupt mapping). Interrupts and low power mode All interrupts allow the processor to leave the Wait low power mode. Only external and specifically mentioned interrupts allow the processor to leave the Halt low power mode (refer to the “Exit from Halt” column in Table 9: Interrupt mapping).

7.1 Non maskable software interrupt

This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit. It is serviced according to the flowchart in Figure 14. Obsolete Product(s) - Obsolete Product(s)

7.2 External interrupts

automatically cleared upon entering the interrupt service routine. case of rising-edge sensitivity.

7.3 Peripheral interrupts

• The I bit of the CC register is cleared.
• The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by:
• Writing “0” to the corresponding bit in the status register or
• Access to the status register while the flag is set followed by a read or write of an associated register. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear sequence is executed.

Figure 14. Interrupt processing flowchart

7.3.1 External Interrupt C ontrol register 1 (EICR1)

Table 9. Interrupt mapping

0 AWU Auto-wakeup interrupt AWUCSR yes (1) FFFAh-FFFBh

4 Not used no FFF2h-FFF3h

7 SI AVD interrupt SICSR no FFECh-FFEDh

9 AT TIMER Overflow Interrupt ATCSR yes (3) FFE8h-FFE9h

11 LITE TIMER RTC1 Interrupt LTCSR yes (3) FFE4h-FFE5h

12 Not used no FFE2h-FFE3h

13 Not used no FFE0h-FFE1h

1. This interrupt exits the MCU from Auto-wakeup from Halt mode only.
2. This interrupt exits the MCU from Wait and Active-halt modes only. Moreover, IS4[1:0] = 01 is the only safe configuration to
3. These interrupts exit the MCU from Active-halt mode only.

These bits define the interrupt sensitivity for ei2 according to Table 10. These bits define the interrupt sensitivity for ei1 according to Table 10. These bits define the interrupt sensitivity for ei0 according to Table 10.

Note: 1 These 8 bits can be written only when the I bit in the CC register is set.

7.3.2 External Interrupt C ontrol register 2 (EICR2)

Note: 1 These 8 bits can be written only when the I bit in the CC register is set.

3 IS4[1:0] = 01 is the only safe configuration to avoid spurious interrupt in Halt and AWUFH

These bits define the interrupt sensitivity for ei1 according to Table 10. These bits define the interrupt sensitivity for ei0 according to Table 10. Table 10. Interrupt sensitivity bits

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Interrupts

7.4 System integrity management (SI)

The System Integrity Management block contains the low voltage detector (LVD) and Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register. Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Section 11.2.1: Illegal opcode reset for further details.

7.4.1 Low voltage detector (LVD)

The low voltage detector function (LVD) generates a static reset when the VDD supply voltage is below a VIT -(LVD) reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT -(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis). The LVD Reset circuitry generates a reset when V DD is below:

• VIT+(LVD) when VDD is rising
• VIT -(LVD) when VDD is falling The LVD function is illustrated in Figure 15. The voltage threshold can be configured by option byte to be low, medium or high. See Section 14.1: Option bytes. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT -(LVD), the MCU can only be in two modes:
• Under full software control
• In static safe reset In these conditions, secure operation is always ensured for the application without the need for external reset hardware. During a low voltage detector reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Note: Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is recommended to pull VDD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 62 and note 4. The LVD is an optional function which can be selected by option byte. See Section 14.1 on page 123. It allows the device to be used without any external RESET circuitry. If the LVD is disabled, an external circuitry must be used to ensure a proper Power-on reset. It is recommended to make sure that the VDD supply voltage rises monotonously when the device is exiting from Reset, to ensure the application functions properly. Make sure the right combination of LVD and AVD thresholds is used as LVD and AVD levels are not correlated. Refer to Table 47 on page 95 and Table 48 on page 96 for more details. Caution: If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will clear the watchdog flag. Obsolete Product(s) - Obsolete Product(s)

7.4.2 Auxiliary voltage detector (AVD)

voltage in order to avoid parasitic detection (hysteresis). real time status bit (AVDF) in the SICSR register. This bit is read only. The AVD threshold is selected by the AVD[1:0] bits in the AVDTHCR register. VIT+(AVD) or VIT -(AVD) threshold (AVDF bit is set). software to shut down safely before the LVD resets the microcontroller. See Figure 17. are not correlated. Refer to Table 47 on page 95 and Table 48 on page 96 for more details. Figure 17. Using the AVD to monitor V DD

7.4.3 Low power modes

(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).

7.4.4 Register description

Table 11. Description of low power modes Wait No effect on SI. AVD interrupts cause the device to exit from Wait mode. The SICSR register is frozen. Table 12. Description of interrupt events Bit 7 Reserved, must be kept cleared. Bits 4:3 Reserved, must be kept cleared.

LVDRF flag remains set to keep trace of the original failure. In this case, a watchdog reset can be detected by software while an external reset can not. BYTE, the LVDRF bit value is undefined. typ.), the LVDRF flag cannot be set even if the device is reset by the LVD. fCLKIN is greater than 10 MHz. when software enters the AVD interrupt routine. Table 13. System integrity register map and reset values

01100 LVDRF

8 Power saving modes

8.1 Introduction

• Slow
• Wait (and Slow-wait)
• Active-halt
• Auto-wakeup from Halt (AWUFH)
• Halt After a reset the normal operating mode is selected by default (Run mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency (fOSC). From Run mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.

Figure 18. Power saving mode transitions

8.2 Slow mode

• To reduce power consumption by decreasing the internal clock in the device,
• To adapt the internal clock frequency (fCPU) to the available supply voltage. Slow mode is controlled by the SMS bit in the MCCSR register which enables or disables Slow mode. In this mode, the oscillator frequency is divided by 32. The CPU and peripherals are clocked at this lower frequency. Note: Slow-wait mode is activated when entering Wait mode while the device is already in Slow mode.

Figure 19. Slow mode clock transition

8.3 Wait mode

Wait mode places the MCU in a low power consumption mode by stopping the CPU. This power saving mode is selected by calling the ‘WFI’ instruction. the starting address of the interrupt or Reset service routine. The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wakeup. Refer to Figure 20 for a description of the Wait mode flowchart.

Figure 20. Wait mode flowchart

1. 1. Before servicing an interrupt, t he CC register is pushed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

8.4 Active-halt and Halt modes

64 CPU CLOCK CYCLE

Table 14. Enabling/disabling Active-halt and Halt modes

8.4.1 Active-halt mode

available. It is entered by executing the ‘HALT’ instruction when Active-halt mode is enabled.

• When exiting Active-halt mode by means of a reset, a 64 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see Figure 22).
• When exiting Active-halt mode by means of an interrupt, the CPU immediately resumes operation by servicing the interrupt vector which woke it up (see Figure 22). When entering Active-halt mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately. In Active-halt mode, only the main oscillator and the selected timer counter (LT/AT) are running to keep a wakeup time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator). Caution: As soon as Active-halt is enabled, executing a HALT instruction while the watchdog is active does not generate a reset if the WDGHALT bit is reset. This means that the device cannot spend more than a defined delay in this power saving mode.

Figure 21. Active-halt timing overview

Figure 22. Active-halt mode flowchart

1. This delay occurs only if the MCU exit s Active-halt mode by means of a reset.
2. Peripherals clocked with an external clock source can still be active.
3. Only the Lite Timer RTC and AT Timer interru pts can exit the MCU from Active-halt mode.
4. Before servicing an interrupt, the CC register is pus hed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

8.4.2 Halt mode

executing the ‘HALT’ instruction when Active-halt mode is disabled. fetching the reset vector which woke it up (see Figure 24). When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately.

Figure 23. Halt timing overview

1. A reset pulse of at least 42µs must be applied when exiting from Halt mode.

Figure 24. Halt mode flowchart

1. WDGHALT is an option bit. See opti on byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 9: Interrupt mapping for more details.

1. Before servicing an interrupt, the CC register is pus hed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

1. The CPU clock must be switched to 1 MHz ( RC/8) or AWU RC before entering Halt mode.

• Make sure that an external event is available to wakeup the microcontroller from Halt mode.
• When using an external interrupt to wakeup the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition.
• For the same reason, reinitialize the level sensitiveness of each external interrupt as a precautionary measure.
• The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memory. For example, avoid defining a constant in ROM with the value 0x8E.
• As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wakeup event (reset or external interrupt).

8.5 Auto-wakeup from Halt mode

Figure 25. AWUFH mode block diagram

• The AWUF flag is set by hardware,
• An interrupt wakes-up the MCU from Halt mode,
• The main oscillator is immediately turned on and the 64 CPU cycle delay is used to stabilize it. AWU RC AWUFH fAWU_RC AWUFH (ei0 source) oscillator prescaler/1 .. 255 interrupt/64 divider to 8-bit Timer input capture Obsolete Product(s) - Obsolete Product(s)

AWU_RC and then calculating the right prescaler value. fAWU_RC to be measured using the main oscillator clock as a reference timebase.

• The MCU can exit AWUFH mode by means of any interrupt with exit from Halt capability or a reset (see Section 8.4: Active-halt and Halt modes).
• When entering AWUFH mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
• In AWUFH mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals. None of the peripherals are clocked except those which get their clock supply from another clock generator (such as an external or auxiliary oscillator like the AWU oscillator).
• The compatibility of watchdog operation with AWUFH mode is configured by the WDGHALT option bit in the option byte. Depending on this setting, the HALT instruction when executed while the watchdog system is enabled, can generate a watchdog reset.

Figure 26. AWUF Halt timing diagram

Figure 27. AWUFH mode flowchart

1. WDGHALT is an option bit. See opti on byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only an AWUFH interrupt and some specific interrupts can exit the MCU from Halt mode (such as external

interrupt). Refer to Table 9: Interrupt mapping for more details.

1. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

64 CPU CLOCK

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Power saving modes

8.5.1 Register description

AWUFH Control/ Status register (AWUCSR) Reset value: 0000 0000 (00h) AWUFH Prescaler register (AWUPR) Reset value: 1111 1111 (FFh) 7 0

00000 AWU

Bits 7:3 Reserved Bit 2 AWUF Auto-wakeup Flag This bit is set by hardware when the AWU module generates an interrupt and cleared by software on reading AWUCSR. Writing to this bit does not change its value. 0: No AWU interrupt occurred 1: AWU interrupt occurred Bit 1 AWUM Auto-wakeup Measurement This bit enables the AWU RC oscillator and connects its output to the input capture of the 8-bit Lite timer. This allows the timer to be used to measure the AWU RC oscillator dispersion and then compensate this dispersion by providing the right value in the AWUPRE register. 0: Measurement disabled 1: Measurement enabled Bit 0 AWUEN Auto-wakeup From Halt Enabled This bit enables the Auto-wakeup From Halt feature: once Halt mode is entered, the AWUFH wakes up the microcontroller after a time delay dependent on the AWU prescaler value. It is set and cleared by software. 0: AWUFH (Auto-wakeup From Halt) mode disabled 1: AWUFH (Auto-wakeup From Halt) mode enabled Note: Whatever the clock source, this bit should be set to enable the AWUFH mode once the HALT instruction has been executed. 7 0 AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0 Read/Write Bits 7:0 AWUPR[7:0] Auto-wakeup Prescaler These 8 bits define the AWUPR Dividing factor (see Table 15: Configuring the dividing factor) Obsolete Product(s) - Obsolete Product(s)

mode before waking up automatically. after a HALT instruction, or the AWUPR remains unchanged. Table 15. Configuring the dividing factor Table 16. AWU register map and reset values

00000 A W U F A W U M AWUE

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 I/O ports

9 I/O ports

9.1 Introduction

The I/O port offers different functional modes:

• Transfer of data through digital inputs and outputs and for specific pins:
• External interrupt generation
• Alternate signal input/output for the on-chip peripherals. An I/O port contains up to 6 pins. Each pin (except PA3/RESET) can be programmed independently as digital input (with or without interrupt generation) or digital output.

9.2 Functional description

Each port has 2 main registers:

• Data register (DR)
• Data Direction register (DDR) and one optional register:
• Option register (OR) Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 28.

9.2.1 Input modes

The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Note: 1 Writing the DR register modifies the latch value but does not affect the pin status. 2 PA3 cannot be configured as input. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Obsolete Product(s) - Obsolete Product(s)

external interrupt is disabled by the OR register. configuring the appropriate sensitivity again. avoid an external interrupt occurring on the unwanted edge.

1. To enable an external interrupt:
2. To disable an external interrupt:

9.2.2 Output modes

reading the DR register returns the previously stored value. Table 17. DR register value and output pin status (1)

1. When switching from input to output mode, the DR regist er has to be written first to drive the correct level

on the pin as soon as the port is configured as an output.

9.2.3 Alternate functions

• When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).
• When the signal is going to an on-chip peripheral, the I/O pin must be configured in floating input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: 1 Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input.

2 When an on-chip peripheral use a pin as input and output, this pin has to be configured in

Figure 28. I/O port general block diagram

Table 18. I/O port mode options (1)

1. NI stands for not implemented; Off for implement ed not activated; On for implemented and activated.

Table 19. I/O port configurations

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

1. When the I/O port is in output configuration and t he associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

interrupt, in order to avoid generating spurious interrupts. the selected pin to the common analog rail which is connected to the ADC input. close to a selected analog pin. stated in the absolute maximum ratings.

9.3 Unused I/O pins

Unused I/O pins must be connected to fixed voltage levels. Refer to Section 12.8.

9.4 Low power modes

9.5 Interrupts

Table 20. Effect of low power modes on I/O ports Table 21. Description of interrupt events

9.6 I/O port implementation

registers and specific feature of the I/O port such as ADC Input or true open drain. prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 29. unwanted side-effects such as spurious interrupt generation. Figure 29. Interrupt I/O port state transitions The I/O port register configurations are summarized in Table 22. Table 22. Port configuration Table 23. I/O port register map and reset values

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 On-chip peripherals

10 On-chip peripherals

10.1 Lite timer (LT)

10.1.1 Introduction

The Lite Timer can be used for general-purpose timing functions. It is based on a free- running 13-bit upcounter with two software-selectable timebase periods, an 8-bit input capture register and watchdog function.

10.1.2 Main features

• Real-time clock – 13-bit upcounter – 1 ms or 2 ms timebase period (@ 8 MHz f OSC) – Maskable timebase interrupt
• Input capture – 8-bit input capture register (LTICR) – Maskable interrupt with wakeup from Halt mode capability
• Watchdog – Enabled by hardware or software (configurable by option byte) – Optional reset on HALT instruction (configurable by option byte) – Automatically resets the device unless disable bit is refreshed – Software reset (forced watchdog reset) – Watchdog reset status flag Obsolete Product(s) - Obsolete Product(s)

Figure 30. Lite timer block diagram

10.1.3 Functional description

generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register. fosc = 8 MHz), after which it then generates a reset. regular intervals to prevent a watchdog reset occurring. Refer to Figure 31. reset will not occur for at least 2 ms. Note: Software can use the timebase feature to set the WDGD bit at 1 or 2 ms intervals.

8 MSB

The WDGRF bit also acts as a flag, indicating that the watchdog was the source of the reset. It is automatically cleared after it has been read. enabled (by hardware or software), the microcontroller will be immediately reset. WDGE bit in the LTCSR is not used. used when the watchdog is enabled. microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG restarts counting after 256 or 512 CPU clocks. If a reset is generated, the watchdog is disabled (reset state). counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. Figure 31. Watchdog timing diagram generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register. The LTICR is a read only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set.

10.1.4 Low power modes

10.1.5 Interrupts

mask in the CC register is reset (RIM instruction). Figure 32. Input capture timing diagram Table 24. Description of low power modes Table 25. Interrupt events (1)

1. The TBF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter).

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 On-chip peripherals

10.1.6 Register description

Lite timer control/status register (LTCSR) Reset value: 0000 0x00 (0xh) 7 0 ICIE ICF TB TBIE TBF WDGR WDGE WDGD Read / Write Bit 7 ICIE Interrupt Enable. This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Bit 6 ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Note: After an MCU reset, software must in itialise the ICF bit by reading the LTICR register Bit 5 TB Timebase period selection. This bit is set and cleared by software. 0: Timebase period = t OSC * 8000 (1 ms @ 8 MHz) 1: Timebase period = tOSC * 16000 (2 ms @ 8 MHz) Bit 4 TBIE Timebase Interrupt enable. This bit is set and cleared by software. 0: Timebase (TB) interrupt disabled 1: Timebase (TB) interrupt enabled Bit 3 TBF Timebase Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No counter overflow 1: A counter overflow has occurred Obsolete Product(s) - Obsolete Product(s)

by software after a read access to the LTCSR register. 0: No watchdog reset occurred. 1: Force a watchdog reset (write), or, a watchdog reset occurred (read). This bit is set and cleared by software. rising or falling edge occurs on the LTIC pin. Table 26. Lite timer register map and reset values

10.2.1 Introduction

a free-running 12-bit upcounter with a PWM output channel.

10.2.2 Main features

• 12-bit upcounter with 12-bit auto-reload register (ATR)
• Maskable overflow interrupt
• PWM signal generator
• Frequency range 2 kHz - 4 MHz (@ 8 MHz fCPU) – Programmable duty-cycle – Polarity control – Maskable compare interrupt
• Output compare function

Figure 33. Block diagram

10.2.3 Functional description

configured as output push-pull alternate function.

register value = 4094), and the minimum value is 2 kHz (ATR register value = 0). At reset, the counter starts counting from 0. DCR0H register must be written first. See caution below. must be greater than the contents of the ATR register. The polarity bit can be used to invert the output signal. event and to have the right signal applied on the PWM output. Figure 34. PWM function

Figure 35. PWM signal example generated if the CMPIE bit is set. Note: The output compare function is only available for DCRx values other than 0 (reset value). DCRx. There is no PWM signal. locked until DCR0L is written.

10.2.4 Low power modes

Table 27. Description of low power modes

10.2.5 Interrupts

10.2.6 Register description

Table 28. Interrupt events

1. The interrupt events are connected to separat e interrupt vectors (see Interrupts chapter).

register is reset (RIM instruction). Bits 7:5 Reserved, mu st be kept cleared. Bits 4:3 CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter from FFFh to ATR value. clock selection) after it has been cleared by software. Bit 1 OVFIE Overflow interrupt enable. This bit is read/write by software and cleared by hardware after a reset. Bit 0 CMPIE Compare interrupt enable. mask the interrupt generation when CMPF bit is set.

CNTRL values close to FFh are read. When a counter overflow occurs, the counter restarts from the value specified in the ATR register. Table 29. Counter clock selection Bits 15:12 Reserved, must be kept cleared. Bits 11:0 CNTR[11:0] Counter value.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7LITEUS2, ST7LITEUS5 Auto reload register (ATRL) This is a 12-bit register which is written by software. The ATR register value is automatically loaded into the upcounter when an overflow occurs. The register value is used to set the PWM frequency. Reset value: 0000 0000 (00h) PWM0 duty cycle register high (DCR0H) Reset value: 0000 0000 (00h) PWM0 duty cycle register low (DCR0L) This 12-bit value is written by software. The high register must be written first. In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWM0 output signal (see Figure 34). In Output Compare mode, (OE0=0 in the PWMCR register) they define the value to be compared with the 12-bit upcounter value. Reset value: 0000 0000 (00h) 7 0 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 Read/Write Bits 15:12 Reserved, must be kept cleared. Bits 11:0 ATR[11:0] Auto-reload Register. 15 8 0 0 0 0 DCR11 DCR10 DCR9 DCR8 Read/Write 7 0 DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 Read/Write Bits 15:12 Reserved, must be kept cleared. Bits 11:0 DCR[11:0] PWMx duty cycle value Obsolete Product(s) - Obsolete Product(s)

000000 O P 0 C M P F 0

Bit 7:2 Reserved, must be kept cleared. Bit 1 OP0 PWM0 output polarity. selects the polarity of the PWM0 signal. 0: The PWM0 signal is not inverted. 1: The PWM0 signal is inverted. Bit 0 CMPF0 PWM0 Compare Flag. register. It indicates that the upcounter value matches the DCR0 register value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value.

0000000 O E 0

Bits 7:1 Reserved, mu st be kept cleared. Bit 0 OE0 PWM0 Output enable. This bit is set and cleared by software. Table 30. Register map and reset values

10 ATRH

11 ATRL

12 PWMCR

13 PWM0CSR

17 DCR0H

18 DCR0L

Table 30. Register map and reset values (continued)

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 On-chip peripherals 10.3 10-bit A/D converter (ADC)

10.3.1 Introduction

The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 5 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 5 different sources. The result of the conversion is stored in a 10-bit Data register. The A/D converter is controlled through a Control/Status register.

10.3.2 Main features

• 10-bit conversion
• Up to 5 channels with multiplexed input
• Linear successive approximation
• Data register (DR) which contains the results
• Conversion complete status flag
• On/off bit (to reduce consumption) The block diagram is shown in Figure 36.

10.3.3 Functional description

VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. Obsolete Product(s) - Obsolete Product(s)

Figure 36. ADC block diagram does not and never increases if the analog input does not. conversion result in the ADCDRH and ADCDRL registers is 00 00h. completed in the alloted time.

• Sample capacitor loading [duration: tSAMPLE] During this phase, the VAIN input voltage to be measured is loaded into the CADC sample capacitor.
• A/D conversion [duration: tHOLD] During this phase, the A/D conversion is computed (8 successive approximations CH2 CH1EOC SPEED ADON 0 CH0 ADCCSR AIN0 AIN1 ANALOG TO DIGITAL CONVERTER AINx ANALOG MUX D4 D3D5D9 D8 D7 D6 D2ADCDRH D1 D0ADCDRL 00 0 0 SLOW 0 RADC CADC HOLD CONTROL fADCfCPU DIV 2 DIV 4 SLOW bit Obsolete Product(s) - Obsolete Product(s)

the optimum analog to digital conversion accuracy.

• The total conversion time: t CONV = tSAMPLE + tHOLD While the ADC is on, these two phases are continuously repeated. At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behavior is that it minimizes the current consumption on the analog pin in case of single input channel measurement. A/D conversion The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the “I/O ports” chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the ADCCSR register, select the CS[2:0] bits to assign the analog channel to convert. ADC conversion mode In the ADCCSR register, set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete:
• The EOC bit is set by hardware.
• The result is in the ADCDR registers. A read to the ADCDRH resets the EOC bit. To read the 10 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRL 3. Read ADCDRH. This cl ears EOC automatically. To read only 8 bits, perform the following steps: 1. Poll EOC bit 1. Read ADCDRH. This cl ears EOC automatically.

10.3.4 Low power modes

power consumption when no conversion is needed and between single shot conversions. Table 31. Effect of low power modes

10.3.5 Interrupts

10.3.6 Register description

EOC bit and starts a new conversion. This bit is set by hardware. It is cleared by software reading the ADCDRH register. configure the ADC clock speed. Refer to the table in the SLOW bit description. This bit is set and cleared by software. Bits 4:3 Reserved. Must be kept cleared. These bits are set and cleared by software. They select the analog input to convert. Table 32. Channel selection

0000 S L O W 0 D 1 D 0

Bits 7:4 Reserved. Forced by hardware to 0. Configuring the ADC clock speed). Bit 2 Reserved. Forced by hardware to 0. Table 33. Configuring the ADC clock speed Table 34. ADC register map and reset values

11 Instruction set

11.1 ST7 addressing modes

• Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles.
• Short addressing mode is less powerful because it can generally only access page zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use shor t addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF , INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes.

Table 35. Description of addressing modes Table 36. ST7 addressing mode overview (1)

11.1.1 Inherent mode

information for the CPU to process the operation.

1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.

Table 36. ST7 addressing mode overview (continued) (1) Table 37. Instructions supporting inherent addressing mode

11.1.2 Immediate

11.1.3 Direct

In Direct instructions, the operands are referenced by their memory address.

11.1.4 Indexed mode ( no offset, short, long)

unsigned addition of an index register (X or Y) with an offset. There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space. Table 38. Instructions supporting inherent immediate addressing mode

11.1.5 Indirect modes (short, long)

space, and requires 1 byte after the opcode. space, and requires 1 byte after the opcode.

11.1.6 Indirect indexed modes (short, long)

space, and requires 1 byte after the opcode. space, and requires 1 byte after the opcode. Table 39. Instructions supporting direct, i ndexed, indirect and indirect indexed

11.1.7 Relative modes (direct, indirect)

The offset follows the opcode. The offset is defined in memory, of which the address follows the opcode.

11.2 Instruction groups

Table 40. Instructions supporting relative modes Table 41. ST7 instruction set

The instructions are described with 1 to 4 bytes. to an instruction using the corresponding indirect addressing mode. indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

11.2.1 Illegal opcode reset

watchdog, allows the detection and recovery from an unexpected fault or interference. Table 41. ST7 instruction set (continued) Table 42. Illegal opcode detection

Table 42. Illegal opcode detection (continued)

12.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

12.1.1 Minimum and maximum values

selected temperature range). mean value plus or minus three times the standard deviation (mean±3Σ).

12.1.2 Typical values

12.1.3 Typical curves

12.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 37. Figure 37. Pin loading conditions

12.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 38. Figure 38. Pin input voltage

12.2 Absolute maximum ratings

1. Directly connecting the I/O pins to V

change of the I/O configuration occurs (for example, due to a corrupted program counter). VSS according to their reset configuration. Table 43. Voltage characteristics

1. I INJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.

12.3 Operating conditions

12.3.1 General operating conditions

TA = -40 to +125 °C unless otherwise specified. Table 44. Current characteristics

1. All power (V DD) and ground (VSS) lines must always be connected to the external supply.
2. I INJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.

1. Negative injection disturbs the analog performance of t he device. In particular, it induces leakage currents

the current as far as possible from the analog input pins.

1. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the

characterisation with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device. Table 45. Thermal characteristics Table 46. General operating conditions

Figure 39. f CPU maximum operating frequency versus VDD supply voltage

12.3.2 Operating conditions with low voltage detector (LVD)

Table 47. Operating characteristics with LVD

1. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on and LVD reset
2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is
3. Not tested in production.

12.3.3 Auxiliary voltage detector (AVD) thresholds

TA = −40 to 125°C, unless otherwise specified.

12.3.4 Internal RC oscillator

Table 48. Operating characteristics with AVD (1)

1. Refer to Section : Monitoring the VDD main supply.
2. Not tested in production, guar anteed by characterization.

Table 49. Voltage drop between AVD flag set and LVD reset generation

1. Not tested in production, guar anteed by characterization.

Table 50. Internal RC oscillator characteristics (5.0 V calibration)

1. See Section 6.2: Internal RC oscillator adjustment
2. Tested in production at 5.0 V only

Table 51. Internal RC oscillator characteristics (3.3 V calibration)

1. See Section 6.2: Internal RC oscillator adjustment
2. Tested in production at 3.3 V only Obsolete Product(s) - Obsolete Product(s)

12.4 Supply current characteristics

A = -40 to +125 °C unless otherwise specified.

12.4.1 Supply current

Table 52. Supply current characteristics

1. CPU running with memory access , all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in

reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. Data based on characterization, not tested in production.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)

driven by external square wave, LVD disabled.

1. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)

driven by external square wave, LVD disabled.

1. Slow-Wait mode selected with fCPU based on f

VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU max.
2. This consumption refers to the Halt period only an d not the associated run period which is software dependent.
3. All I/O pins in output mode with a static value at VSS ( no load), LVD disabled. Data based on characterization results,

tested in production at VDD max and fCPU max.

12.4.2 Internal RC oscillator supply current characteristics

Table 53. Internal RC oscillator supply current

1. Data based on characterization results, not tested in production.
2. CPU running with memory access, all I/O pi ns in input mode with a static value at VDD or VSS (no load), all peripherals in

reset state; CPU clock provided by the internal RC, LVD disabled.

1. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; CPU clock provided by

the internal RC, LVD disabled.

1. Slow mode selected with f CPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS (no

load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.

1. Slow-Wait mode selected with f CPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or VSS

(no load), all peripherals in reset state; CPU clock provided by the internal RC, LVD disabled.

Figure 42. Typical I DD in run mode vs. internal clock frequency and VDD Figure 43. Typical I DD in WFI mode vs. internal clock frequency and VDD Figure 44. Typical I DD in Slow, Slow-wait and Active-halt mode vs VDD & int

8 MHz

4 MHz

2 MHz

12.4.3 On-chip peripherals

12.5 Clock and timing characteristics

Subject to general operating conditions for VDD, fOSC, and TA. Table 54. On-chip peripheral characteristics

1. Not tested in production, guar anteed by characterization.
2. Data based on a differential I DD measurement between reset configuration (timer stopped) and the timer running in PWM
3. Data based on a differential I DD measurement between reset configuration and continuous A/D conversions with amplifier

Table 55. General timings

1. Data based on characterization. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles

needed to finish the current instruction execution. Table 56. Auto-wakeup RC oscillator

1. Data guaranteed by design.

12.6 Memory characteristics

Table 57. RAM and Hardware registers Table 58. Flash Program memory

1. Minimum V DD supply voltage without losing data stored in RAM (in Halt mode or under reset) or in

hardware registers (only in Halt mode). Guaranteed by construction, not tested in production.

1. Up to 32 bytes can be programmed at a time.
2. Data based on reliability test results and monitored in production.
3. The data retention time increases when the T A decreases.
4. Design target value pending full product characterization.
5. Guaranteed by Design. Not tested in production.

12.7 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

12.7.1 Functional EMS (elect romagnetic susceptibility)

• ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (control registers...) Pre-qualification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Table 59. EMC characteristics

12.7.2 Electromagnetic Interference (EMI)

norm SAE J 1752/3 which specifies the board and the loading of each pin.

12.7.3 Absolute maximum rati ngs (electrical sensitivity)

product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.

• LU: 3 complementary static tests are required on 10 parts to assess the latchup performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latchup standard. For more details, refer to the application note AN1181.
• DLU: Electrostatic discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latchup performance in

Table 60. EMI characteristics (1)

1. Data based on characterization results, not tested in production.

0.1 MHz to

30 MHz 21

130 MHz 23

130 MHz to

Table 61. Absolute maximum ratings

1. Data based on characterization results, not tested in production.

as near as possible to the pins of the micro and the component is put in reset mode. refer to the application note AN1181. Table 62. Electrical sensitivities

1. Class description: A Class is an STMi croelectronics internal specification. All its limits are higher than the

Class strictly covers all the JEDEC criteria (international standard).

12.8 I/O port pin characteristics

12.8.1 General characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified. Figure 48. Two typical applications with unused I/O pin

1. Caution: During normal operation the ICCCLK pin must be pulled- up, internally or externally (external pull-

up of 10k mandatory in noisy environment). This is to avoid entering I2C mode unexpectedly during a reset.

1. I/O can be left unconnected if it is configured as output (0 or 1) by the software. This has the advantage of

greater EMC robustness and lower cost. Table 63. General characteristics

1. Data based on characterization results, not tested in production.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of

production. This value depends on VDD and temperature values.

1. The R PU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current

characteristics described in Figure 49).

1. R PU not applicable on PA3 because it is multiplexed on RESET pin
2. To generate an external interrupt, a minimum pulse wi dth has to be applied on an I/O port pin configured

as an external interrupt source.

Figure 49. Typical I PU vs. VDD with VIN=VSSl

12.8.2 Output driving current characteristics

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Table 64. Output driving current characteristics

1. The IIO current sunk must always respect the absolute maximum rating specified in Table 52 and the sum of IIO (I/O ports and control pins)
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 52 and the sum of IIO (I/O ports and control pins)

must not exceed IVDD. True open drain I/O pins do not have VOH.

1. Not tested in production, based on characterization results.

Figure 59. Typical V OL vs. VDD (HS pins) Figure 60. Typical V DD-VOH vs. VDD (HS pins)

12.9 Control pin characteristics

The reset network protects the device against parasitic resets. not be taken into account internally. maximum value specified for IINJ(RESET) in Table 44.

Figure 61. RESET pin protection when LVD is enabled

1. When the LVD is enabled, it is recommended not to c onnect a pull-up resistor or capacitor. A 10nF pull-

down capacitor is required to filter noise on the reset line.

1. In case a capacitive power supply is used, it is recommended to connect a 1M Ω pull-down resistor to the

add 5µA to the power consumption of the MCU). Table 65. Asynchronous RESET pin characteristics (1)

1. T A = -40°C to 125°C, unless otherwise specified.
2. Data based on characterization results, not tested in production.
3. The I IO current sunk must always respect the absolute maximum rating specified in Table 44 and the sum

of IIO (I/O ports and control pins) must not exceed IVSS.

1. The R ON pull-up equivalent resistor is based on a resistive transistor. Specified for voltages on RESET pin
2. To guarantee the reset of the device, a mi nimum pulse has to be applied to the RESET pin. All short pulses

applied on RESET pin with a duration below th(RSTL)in can be ignored.

Figure 62. RESET pin protection when LVD is disabled

12.10 ADC characteristics

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified. Table 66. 10-bit ADC characteristics

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5 V. They are given only as

design guidelines and are not tested.

1. The maximum ADC clock frequency allowed within V DD = 2.4 to 2.7 V operating range is 1 MHz.
2. When V DDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than

10kΩ). Data based on characterization results, not tested in production.

1. The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the

enable is then always valid.

Figure 63. Typical application with ADC Table 67. ADC accuracy with V DD = 3.3 to 5.5 V

1. Data based on characterization results over the whole temperature range.

Table 68. ADC accuracy with V DD = 2.7 to 3.3 V

1. Data based on characterization results over the whole temperature range.

Table 69. ADC accuracy with V DD = 2.4V to 2.7V

1. Data based on characterization results at a temperature ≥ 25°C.

Figure 64. ADC accura cy characteristics

1. Example of an actual transfer curve
2. End point correlation line

T=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.

1. EO=Offset Error: deviation between the first actual transition and the first ideal one.
2. EG=Gain Error: deviation between the last ideal transition and the last actual one.
3. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one.
4. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

13.1 Package mechanical data

Figure 65. 8-lead very thin fine pitc h dual flat no-lead package outline Table 70. 8-lead very thin fine pitch dual flat no-lead package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 66. 8-pin plastic small outline package, 150-mil width package outline

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 67. 8-pin plastic dual in-line package, 300-mil width package outline Table 72. 8-pin plastic dual in-line package, 300-mil width package mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 68. 16-pin plastic dual in-line package, 300-mil width, package outline

1. Values in inches are converted from mm and rounded to 4 decimal digits.

13.2 Thermal characteristics

Table 74. Thermal characteristics

1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.

ports used in the application.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Device configuration and ordering information

14 Device configuration and ordering information

Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (FASTROM). Refer to Table 79 for the full list of supported part numbers:

• ST7FLITEUSA2xx and ST7FLITEUSA5xx XFlash devices are shipped to customers with a default program memory content (FFh).
• Factory Advanced Service Technique ROM (FASTROM) versions are also available: they are factory-programmed XFlash devices. The FASTROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer using the Option Bytes while the FASTROM devices are factory-configured.

14.1 Option bytes

The two option bytes allow the hardware configuration of the microcontroller to be selected. The option bytes can be accessed only in programming mode (for example using a standard ST7 programming tool).

14.1.1 OPTION BYTE 1

Bit 7:6 CKSEL[1:0] Startup clock selection. This bit is used to select the startup frequency. By default, the internal RC is selected (see Table 75: Startup clock selection). Bit 5 Reserved, must always be 1. Bit 4 Reserved, must always be 0. Bits 3:2 LVD[1:0] Low Voltage Detection selection These option bits enable the LVD block with a selected threshold as shown in Table 76: LVD threshold configuration. Bit 1 WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) Bit 0 WDG HALT Watchdog Reset on Halt This option bit determines if a reset is generated when entering Halt mode while the watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode Obsolete Product(s) - Obsolete Product(s)

14.1.2 OPTION BYTE 0

Table 75. Startup clock selection Table 76. LVD threshold configuration Bits 7:4 Reserved, must always be 1. Bit 3 Reserved, must always be 0. Table 77: Definition of sector 0 size). ST7 Flash Programming Reference Manual for more details. This option indicates if the FLASH program memory is write protected. itself) can never be erased or programmed again. Table 77. Definition of sector 0 size

14.2 Ordering information

completed option list appended.

0 Res Res LVD1 LVD0 WDG

Table 79. Supported order codes (1)

1. Contact ST sales office for product availability.
2. For development or tool prototyping purposes only, not orderable in production quantities.

Table 79. Supported order codes (1) (continued)

Figure 69. Option list *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. Authorized characters are letters, digits, '.', '-', '/' and spaces only. authorized option byte combinations.

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) Device configuration and ordering information ST7LITEUS2, ST7LITEUS5

14.3 Development tools

Development tools for the ST7 microcontrollers include a complete range of hardware systems and software tools from STMicroelectronics and third-party tool suppliers. The range of tools includes solutions to help you evaluate microcontroller peripherals, develop and debug your application, and program your microcontrollers.

14.3.1 Starter kits

ST offers complete, affordable starter kits. Starter kits are complete, affordable hardware/software tool packages that include features and samples to help you quickly start developing your application.

14.3.2 Development and debugging tools

Assembler-Linker toolchain, which are all seamlessly integrated in the ST7 integrated development environments in order to facilitate the debugging and fine-tuning of your application. The Cosmic C Compiler is available in a free version that outputs up to 16 Kbytes of code. The range of hardware tools includes full-featured ST7-EMU3 series emulators, cost effective ST7-DVP3 series emulators and the low-cost RLink in-circuit debugger/programmer. These tools are supported by the ST7 Toolset from STMicroelectronics, which includes the STVD7 integrated development environment (IDE) with high-level language debugger, editor, project manager and integrated programming interface.

14.3.3 Programming tools

During the development cycle, the ST7-DVP3 and ST7-EMU3 series emulators and the RLink provide in-circuit programming capability for programming the Flash microcontroller on your application board. ST also provides a low-cost dedicated in-circuit programmer, the ST7-STICK, as well as ST7 Socket Boards which provide all the sockets required for programming any of the devices in a specific ST7 sub-family on a platform that can be used with any tool with in- circuit programming capability for ST7. For production programming of ST7 devices, ST’s third-party tool partners also provide a complete range of gang and automated programming solutions, which are ready to integrate into your production environment.

14.3.4 Order codes for developm ent and programming tools

Table 80 below lists the ordering codes for the ST7LITEUSx development and programming tools. For additional ordering codes for spare parts and accessories, refer to the online product selector at www.st.com/mcu. Obsolete Product(s) - Obsolete Product(s)

14.4 ST7 application notes

Table 80. Development tool order codes for the ST7LITEUSx family

1. Available from ST or from Raisonance, www.raisonance.com.
2. Includes connection kit for Plastic DIP16/ SO16 only. See “How to order an EMU or DVP” in ST product and tool selection

guide for connection kit ordering information.

1. Parallel port connection to PC.
2. Add suffix /EU, /UK or /US for the power supply for your region.

Table 81. ST7 application notes

Table 81. ST7 application notes (continued)

Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Known limitations

15 Known limitations

External interrupt 2 (ei2) Whatever the external interrupt sensitivity configured through EICR1 register, ei2 cannot exit the MCU from Halt, Active-halt and AWUFH modes when a falling edge occurs. Workaround None Obsolete Product(s) - Obsolete Product(s)

Table 82. Document revision history conditions with low voltage detector (LVD). Table 49: Voltage drop between AVD flag set and LVD reset generation. Table 79. Modified conditioning option in option list. Modified Section 14.3: Section : . Added erratasheet at the end of the document.

RON data corrected in Table 65. Replaced ST7ULTRALITE by ST7LITEUS2 and ST7LITEUS5. limitations, and added External interrupt 2 (ei2). Section 12.8.2: Output driving current characteristics. Updated internal RC prescaler to add 500 KHz. plastic dual in-line package, 300-mil width, package outline. Changed order codes to die A version in Table 79: Supported order codes. Removed soldering information section. Table 82. Document revision history (continued)