ST7FL19F1MCE

ST7L15 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Features

■ Memories – 4 Kbytes single voltage extended Flash (XFlash) or ROM with readout protection, In- Circuit programming and In-Application Pro- gramming (ICP and IAP), 10K write/erase cy- cles guaranteed, data retention 20 years at 55°C – 256 bytes RAM – 128 bytes data E2PROM with readout protec- tion, 300K write/erase cycles guaranteed, data retention 20 years at 55°C ■ Clock, Reset and Supply Management – Enhanced reset system – Enhanced low voltage supervisor (LVD) for main supply – Clock sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock – Optional x4 or x8 PLL for 4 or 8 MHz internal clock (only x8 PLL available for ROM devices) – 5 power saving modes: Halt, Active Halt, Auto Wake-Up from Halt, Wait and Slow ■ I/O Ports – Up to 17 multifunctional bidirectional I/O lines –7 high sink outputs ■ 5 Timers – Configurable watchdog timer – Two 8-bit Lite timers with prescaler, 1 realtime base and 1 input capture – Two 12-bit autoreload timers with 4 PWM out- puts, 1 input capture, 1 pulse and 4 output compare functions ■ Communication Interface – SPI synchronous serial interface ■ Interrupt Management – 12 interrupt vectors plus TRAP and RESET – 15 external interrupt lines (on 4 vectors) ■ A/D Converter – 7 input channels – 10-bit precision ■ Instruction Set – 8-bit data manipulation – 63 basic instructions with illegal opcode de- tection – 17 main addressing modes – 8 x 8 unsigned multiply instructions ■ Development Tools – Full hardware/software development package – DM (Debug Module) Device Summary SO20 300mil Features ST7L15 ST7L19 Program Memory - bytes 4K RAM (stack) - bytes 256 (128) Data EEPROM - bytes - 128 Peripherals Lite Timer with Watchdog, Autoreload Timer, SPI, 10-bit ADC Operating Supply 3V to 5.5V CPU Frequency Up to 8 MHz (w/ext OSC up to 16 MHz and int 1 MHz RC 1%, PLLx8/4 MHz) Operating Temperature Up to - 40 to +85°C / -40 to +125°C

1 INTRODUCTION

1.1 DESCRIPTION

tion Programming (IAP) capability.

1.2 PARAMETRIC DATA

1.3 DEBUG MODULE

ICC Protocol Reference Manual. Figure 1. General Block Diagram *Note: Not available on ROM devices.

1 MHz

16 MHz

2 PIN DESCRIPTION

Figure 2. 20-Pin SO Package Pinout

1. This pin cannot be configured as external interrupt in ROM devices.
2. OSC1 and OSC2 are not multiplexed in ROM devices and Port C is not present.

The RESET configuration of each pin (shown in bold) is valid as long as the device is in reset state. Table 1. Device Pin Description

3 RESET I/O C T X X Top priority non maskable interrupt (active low)

ST7L15, ST7L19 Notes: 1. This pin cannot be configured as external interrupt in ROM devices. 2. OSC1 and OSC2 are not multiplexed in ROM devices and Port C is not present. 3. PCOR not implemented but p-transistor always active in output mode (refer to Figure 29 on page 45) 4P B 0 / A I N 0 / S S I/O C T X ei3 XXX Port B0 ADC Analog Input 0 or SPI Slave Select (active low) Caution: No negative current injec- tion allowed on this pin.

5 PB1/AIN1/SCK I/O C T X XXX Port B1 ADC Analog Input 1 or SPI Serial

6 PB2/AIN2/MISO I/O C T X XXX Port B2 ADC Analog Input 2 or SPI Master

7 PB3/AIN3/MOSI I/O C T X

XXX Port B3 ADC Analog Input 3 or SPI Master Out / Slave In Data 81) PB4/AIN4/CLKIN/ COMPIN- I/O C T X XXX Port B4 ADC Analog Input 4 or External clock input 91) PB5/AIN5 I/O C T X XXX Port B5 ADC Analog Input 5 101) PB6/AIN6 I/O C T X XXX Port B6 ADC Analog Input 6 111) PA7 I/O C T HS X ei1 X X Port A7

12 PA6 /MCO/

ICCCLK/BREAK I/O C T X ei1 XX Port A6 Main Clock Output or In-Circuit Communication Clock or External BREAK Caution: During normal operation this pin must be pulled- up, internal- ly or externally (external pull-up of 10k mandatory in noisy environ- ment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset puts it back in input pull-up

13 PA5 /ICCDATA/

XX Port A5 In-Circuit Communication Data or Autoreload Timer PWM3

14 PA4/ATPWM2 I/O C T HS X XX Port A4 Autoreload Timer PWM2

15 PA3/ATPWM1 I/O C T HS X

XX Port A3 Autoreload Timer PWM1

16 PA2/ATPWM0 I/O C T HS X XX Port A2 Autoreload Timer PWM0

17 PA1/ATIC I/O C T HS X XX Port A1 Autoreload Timer Input Capture

181) PA0/LTIC I/O C T HS X XX Port A0 Lite Timer Input Capture 192) OSC2/PC1 I/O X X Port C13) Resonator oscillator inverter output 202) OSC1/CLKIN/PC0 I/O X X Port C03) Resonator oscillator inverter input or External clock input Pin No. Pin Name Type Level Port / Control Main Function (after reset) Alternate Function SO20 Input Output Input Output float wpu int ana OD PP

3 REGISTER AND MEMORY MAP

64 Kbytes of memories and I/O registers. up to 128 bytes for the stack from 180h to 1FFh. are located in Sector 0 (F000h-FFFFh). Figure 3. Memory Map

1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area but are special bytes containing also the

can still be obtained through these four addresses.

1 Kbyte

3 Kbytes

Table 2. Hardware Register Map

ST7L15, ST7L19 Legend: x = undefined, R/W = read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In i nput configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the Debug Module registers, see ST7 ICC Protocol Reference Manual. 0031h 0032h 0033h SPI SPIDR SPICR SPICSR SPI Data I/O Register SPI Control Register SPI Control Status Register xxh 0xh 00h R/W R/W R/W 0034h 0035h 0036h ADC ADCCSR ADCDRH ADCDRL A/D Control Status Register A/D Data Register High Data Low Register 00h xxh 0xh R/W Read Only R/W 0037h ITC EICR External Interrupt Control Register 00h R/W 0038h MCC MCCSR Main Clock Contro l/Status Register 00h R/W 0039h 003Ah Clock and Reset RCCR SICSR RC oscillator Control Register System Integrity Control/Status Register FFh 0110 0xx0b R/W R/W 003Bh PLL clock select PLLTST PLL test register 00h R/W 003Ch ITC EISR External Interrupt Selection Register 0Ch R/W 003Dh to 0048h Reserved area (12 bytes) 0049h 004Ah AWU AWUPR AWUCSR AWU Prescaler Register AWU Control/Status Register FFh 00h R/W R/W 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h DM DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DMCR2 DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low DM Control Register 2 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W 0052h to 007Fh Reserved area (46 bytes) Address Block Register Label Register Name Reset Status Remarks

ST7L15, ST7L19

4 FLASH PROGRAM MEMORY

4.1 INTRODUCTION

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Program- ming. The array matrix organization allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 MAIN FEATURES

■ ICP (In-Circuit Programming) ■ IAP (In-Application Programming) ■ ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM ■ Sector 0 size configurable by option byte ■ Readout and write protection

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different ways: – Insertion in a programming tool. In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be pro- grammed or erased. – In-Circuit Programming. In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board. – In-Application Programming. In this mode, sector 1 and data EEPROM (if present) can be programmed or erased without removing the device from the application board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Commu- nication) which allows an ST7 plugged on a print- ed circuit board (PCB) to communicate with an ex- ternal programming device connected via a cable. ICP is performed in three steps: – Switch the ST7 to ICC mode (In-Circuit Com- munications). This is done by driving a specif- ic signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RE- SET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. – Download ICP Driver code in RAM from the ICCDATA pin – Execute ICP Driver code in RAM to program the Flash memory Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In-Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). IAP mode is fully controlled by user software, al- lowing it to be adapted to the user application (such as a user-defined strategy for entering pro- gramming mode or a choice of communications protocol used to fetch the data to be stored). This mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the pro- gramming operation.

4.4 ICC INTERFACE

Figure 4. Typical ICC Interface

1. If the ICCCLK or ICCDATA pins are only used as out-

documentation for recommended resistor values.

1. During the ICP session, the programming tool must

erated by the application during the ICC session.

1. The use of pin 7 of the ICC connector depends on the

fer to the Programming Tool Manual.

1. Pin 9 must be connected to the OSC1 pin of the ST7

OSC2 must be grounded in this case.

1. In 38-pulse ICC mode, t he internal RC oscillator is

pull-up of 10k mandatory in noisy environment).

ST7L15, ST7L19 FLASH PROGRAM MEMORY (cont’d)

4.5 MEMORY PROTECTION

There are two different types of memory protec- tion: Readout Protection and Write/Erase Protec- tion, which can be applied individually.

4.5.1 Readout Protection

Readout protection, when selected, protects against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreaka- ble, the feature provides a very high level of pro- tection for a general purpose microcontroller. Both program and data E 2 memory are protected. In Flash devices, this protection is removed by re- programming the option. In this case, both pro- gram and data E 2 memory are automatically erased and the device can be reprogrammed. Readout protection selection depends on the de- vice type: – In Flash devices it is enabled and removed through the FMP_R bit in the option byte. – In ROM devices it is enabled by the mask option specified in the Option List.

4.5.2 Flash Write/Erase Protection

Write/erase protection, when set, makes it impos- sible to both overwrite and erase program memo- ry. It does not apply to E 2 data. Its purpose is to provide advanced security to applications and pre- vent any change being made to the memory con- tent. Warning: Once set, Write/erase protection can never be removed. A write-protected Flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6 RELATED DOCUMENTATION

For details on Flash programming and ICC proto- col, refer to the ST7 Flash Programming Refer- ence Manual and to the ST7 ICC Protocol Refer- ence Manual

4.7 REGISTER DESCRIPTION

FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing op- erations. When an EPB or anothe r programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

00000 O P T L A T P G M

5 DATA EEPROM

5.1 INTRODUCTION

basic access protocol described in this chapter.

5.2 MAIN FEATURES

Figure 5. EEPROM Block Diagram

0 E2LAT00 0 0 0 E2PGM

5.3 MEMORY ACCESS

sult in an unexpected code being executed. set by software (the E2PGM bit remains cleared). icant Bits of the address can change. LAT bits are cleared simultaneously. It is not possible to read the latched data. This note is illustrated by the Figure 8 on page 16. Figure 6. Data EEPROM Programming Flowchart

Figure 7. Data EEPROM Write Operation If a programming cycle is interrupted (by a reset action), the integrity of the data in memory is not guaranteed.

5.4 POWER SAVING MODES

tion in progress, and data may be corrupted.

5.5 ACCESS ERROR HANDLING

data on the bus is not latched.

5.6 DATA EEPROM READOUT PROTECTION

tion bit (see option byte section). are protected using the same option bit. Figure 8. Data EEPROM Programming Cycle

5.7 REGISTER DESCRIPTION

Bits 7:2 = Reserved, forced by hardware to 0. Table 3. Data EEPROM Register Map and Reset Values

000000 E 2 L A T E 2 P G M

6 CENTRAL PROCESSING UNIT

6.1 INTRODUCTION

6.2 MAIN FEATURES

6.3 CPU REGISTERS

temporary storage areas for data manipulation. (Program Counter High which is the MSB). Figure 9. CPU Registers

ST7L15, ST7L19 CPU REGISTERS (cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions. These bits can be individually tested and/or con- trolled by specific instructions. Bit 4 = H Half carry This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested usin g the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines. Bit 3 = I Interrupt mask This bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET in- structions and is tested by the JRM and JRNM in- structions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. Bit 2 = N Negative This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- tions. Bit 1 = Z Zero This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. 111HINZC

popped from the stack (see Figure 10). mented and the context is pushed on the stack. and the context is popped from the stack. terrupt occupies five locations in the stack area. Figure 10. Stack Manipulation Example

1 SP6 SP5 SP4 SP3 SP2 SP1 SP0

ST7L15, ST7L19

7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a ran ge of utility features for securing the application in critical situations (for example, in case of a power brown-out) and re- ducing the number of external components. Main features ■ Clock Management – 1 MHz internal RC oscillator (enabled by op- tion byte – 1 to 16 MHz External crystal/ceramic resona- tor – External Clock Input (enabled by option byte) – PLL for multiplying the frequency by 8 or 4 (enabled by option byte). Only multiplying by 8 is available for ROM devices. ■ Reset Sequence Manager (RSM) ■ System Integrity Management (SI) – main supply Low Voltage Detection (LVD) with reset generation (enabled by option byte)

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT

The device contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5V to 5.5V). It must be cali- brated to obtain the frequency required in the ap- plication. This is done by the software writing a 10- bit calibration value in the RCCR (RC Control Reg- ister) and in the bits 6:5 in the SICSR (SI Control Status Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), that is, each time the device is reset, the calibration value must be loaded in the RCCR. Predefined calibration values are stored in EEPROM for 3.3V and 5V V DD sup- ply voltages at 25°C, as shown in the following ta- ble. Note: 1. DEE0h, DEE1h, DEE2h, and DEE3h addresses are lo- cated in a reserved area but are special bytes containing also the RC calibration val ues which are read-accessible only in user mode. If all the EEPROM data or Flash space (including the RC calibrati on value locations) has been erased (after the readout pr otection removal), then the RC calibration values c an still be obtained through these four addresses. For compatibility reasons with the SICSR register, CR[1:0] bits are stored in the fifth and sixth position of the DEE1 and DEE3 addresses. Notes: – In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of the se- lection in the option byte. For ST7L1 devices which do not support the internal RC oscillator, the “option byte disabled” mode must be used (35-pulse ICC mode entry, clock provided by the tool). – For more information on the frequency and accu- racy of the RC oscillator see “ELECTRICAL CHARACTERISTICS” on page 98. – To improve clock stability and frequency accura- cy, it is recommended to place a decoupling ca- pacitor, typically 100nF, between the V DD and VSS pins as close as possible to the ST7 device. – These bytes are systematically programmed by ST, including on FASTROM devices. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the RC frequency using an ex- ternal reference signal. RCCR Conditions ST7L1 Address RCCRH0 V DD = 5V TA = 25°C fRC = 1 MHz DEE0h1) (CR[9:2]) RCCRL0 DEE1h 1) (CR[1:0]) RCCRH1 V DD = 3.3V TA = 25°C fRC = 1 MHz DEE2h1) (CR[9:2]) RCCRL1 DEE3h 1) (CR[1:0])

7.2 PHASE LOCKED LOOP

fOSC is driven by the external clock. Figure 11. PLL Output Frequency Timing of the LOCKED bit in the SICSR register.

1. It is possible to obtain fOSC = 4 MHz in the 3.3V

7.3 REGISTER DESCRIPTION

Bits 7:2 = Reserved, must be kept cleared. and write it to this register at start-up. SICSR register. Refer to section 7.6.3 on page 30.

000000 MCO SMS

Figure 12. Clock Management Block Diagram

7.4 MULTI-OSCILLATOR (MO)

CAL CHARACTERISTICS for more details.

7.4.1 External Clock Source

the OSC1 pin while the OSC2 pin is tied to ground. is selected by default as the external clock.

7.4.2 Crystal/Ceramic Oscillators

7.4.3 Internal RC Oscillator

wise they are general purpose I/O. Table 4. ST7 Clock Sources

7.5 RESET SEQUENCE MANAGER (RSM)

7.5.1 Introduction

fer to section 12.2.1 on page 95 for further details. ways kept low during the delay phase. dresses FFFEh-FFFFh in the ST7 memory map. Figure 13. RESET Sequence Phases

7.5.2 Asynchronous External RESET Pin

output with integrated R ON weak pull-up resistor. can enter the RESET state even in HALT mode.

Figure 14. Reset Block Diagram Note 1: See “Illegal Opcode Reset” on page 95 for more details on illegal opcode reset conditions.

7.5.3 External Power-On RESET

specified for the selected fOSC frequency.

7.5.4 Internal Low Voltage Detector (LVD)

VDD <V IT- (falling edge) as shown in Figure 15.

7.5.5 Internal Watchdog RESET

Watchdog counter overflow is shown in Figure 15. low during at least tw(RSTL)out. Figure 15. RESET Sequences

7.6 SYSTEM INTEGRITY MANAGEMENT (SI)

managed by the SICSR register. fer to section 12.2.1 on page 95 for further details.

7.6.1 Low Voltage Detector (LVD)

down, keeping the ST7 in reset. The LVD function is illustrated in Figure 16. Figure 16. Low Voltage Detector vs Reset

Figure 17. Reset and Supply Management Block Diagram

7.6.2 Low-Power Modes

HALT The SICSR register is frozen.

ST7L15, ST7L19 SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)

7.6.3 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0110 0xx0 (6xh) Bit 7 = Reserved (should be 0) Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad- justment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer to section 7.3 on page 22. Bit 4 = WDGRF Watchdog Reset flag This bit indicates that the last Reset was generat- ed by the Watchdog peripheral. It is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given in the following table. Bit 3 = LOCKED PLL Locked Flag This bit is set and cleared by hardware. It is set au- tomatically when the PLL reaches its operating fre- quency. 0: PLL not locked 1: PLL locked Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generat- ed by the LVD block. It is set by hardware (LVD re- set) and cleared by software (by reading). When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Bits 1:0 = Reserved (should be 0) Application notes The LVDRF flag is not cleared when another RE- SET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the origi- nal failure. In this case, a watchdog reset can be detected by software while an external reset can not. PLL TEST REGISTER (PLLTST) Read/Write Reset Value: 0000 0000(00h) Bit 7: PLLdiv2 PLL clock divide by 2 This bit is read or write by software and cleared by hardware after reset. This bit divides the PLL out- put clock by 2. 0: PLL output clock 1: Divide by 2 of PLL output clock Refer to “Clock Management Block Diagram” on page 23. Note: Write of this bit is effective after two t CPU cy- cles (if system clock is 8 MHz) or else one cycle (if system clock is 4 MHz), that is, effective time is 250ns. Bits 6:0: Reserved, must always be cleared. Res CR1 CR0 WDG RF LOCKED LVD RF Res Res RESET Sources LVDRF WDGRF External RESET pin 0 0 Watchdog 0 1 LVD 1 X PLLdiv2 0 0 0 0 0 0 0

ST7L15, ST7L19

8 INTERRUPTS

The ST7 core may be interrupted by one of two dif- ferent methods: Maskable hardware interrupts as listed in Table 5, “Interrupt Mapping,” on page 32 and a non-maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Fig- ure 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: – Normal processing is suspended at the end of the current instruction execution. – The PC, X, A and CC registers are saved onto the stack. – The I bit of the CC register is set to prevent addi- tional interrupts. – The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table for vector address- es). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit is cleared and the main program resumes. Priority Management By default, a servicing interrupt cannot be inter- rupted because the I bit is set by hardware enter- ing in interrupt routine. In the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the Interrupt Map- ping table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifi- cally mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT” column in the Interrupt Mapping ta- ble).

8.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc- tion is executed regardless of the state of the I bit. It is serviced according to the flowchart in Figure 18.

8.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to le ave the HALT low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt tr iggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the Mis- cellaneous or Interrupt register (if available) ap- plies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity.

8.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: – The I bit of the CC register is cleared. – The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status register or – Access to the status register while the flag is set followed by a read or write of an associated reg- ister. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear se- quence is executed.

Figure 18. Interrupt Processing Flowchart Table 5. Interrupt Mapping

1. This interrupt exits the MCU from “Auto Wake-Up from Halt” mode only.
2. These interrupts exit the MCU from “ACTIVE HALT” mode only.

0 AWU Auto Wake-Up Interrupt AWUCSR yes 1) FFFAh-FFFBh

5 LITE TIMER LITE TIMER RTC2 interrupt LTCSR2 no FFF0h-FFF1h

6 Not used FFEEh-FFEFh

7 Not used FFECh-FFEDh

8 AT TIMER

9 AT TIMER Overflow Interrupt ATCSR yes

10 LITE TIMER LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h

11 LITE TIMER RTC1 Interrupt LTCSR yes 2) FFE4h-FFE5h

12 SPI SPI Peripheral Interrupts SPICSR yes FFE2h-FFE3h

13 AT TIMER AT TIMER Overflow Interrupt ATCSR2 no FFE0h-FFE1h

(Port B0) according to Table 6. (Port B3) according to Table 6. (Port A7) according to Table 6. (Port A0) according to Table 6.

1. These 8 bits can be written only when the I bit in
2. Changing the sensitivity of a particular external

Table 6. Interrupt Sensitivity Bits

1. PB4 cannot be used as an external interrupt in HALT

00 P B 0 *

00 P B 3 *

ST7L15, ST7L19 INTERRUPTS (cont’d) Bits 3:2 = ei1[1:0] ei1 pin selection These bits are written by software. They select the Port A I/O pin used for the ei1 external interrupt ac- cording to the table below. External Interrupt I/O pin selection * Reset State Bits 1:0 = ei0[1:0] ei0 pin selection These bits are written by software. They select the Port A I/O pin used for the ei0 external interrupt ac- cording to the table below. External Interrupt I/O pin selection * Reset State ei11 ei10 I/O Pin 0 0 PA4 0 1 PA5 1 0 PA6 1 1 PA7* ei01 ei00 I/O Pin 0 0 PA0 * 0 1 PA1 1 0 PA2 1 1 PA3

9 POWER SAVING MODES

9.1 INTRODUCTION

Figure 19. Power Saving Mode Transitions

9.2 SLOW MODE

the available supply voltage.

1. The CPU and peripherals are clocked at this

Figure 20. SLOW Mode Clock Transition

9.3 WAIT MODE

sumption mode by stopping the CPU. Figure 21. WAIT Mode Flowchart

1. Before servicing an interrupt, the CC register is pushed

256 OR 4096 CPU CLOCK

9.4 HALT MODE

as an external or auxiliary oscillator). tion 15.1 on page 126 for more details). Figure 22. HALT Timing Overview Figure 23. HALT Mode Flowchart

1. WDGHALT is an option bit. See option byte section for
2. Peripheral clocked with an external clock source can
3. Only some specific interrupts can exit the MCU from

“Interrupt Mapping,” on page 32 for more details.

1. Before servicing an interrupt, the CC register is pushed
2. If the PLL is enabled by option byte, it outputs the clock

after a delay of tSTARTUP (see Figure 11 on page 22).

9.4.1 Halt Mode Recommendations

wake up the microcontroller from HALT mode. gram memory with the value 0x8E.

9.5 ACTIVE HALT MODE

ping,” on page 32) or a RESET. as external or auxiliary oscillator). active does not generate a RESET. fined delay in this power saving mode. Figure 24. ACTIVE HALT Timing Overview

Figure 25. ACTIVE HALT Mode Flowchart

1. This delay occurs only if the MCU exits ACTIVE HALT
2. Peripherals clocked with an ex ternal clock source can
3. Only the RTC1 interrupt and some specific interrupts

Table 5, “Interrupt Mapping,” on page 32 for more details.

1. Before servicing an interrupt, the CC register is pushed

9.6 AUTO WAKE-UP FROM HALT MODE

rate realtime clock available). Figure 26. AWUFH Mode Block Diagram software reading the AWUCSR register.

set (see Section 9.4 HALT MODE). Figure 27. AWUF Halt Timing Diagram

Figure 28. AWUFH Mode Flowchart

1. WDGHALT is an option bit. See option byte section for
2. Peripheral clocked with an external clock source can
3. Only an AWUFH interrupt and some specific interrupts
4. Before servicing an interrupt, the CC register is pushed

and recovered when the CC register is popped.

1. If the PLL is enabled by t he option byte, it outputs the

9.6.0.1 Register Description

value in the AWUPRE register. before waking up automatically. Table 7. AWU Register Map and Reset Values

00000 A W U F A W U M A W U E N

ST7L15, ST7L19

10 I/O PORTS

10.1 INTRODUCTION

The I/O ports allow data transfer. An I/O port con- tains up to eight pins. Each pin can be pro- grammed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can in- clude external interrupt, alternate signal input/out- put for on-chip peripherals or analog input.

10.2 FUNCTIONAL DESCRIPTION

A Data Register (DR) and a Data Direction Regis- ter (DDR) are always associated with each port. The Option Register (OR), which allows input/out- put options, may or may not be implemented. The following description take s into account the OR register. Refer to the Port Configuration table for device specific information. An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: Bit x corre- sponding to pin x of the port. Figure 29 shows the generic I/O block diagram.

10.2.1 Input Modes

Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin. If an OR bit is available, different input modes can be configured by software: Floating or pull-up. Re- fer to Section 10.3 I/O PORT IMPLEMENTATION for configuration. Notes: 1. Writing to the DR modifies the latch value but does not change the state of the input pin. 2. Do not use read/mod ify/write instructions (BSET/BRES) to modify the DR register.

10.2.1.1 External Interrupt Function

External interrupt capabilit y is selected using the EISR register. If EISR bits are <> 0, the corre- sponding pin is used as external interrupt. In this case, the ORx bit can select the pin as either inter- rupt floating or interrupt pull-up. In this configura- tion, a signal edge or level input on the I/O gener- ates an interrupt request via the corresponding in- terrupt vector (eix). Falling or rising edge sensitivity is programmed in- dependently for each interrupt vector. The Exter- nal Interrupt Control Register (EICR) or the Miscel- laneous Register controls this sensitivity, depend- ing on the device. A device may have up to seven external interrupts. Several pins may be tied to one external interrupt vector. Refer to “PIN DESCRIPTION” on page 5 to see which ports have external interrupts. If several I/O interrupt pins on the same interrupt vector are selected simultaneously, they are logi- cally combined. For this reason, if one of the inter- rupt pins is tied low, it may mask the others. External interrupts are hardware interrupts. Fetch- ing the corresponding interrupt vector automatical- ly clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spu- rious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input, which is switched to '1' when the external interrupt is disa- bled by the OR register. To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) must be selected before changing the OR register bit and configuring the appropriate sensitivity again. Caution: If a pin level change occurs during these operations (asynchronous signal input), as inter- rupts are generated according to the current sen- sitivity, it is advised to disable all interrupts before and to re-enable them after the complete previous sequence in order to avoid an external interrupt occurring on the unwanted edge. This corresponds to the following steps: 1. To enable an external interrupt: – Set the interrupt mask with the SIM instruction (in cases where a pin level change could oc- cur) – Select rising edge – Enable the external interrupt through the OR register – Select the desired sensitivity if different from rising edge – Reset the interrupt mask with the RIM instruc- tion (in cases where a pin level change could occur) 2. To disable an external interrupt:

ST7L15, ST7L19 I/O PORTS (cont’d) – Set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could occur) – Select falling edge – Disable the external interrupt through the OR register – Select rising edge – Reset the interrupt mask with the RIM instruc- tion (in cases where a pin level change could occur)

10.2.2 Output Modes

Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value. If an OR bit is available, different output modes can be selected by software: Push-pull or open- drain. Refer to “I/O PORT IMPLEMENTATION” on page 47 for configuration. DR Value and Output Pin Status

10.2.3 Alternate Functions

Many ST7 I/Os have one or more alternate func- tions. These may include output signals from, or input signals to, on-chip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports. A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripher- al’s control register). The peripheral configures the I/O as an output and takes priority over standard I/ O programming. The I/O’s state is readable by ad- dressing the corresponding I/O data register. Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this increases current con- sumption. Before using an I/O as an alternate in- put, configure it without interrupt. Otherwise spuri- ous interrupts can occur. Configure an I/O as input floating for an on-chip peripheral signal which can be input and output. Caution: I/Os which can be configured as both an analog and digital alternate function need special attention. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function. DR Push-Pull Open-Drain 0V OL VOL 1V OH Floating

Figure 29. I/O Port General Block Diagram Table 8. Port Mode Options table for device specific information.

Table 9. I/O Configurations

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the

DR register reads the alternate function output status.

1. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate

function reads the pin status given by the DR register content.

rail, connected to the ADC input.

10.3 I/O PORT IMPLEMENTATION

spurious interrupt generation. Figure 30. Interrupt I/O Port State Transitions

10.4 UNUSED I/O PINS

age levels. Refer to section 13.8 on page 113.

10.5 LOW-POWER MODES

10.6 INTERRUPTS

register is cleared (RIM instruction). cause the device to exit from WAIT mode. cause the device to exit from HALT mode.

10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION

Port C is not present on ROM devices. Table 10. Port Configuration (Standard Ports) Table 11. I/O Port Register Map and Reset Values

ST7L15, ST7L19

10.8 MULTIPLEXED INPUT/OUTPUT PORTS

OSC1/PC0 are multiplexed on one pin (pin20) and OSC2/PC1 are multiplexed on another pin (pin19). 0002h PAOR Reset Value MSB 01 00000 LSB 0003h PBDR Reset Value MSB 11 11111 LSB 0004h PBDDR Reset Value MSB 00 00000 LSB 0005h PBOR Reset Value MSB 00 00000 LSB 0006h PCDR Reset Value MSB 00 00001 LSB 0007h PCDDR Reset Value MSB 00 00000 LSB Address (Hex.) Register Label 76543210

11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

11.1.2 Main Features

11.1.3 Functional Description

programmed by the user in 64 increments. Figure 31. Watchdog Block Diagram

– The WDGA bit is set (watchdog enabled). activated, it can be disabled only by a reset. WDGA bit is set and the T6 bit is cleared).

1. The timing variation shown in Table 12 is due to
2. The number of CPU clock cycles applied during

into account in addition to these timings.

11.1.4 Hardware Watchdog Option

WDGA bit in the CR is not used.

11.1.4.1 Using Halt Mode with the WDG

11.1.5 Interrupts

11.1.6 Register Description

Bit 7 = WDGA Activation bit. watchdog can generate a reset. dog option is enabled by option byte. Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB). Table 13. Watchdog Timer Register Map and Reset Values

11.2 DUAL 12-BIT AUTORELOAD TIMER 4 (AT4)

11.2.1 Introduction

capture register and four PWM output channels.

11.2.2 Main Features

Figure 32. Single Timer Mode (ENCNTR2 = 0)

Figure 33. Dual Timer Mode (ENCNTR2 = 1)

11.2.3 Functional Description

11.2.3.1 PWM Mode

ent frequency controlled by CNTR2 and ATR2. minimum value is 1 kHz (ATR register value = 0). minimum value is 8 kHz (ATR register value = 0).

1. The maximum value of ATR is 4094 because it
2. To update the DCRx registers at 32 MHz, the

after a write to the DCRx registers. ing transfer bit (TRANx bit) is set. PWMx outputs driven by Counter 2. At reset, the counter starts counting from 0. Figure 34. PWM Polarity Inversion sion when triggered by the counter overflow input. bled using the OEx bits in the PWMCR register.

11.2.3.2 Dead Time Generation

mable dead time by setting the DTE bit. will take place only after an overflow.

1. Dead time is generated only when DTE = 1 and

output signals will be at their reset state.

1. Half-bridge driving is possible only if polarities of

ping PWM0/PWM1 signals will be generated.

1. Dead Time generation does not work at 1ms

Figure 37. Dead Time Generation

11.2.3.3 Break Function

BPEN bit in the BREAKCR register. respective OEx bit is set in the PWMCR register. hardware at high level and all PWMs are enabled. pins if respective OEx is set (after the inverter). set value, that is 00h (if BREN1 = 1). set value, that is 00h (if BREN2 = 1). Figure 38. Block Diagram of Break Function

11.2.3.4 Output Compare Mode

Preload DCRxH and DCRxL registers.

1. The output compare function is only available

for DCRx values other than 0 (reset value).

1. Duty cycle registers are buffered internally. The

Figure 39. Block Diagram of Output Compare Mode (Single Timer)

11.2.3.5 Input Capture Mode

Figure 40. Block Diagram of Input Capture Mode Figure 41. Input Capture Timing Diagram

ture value. Refer to Figure 42. Figure 42. Long Range Input Capture Block Diagram

1. Since the input capture flags (ICF) for both tim-
2. If the ICS bit changes (from 0 to 1 or from 1 to

– First, reset both ICIE bits. – Finally, set the ICIE bit of desired interrupt.

1. How to compute a pulse length with long input

Refer to Figure 43 on page 61.

8 LSB bits

12 MSB bits

where N = No of overflows of 12-bit CNTR1. Figure 43. Long Range Input Capture Timing Diagram

ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d)

11.2.3.6 One Pulse Mode (available only on

Flash devices) One Pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in dual timer mode that is only for CNTR2, when the OP_EN bit in PWM3CSR regis- ter is set. One Pulse mode is activated by the external LTIC input. The active edge of the LTIC pin is selected by the OPEDGE bit in the PWM3CSR register. After obtaining the active edge of the LTIC pin, CNTR2 is reset (000h) and PWM3 is set to high. CNTR2 starts counting from 000h and when it reaches the active DCR3 value, PWM3 goes low. Until this time, any further transitions on the LTIC signal will have no effect. If there are LTIC transi- tions after CNTR2 reaches the DCR3 value, CNTR2 is reset again and PWM3 goes high. If there are no more LTIC active edges after the first active edge, CNTR2 counts until it reaches the ARR2 value, it is then reset and PWM3 is set to high. The counter again starts counting from 000h. When it reaches the active DCR3 value, PWM3 goes low, after which the counter counts until it reaches ARR2, it is reset and PWM3 is set to high again, and the cycle continues in this manner. The same operation applies for PWM2, but in this case the comparison is done on DCR2 OP_EN and OPEDGE bits take effect on the fly and are not synchronized with the Counter 2 over- flow. The output bit OP2/3 can be used to invert the po- larity of PWM2/3 in One Pulse mode. The update of these bits (OP2/3) is synchronized with the Counter 2 overflow, provided the TRAN2 bit is set. Notes: 1. The time taken from activation of LTIC input and CNTR2 reset is between 1 and 2 t CPU cycles, that is 125n to 250ns (with 8 MHz fCPU). 2. To avoid spurious interrupts, the LiteTimer input capture interrupt should be disabled while 12-bit ARTimer is in One Pulse mode. 3. Priority of various conditions is as follows for PWM3: Break > One Pulse mode with active LTIC edge > Forced overflow by s/w > One Pulse mode without active LTIC edge > normal PWM operation. 4. It is possible to u pdate DCR2/3 and OP2/3 at the Counter 2 reset because the update is syn- chronized with the counter reset. This is managed by the overflow interrupt which is generated if the counter is reset either due to ARR match or active pulse at LTIC pin. 5. DCR2/3 and OP2/3 update in One Pulse mode is done dynamically using force update in soft- ware. 6. DCR3 update in this mode is not synchronized with any event. That may lead to a longer next PWM3 cycle duration than expected just after the change (refer to Figure 46). 7. In One Pulse mode, the ATR2 value must be greater than the DCR2/3 value for PWM2/3 (oppo- site to normal PWM mode). 8. If there is an active edge on the LTIC pin after the counter has reset due to an ARR2 match, then the timer again is reset and appears as modified Duty cycle, depending on whether the new DCR value is less than or more than the previous value. 9. The TRAN2 bit should be set along with the FORCE2 bit with the same instruction after a write to the DCR register. 10. ARR2 value should be changed after an over- flow in One Pulse mode to avoid any irregular PWM cycle. 11. When exiting from One Pulse mode, the OP_EN bit in the PWM3CSR register should be reset first and then the ENCNTR2 bit (if Counter 2 must be stopped). How to enter One Pulse mode: 1. Load ATR2H/ATR2L with required value. 2. Load DCR3H/DCR3L for PWM3. ATR2 value must be greater than DCR3. 3. Set OP3 in PWM3CSR if polarity change is re- quired. 4. Select CNTR2 by setting ENCNTR2 bit in ATCSR2. 5. Set TRAN2 bit in ATCSR2 to enable transfer. 6. "Wait for Overflow" by checking the OVF2 flag in ATCSR2. 7. Select counter clock using CK<1:0> bits in ATC- SR. 8. Set OP_EN bit in PWM3CSR to enable One Pulse mode. 9. Enable PWM3 by OE3 bit of PWMCR. The "Wait for Overflow" in step 6 can be replaced by forced update. Follow the same procedure for PWM2 with the bits corresponding to PWM2. Note: When break is applied in One Pulse mode, DUAL 12-BIT AUTORELOAD TIMER 4, CNTR2, DCR2/3 and ATR2 registers are reset. Conse-

Figure 44. Block Diagram of One Pulse Mode Figure 45. One Pulse Mode Timing Diagram Figure 46. Dynamic DCR2/3 update in One Pulse Mode

000 DCR2/3 000 DCR2/3 ATR2 000

11.2.3.7 Force Update (available only on Flash

Figure 47. Force Overflow Timing Diagram

11.2.4 Low Power Modes

11.2.5 Interrupts

in the CC register is reset (RIM instruction).

ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d)

11.2.6 Register Description

TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0x00 0000 (x0h) Bit 7 = Reserved, must be kept cleared Bit 6 = ICF Input Capture Flag This bit is set by hardware and cleared by software by reading the ATICR register (a read access to ATICRH or ATICRL will clear this flag). Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Bit 5 = ICIE IC Interrupt Enable This bit is set and cleared by software. 0: Input capture interrupt disabled 1: Input capture interrupt enabled Bits 4:3 = CK[1:0] Counter Clock Selection These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter. Bit 2 = OVF1 Overflow Flag This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter CNTR1 from FFFh to ATR1 value. 0: No counter overflow occurred 1: Counter overflow occurred Bit 1 = OVFIE1 Overflow Interrupt Enable This bit is read/write by software and cleared by hardware after a reset. 0: Overflow interrupt disabled. 1: Overflow interrupt enabled. Bit 0 = CMPIE Compare Interrupt Enable This bit is read/write by software and cleared by hardware after a reset. It can be used to mask the interrupt generated when any of the CMPFx bit is set. 0: Output compare interrupt disabled. 1: Output Compare interrupt enabled. COUNTER REGISTER 1 HIGH (CNTR1H) Read only Reset Value: 0000 0000 (00h) COUNTER REGISTER 1 LOW (CNTR1L) Read only Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared Bits 11:0 = CNTR1[11:0] Counter Value This 12-bit register is read by software and cleared by hardware after a reset. The counter CNTR1 in- crements continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. The CNTRH register can be in- cremented between the two reads, and in order to be accurate when f TIMER =f CPU, the software should take this into account when CNTRL and CNTRH are read. If CNTRL is close to its highest value, CNTRH could be incremented before it is read. When a counter overflow occurs, the counter re- starts from the value specified in the ATR1 regis- ter.

0 ICF ICIE CK1 CK0 OVF1 OVFIE1 CMPIE

Counter Clock Selection CK1 CK0 OFF 0 0 fLTIMER (1ms timebase @ 8 MHz) 0 1 fCPU 10 15 8

0000 CNTR1_

CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_

ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) AUTORELOAD REGISTER (ATR1H) Read / Write Reset Value: 0000 0000 (00h) AUTORELOAD REGISTER (ATR1L) Read / Write Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared Bits 11:0 = ATR1[11:0] Autoreload Register 1 This is a 12-bit register which is written by soft- ware. The ATR1 register value is automatically loaded into the upcounter CNTR1 when an over- flow occurs. The register value is used to set the PWM frequency. PWM OUTPUT CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) Bits 7:0 = OE[3:0] PWMx Output Enable. These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled. PWMx Output Alternate Function disabled (I/O pin free for general purpose I/O) 1: PWM mode enabled PWMx CONTROL STATUS REGISTER (PWMxCSR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:4 = Reserved, must be kept cleared Bit 3 = OP_EN One Pulse Mode Enable (not appli- cable to ROM devices) This bit is read/write by software and cleared by hardware after a reset. This bit enables the One Pulse feature for PWM2 and PWM3. (Only availa- ble for PWM3CSR) 0: One Pulse mode disable for PWM2/3. 1: One Pulse mode enable for PWM2/3. Bit 2 = OPEDGE One Pulse Edge Selection (not applicable to ROM devices) This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the LTIC signal for One Pulse feature. This bit will be effective only if OP_EN bit is set. (Only available for PWM3CSR) 0: Falling edge of LTIC is selected. 1: Rising edge of LTIC is selected. Bit 1 = OPx PWMx Output Polarity This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM signal. 0: The PWM signal is not inverted. 1: The PWM signal is inverted. Bit 0 = CMPFx PWMx Compare Flag This bit is set by hardware and cleared by software by reading the PWMxCSR register. It indicates that the upcounter value matches the Active DCRx register value. 0: Upcounter value does not match DCRx value. 1: Upcounter value matches DCRx value. 15 8 0 0 0 0 ATR11 ATR10 ATR9 ATR8 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0

0 OE3 0 OE2 0 OE1 0 OE0

0 0 0 0 OP_EN OPEDGE OPx CMPFx

ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) BREAK CONTROL REGISTER (BREAKCR) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = Reserved, must be kept cleared Bit 6 = BREDGE Break Input Edge Selection (not applicable to ROM devices) This bit is read/write by software and cleared by hardware after reset. It selects the active level of Break signal. 0: Low level of Break selected as active level. 1: High level of Break selected as active level. Bit 5 = BA Break Active This bit is read/write by software, cleared by hard- ware after reset and set by hardware when the BREAK pin is low. It acti vates/deactivates the Break function. 0: Break not active 1: Break active Bit 4 = BPEN Break Pin Enable This bit is read/write by software and cleared by hardware after Reset. 0: Break pin disabled 1: Break pin enabled Bits 3:0 = PWM[3:0] Break Pattern These bits are read/write by software and cleared by hardware after a reset. They are used to force the four PWMx output signals into a stable state when the Break function is active and correspond- ing OEx bit is set. PWMx DUTY CYCLE REGISTER HIGH (DCRxH) Read / Write Reset Value: 0000 0000 (00h) PWMx DUTY CYCLE REGISTER LOW (DCRxL) Read / Write Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value This 12-bit value is writ ten by software. It defines the duty cycle of the corresponding PWM output signal (see Figure 35). In PWM mode (OEx = 1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see Figure 35 ). In Output Compare mode, they define the value to be com- pared with the 12-bit upcounter value. INPUT CAPTURE REGISTER HIGH (ATICRH) Read only Reset Value: 0000 0000 (00h) INPUT CAPTURE REGISTER LOW (ATICRL) Read only Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared

0 BREDGE BA BPEN PWM3 PWM2 PWM1 PWM0

0 0 0 0 DCR11 DCR10 DCR9 DCR8 DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 15 8 0 0 0 0 ICR11 ICR10 ICR9 ICR8 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) Bits 11:0 = ICR[11:0] Input Capture Data This is a 12-bit register which is readable by soft- ware and cleared by hardware after a reset. The ATICR register contains the captured value of the 12-bit CNTR1 register when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS). Capture will only be performed when the ICF flag is cleared. BREAK ENABLE REGISTER (BREAKEN) Read/Write Reset Value: 0000 0011 (03h) Bits 7:2 = Reserved, must be kept cleared Bit 1 = BREN2 Break Enable for Counter 2 (forced at high level in ROM devices) This bit is read/write by software. It enables the break functionality for Counter 2 if BA bit is set in BREAKCR. It controls PWM2/3 if ENCNTR2 bit is set. 0: No Break applied for CNTR2 1: Break applied for CNTR2 Bit 0 = BREN1 Break Enable for Counter 1 (forced at high level in ROM devices) This bit is read/write by software. It enables the break functionality for Counter 1. If BA bit is set, it controls PWM0/1 by default, and controls PWM2/3 also if ENCNTR2 bit is reset. 0: No Break applied for CNTR1 1: Break applied for CNTR1 TIMER CONTROL REGISTER2 (ATCSR2) Read/Write Reset Value: 0000 0011 (03h) Bit 7 = FORCE2 Force Counter 2 Overflow (not applicable to ROM devices) This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It is reset by hard- ware one CPU clock cycle after Counter 2 over- flow has occurred. 0: No effect on CNTR2 1: Loads FFFh in CNTR2 Note: This bit must not be reset by software Bit 6 = FORCE1 Force Counter 1 Overflow (forced at high level in ROM devices) This bit is read/set by software. When set, it loads FFFh in CNTR1 register. It is reset by hardware one CPU clock cycle after Counter 1 overflow has occurred. 0: No effect on CNTR1 1: Loads FFFh in CNTR1 Note: This bit must not be reset by software Bit 5 = ICS Input Capture Shorted This bit is read/write by software. It allows the AT- timer CNTR1 to use the LTIC pin for long input capture. 0: ATIC for CNTR1 input capture 1: LTIC for CNTR1 input capture Bit 4 = OVFIE2 Overflow Interrupt 2 Enable This bit is read/write by software and controls the overflow interrupt of Counter 2. 0: Overflow interrupt disabled 1: Overflow interrupt enabled Bit 3 = OVF2 Overflow Flag This bit is set by hardware and cleared by software by reading the ATCSR2 register. It indicates the transition of the Counter 2 from FFFh to ATR2 val- ue. 0: No counter overflow occurred 1: Counter overflow occurred Bit 2 = ENCNTR2 Enable Counter 2 for PWM2/3 This bit is read/write by software and switches the PWM2/3 operation to the CNTR2 counter. If this bit is set, PWM2/3 will be generated using CNTR2. 0: PWM2/3 is generated using CNTR1. 1: PWM2/3 is generated using CNTR2. Note: Counter 2 becomes frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the counter will restart from the last value.

000000 B R E N 2 B R E N 1

1 ICS OVFIE2 OVF2 ENCNT

ST7L15, ST7L19 DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d) Bit 1 = TRAN2 Transfer Enable 2 This bit is read/write by software, cleared by hard- ware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2. It allows the value of the Preload DCRx registers to be transferred to the Active DCRx registers after the next overflow event. The OPx bits are transferred to the shadow OPx bits in the same way. Notes: 1. DCR2/3 transfer is co ntrolled using this bit if ENCNTR2 bit is set. 2. This bit must not be reset by software. Bit 0 = TRAN1 Transfer Enable 1 This bit is read/write by software, cleared by hard- ware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR1. It allows the value of the Preload DCRx registers to be transferred to the Active DCRx reg- isters after the next overflow event. The OPx bits are transferred to the shadow OPx bits in the same way. Notes: 1. DCR0,1 transfers are always controlled using this bit. 2. DCR2/3 transfer is co ntrolled using this bit if ENCNTR2 is reset. 3.This bit must not be reset by software AUTORELOAD REGISTER2 (ATR2H) Read / Write Reset Value: 0000 0000 (00h) AUTORELOAD REGISTER2 (ATR2L) Read / Write Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared Bits 11:0 = ATR2[11:0] Autoreload Register 2 This is a 12-bit register which is written by soft- ware. The ATR2 register value is automatically loaded into the upcounter CNTR2 when an over- flow of CNTR2 occurs. The register value is used to set the PWM2/PWM3 frequency when ENCNTR2 is set. DEAD TIME GENERATOR REGISTER (DTGR) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = DTE Dead Time Enable This bit is read/write by software. It enables a dead time generation on PWM0/PWM1. 0: No Dead time insertion. 1: Dead time insertion enabled. Bits 6:0 = DT[6:0] Dead Time Value These bits are read/write by software. They define the dead time inserted between PWM0/PWM1. Dead time is calculated as follows: Dead Time = DT[6:0] x Tcounter1 Note: 1. If DTE is set and DT[6:0] = 0, PWM output sig- nals are at their reset state. 15 8 0 0 0 0 ATR11 ATR10 ATR9 ATR8 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 DTE DT6 DT5 DT4 DT3 DT2 DT1 DT0

Table 14. Register Map and Reset Values

10 ATR1H

11 ATR1L

12 PWMCR

13 PWM0CSR

14 PWM1CSR

15 PWM2CSR

16 PWM3CSR

17 DCR0H

18 DCR0L

19 DCR1H

20 ATICRL

ST7L15, ST7L19

21 ATCSR2

22 BREAKCR

23 ATR2H

24 ATR2L

25 DTGR

26 BREAKEN

(Hex.) Register Label 765 4 3 2 1 0

11.3 LITE TIMER 2 (LT2)

11.3.1 Introduction

bit upcounters and an 8-bit input capture register.

11.3.2 Main Features

Figure 48. Lite Timer 2 Block Diagram

11.3.3 Functional Description

11.3.3.1 Timebase Counter 1

riod between two counter overflow events is 1 ms. software reading the LTCSR1 register.

11.3.3.2 Input Capture

LTICR1 register contains the MSB of Counter 1. ICF bit is cleared by reading the LTICR register. capture is inhibited if the ICF bit is set.

11.3.3.3 Timebase Counter 2

rupt request is generated if the TB2IE bit is set. Figure 49. Input Capture Timing Diagram.

ST7L15, ST7L19 LITE TIMER (cont’d)

11.3.4 Low Power Modes

11.3.5 Interrupts

Note: The TBxF and ICF interrupt events are con- nected to separate interrupt vectors (see Inter- rupts chapter). They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction).

11.3.6 Register Description

LITE TIMER CONTROL/STATUS REGISTER 2 (LTCSR2) Read / Write Reset Value: 0000 0000 (00h) Bits 7:2 = Reserved, must be kept cleared. Bit 1 = TB2IE Timebase 2 Interrupt enable This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled Bit 0 = TB2F Timebase 2 Interrupt Flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred LITE TIMER AUTO RELOAD REGISTER (LTARR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:0 = AR[7:0] Counter 2 Reload Value These bits register is read/write by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. LITE TIMER COUNTER 2 (LTCNTR) Read only Reset Value: 0000 0000 (00h) Bits 7:0 = CNT[7:0] Counter 2 Reload Value This register is read by software. The LTARR val- ue is automatically loaded into Counter 2 (LTCN- TR) when an overflow occurs. LITE TIMER CONTROL/STATUS REGISTER (LTCSR1) Read / Write Reset Value: 0x00 0000 (x0h) Bit 7 = ICIE Interrupt Enable This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Mode Description SLOW No effect on Lite timer (this peripheral is driven directly by f OSC/32) WAIT No effect on Lite timer ACTIVE HALT No effect on Lite timer HALT Lite timer stops counting Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Active Halt Exit from Halt Timebase 1 Event TB1F TB1IE Yes Yes NoTimebase 2 Event TB2F TB2IE No IC Event ICF ICIE No

000000 T B 2 I E T B 2 F

A R 7A R 7A R 7A R 7A R 3A R 2A R 1A R 0 CNT7 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0 ICIE ICF TB TB1IE TB1F - - -

does not change the bit value. This bit is set and cleared by software. This bit is set and cleared by software. Table 15. Lite Timer Register Map and Reset Values

08 LTCSR2

09 LTARR

ST7L15, ST7L19 ON-CHIP PERIPHERALS (cont’d)

11.4 SERIAL PERIPHERAL INTERFACE (SPI)

11.4.1 Introduction

The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves.

11.4.2 Main Features

■ Full duplex synchronous transfers (on three lines) ■ Simplex synchronous transfers (on two lines) ■ Master or slave operation ■ 6 master mode frequencies (fCPU/4 max.) ■ fCPU/2 max. slave mode frequency (see note) ■ SS Management by software or hardware ■ Programmable clock polarity and phase ■ End of transfer interrupt flag ■ Write collision, Master Mode Fault and Overrun flags Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence.

11.4.3 General Description

Figure 50 on page 77 shows the serial peripheral interface (SPI) block diagram. There are three reg- isters: – SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR) The SPI is connected to external devices through four pins: – MISO: Master In / Slave Out data – MOSI: Master Out / Slave In data – SCK: Serial Clock out by SPI masters and in- put by SPI slaves –S S : Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves indi- vidually and to avoid contention on the data lines. Slave SS inputs can be driven by stand- ard I/O ports on the master Device.

Figure 50. Serial Peripheral Interface Block Diagram

11.4.3.1 Functional Description

slave (most significant bit first). the master device via the SCK pin). simplex communication is possible). Figure 51. Single Master/ Single Slave Application

11.4.3.2 Slave Select Management

shift register (see Section 11.4.5.3). Figure 52. Generic SS Figure 53. Hardware/Software Slave Select Management

ST7L15, ST7L19 SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0). How to operate the SPI in master mode To operate the SPI in master mode, perform the following steps in order: 1. Write to the SPICR register: – Select the clock frequency by configuring the SPR[2:0] bits. – Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 54 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: – Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: – Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high). Important note: if the SPICSR register is not writ- ten first, the SPICR register setting (MSTR bit) may be not taken into account. The transmit sequence begins when software writes a byte in the SPIDR register.

11.4.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most sig- nificant bit first. When data transfer is complete: – The SPIF bit is set by hardware. – An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register Note: While the SPIF bit is se t, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read.

11.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the fol- lowing actions: – Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 54). Note: The slave must have the same CPOL and CPHA settings as the master. – Manage the SS pin as described in Section 11.4.3.2 and Figure 52. If CPHA = 1 SS must be held low continuously. If CPHA = 0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions.

11.4.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most sig- nificant bit first. The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. When data transfer is complete: – The SPIF bit is set by hardware. – An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICS R register while the SPIF bit is set 2. A write or a read to the SPIDR register Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 11.4.5.2).

11.4.4 Clock Phase and Clock Polarity

master and the slave device. Figure 54. Data Clock Timing Diagram Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

11.4.5 Error Flags

11.4.5.1 Master Mode Fault (MODF)

quest is generated if the SPIE bit is set.

1. A read access to the SPICSR register while the
2. A write to the SPICR register.

inal state during or after this clearing sequence. the MODF bit clearing sequence. slave mode with the MODF bit set.

11.4.5.2 Overrun Condition (OVR)

generated if the SPIE bit is set.

11.4.5.3 Write Collision Error (WCOL)

the software write will be unsuccessful. is set (the WCOL bit is a status flag only). Figure 55. Clearing the WCOL Bit (Write Collision Flag) Software Sequence

11.4.5.4 Single Master and Multimaster

that time, thus disabling the slave devices. through the serial peripheral interface system. Figure 56. Single Master / Multiple Slave Configuration

ST7L15, ST7L19 SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.6 Low Power Modes

11.4.6.1 Using the SPI to wake up the device

In slave configuration, the SPI is able to wake up the device from HALT mode through a SPIF inter- rupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from HALT mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from HALT mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake up the device from HALT mode only if the Slave Select signal (exter- nal SS pin or the SSI bit in the SPICSR register) is low when the device en ters HALT mode. So, if Slave selection is configured as external (see Sec- tion 11.4.3.2), make sure the master drives a low level on the SS pin when the slave enters HALT mode.

11.4.7 Interrupts

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ation resumes when the device is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the soft- ware is running (interrupt vector fetching). If several data are received before the wake- up event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Transfer Event SPIF SPIE Yes Yes Master Mode Fault Event MODF No Overrun Error OVR

11.4.8 Register Description

This bit is set and cleared by software. Note: This bit has no effect in slave mode. tions of the MISO and MOSI pins are reversed. This bit is set and cleared by software. CPHA settings as the master. Note: These 2 bits have no effect in slave mode. Table 16. SPI Master Mode SCK Frequency

ST7L15, ST7L19 SERIAL PERIPHERAL INTERFACE (cont’d) SPI CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only) This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the device and an exter- nal device has been completed. Note: While the SPIF bit is se t, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read. Bit 6 = WCOL Write Collision status (Read only) This bit is set by hardware when a write to the SPIDR register is done during a transmit se- quence. It is cleared by a software sequence (see Figure 55). 0: No write collision occurred 1: A write collision has been detected Bit 5 = OVR SPI Overrun error (Read only) This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 11.4.5.2). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Bit 4 = MODF Mode Fault flag (Read only) This bit is set by hardware when the SS pin is pulled low in master mode (see Section 11.4.5.1 Master Mode Fault (MODF)). An SPI interrupt can be generated if SPIE = 1 in the SPICR register. This bit is cleared by a software sequence (An ac- cess to the SPICSR register while MODF = 1 fol- lowed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bit 3 = Reserved, must be kept cleared. Bit 2 = SOD SPI Output Disable This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE = 1) 1: SPI output disabled Bit 1 = SSM SS Management This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section 11.4.3.2 Slave Select Management. 0: Hardware management (SS managed by exter- nal pin) 1: Software management (internal SS signal con- trolled by SSI bit. External SS pin free for gener- al-purpose I/O) Bit 0 = SSI SS Internal Mode This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the SS slave select signal when the SSM bit is set. 0: Slave selected 1: Slave deselected SPI DATA I/O REGISTER (SPIDR) Read/Write Reset Value: Undefined The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will init iate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value lo- cated in the buffer and not the content of the shift register (see Figure 50). SPIF WCOL OVR MODF - SOD SSM SSI D7 D6 D5 D4 D3 D2 D1 D0

Table 17. SPI Register Map and Reset Values

11.5.1 Introduction

age levels from up to seven different sources. through a Control/Status Register.

11.5.2 Main Features

The block diagram is shown in Figure 57.

11.5.3 Functional Description

11.5.3.1 Analog Power Supply

loaded or badly decoupled power supply lines. Figure 57. ADC Block Diagram

ST7L15, ST7L19 10-BIT A/D CONVERTER (ADC) (cont’d)

11.5.3.2 Digital A/D Conversion Result

The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V AIN) is greater than V DDA (high-level voltage reference) then the conversion result is FFh in the A DCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (low- level voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and AD- CDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section. R AIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this results in a loss of accuracy due to leak- age and sampling not being completed in the allot- ed time.

11.5.3.3 A/D Conversion

The analog input ports must be configured as in- put, no pull-up, no interrupt. Refer to the “I/O ports” chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the ADCCSR register: – Select the CH[2:0] bits to assign the analog channel to convert. ADC Conversion mode In the ADCCSR register: Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete: – The EOC bit is set by hardware. – The result is in the ADCDR registers. A read to the ADCDRH resets the EOC bit. To read the 10 bits, perform the following steps: 1. Poll the EOC bit 2. Read ADCDRL 3. Read ADCDRH. This clears EOC automati- cally. To read only 8 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRH. This clears EOC automati- cally.

11.5.4 Low-Power Modes

Note: The A/D converter may be disabled by re- setting the ADON bit. This feature allows reduced power consumption when no conversion is need- ed and between single shot conversions.

11.5.5 Interrupts

None. Mode Description WAIT No effect on A/D converter HALT A/D Converter disabled. After wake-up from HALT mode, the A/D converter requires a stabilization time tSTAB (see Electrical Characteristics) before accu- rate conversions can be performed.

ST7L15, ST7L19 10-BIT A/D CONVERTER (ADC) (cont’d)

11.5.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by soft- ware reading the ADCDRH register. 0: Conversion is not complete 1: Conversion complete Bit 6 = SPEED ADC clock selection This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit de- scription (ADCDRL register). Bit 5 = ADON A/D Converter on This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bits 4:3 = Reserved (must be kept cleared) Bits 2:0 = CH[2:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. *The number of channels is device dependent. Refer to the device pinout description. DATA REGISTER HIGH (ADCDRH) Read Only Reset Value: xxxx xxxx (xxh) Bits 7:0 = D[9:2] MSB of Analog Converted Value AMP CONTROL/DATA REGISTER LOW (AD- CDRL) Read/Write Reset Value: 0000 00xx (0xh) Bits 7:5 = Reserved (forced by hardware to 0) Bit 4 = Reserved (must be kept cleared) Bit 3 = SLOW Slow mode This bit is set and cleared by software. It is used together with the SPEED bit in the ADCCSR regis- ter to configure the ADC clock speed as shown on the table below. Note: Max f ADC allowed = 4 MHz (see section 13.11 on page 122) Bit 2 = Reserved (must be kept cleared) Bits 1:0 = D[1:0] LSB of Analog Converted Value EOC SPEED ADON 0 0 CH2 CH1 CH0 Channel Pin* CH2 CH1 CH0 A I N 0 000 A I N 1 001 A I N 2 010 A I N 3 011 A I N 4 100 A I N 5 101 A I N 6 110 D9 D8 D7 D6 D5 D4 D3 D2 000- S L O W - D 1 D 0 fADC SLOW SPEED fCPU/2 0 0 fCPU 01 fCPU/4 1 x

Table 18. ADC Register Map and Reset Values

12 INSTRUCTION SET

12.1 ST7 ADDRESSING MODES

Table 19. ST7 Addressing Mode Overview

1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.

ST7L15, ST7L19 ST7 ADDRESSING MODES (cont’d)

12.1.1 Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation.

12.1.2 Immediate

Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value.

12.1.3 Direct

In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub- modes: Direct (Short) The address is a byte, thus requires only 1 byte af- ter the opcode, but only allows 00 - FF addressing space. Direct (Long) The address is a word, thus allowing 64 Kbyte ad- dressing space, but requires 2 bytes after the op- code.

12.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three submodes: Indexed (No Offset) There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE addressing space. Indexed (Long) The offset is a word, thus allowing 64 Kbyte ad- dressing space and requires 2 bytes after the op- code.

12.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (point- er). The pointer address follows the opcode. The indi- rect addressing mode consists of two submodes: Indirect (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Subroutine Return IRET Interrupt Subroutine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations

12.1.6 Indirect Indexed (Short, Long)

er address follows the opcode. and requires 1 byte after the opcode. and requires 1 byte after the opcode. Table 20. Instructions Supporting Direct,

12.1.7 Relative Mode (Direct, Indirect)

register value by adding an 8-bit signed offset to it. The offset follows the opcode.

ST7L15, ST7L19

12.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Using a prebyte The instructions are described with 1 to 4 bytes. In order to extend the number of available op- codes for an 8-bit CPU (256 opcodes), three differ- ent prebyte opcodes are defined. These prebytes modify the meaning of the instruction they pre- cede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, di- rect bit or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruc- tion using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

12.2.1 Illegal Opcode Reset

In order to provide enhanced robustness to the de- vice against unexpected behavior, a system of ille- gal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, com- bined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. Note: A valid prebyte associated with a valid op- code forming an unauthorized combination does not generate a reset. Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF

ST7L15, ST7L19 INSTRUCTION GROUPS (cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >

ST7L15, ST7L19 INSTRUCTION GROUPS (cont’d) Mnemo Description Function/Example Dst Src H I N Z C JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2's compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z

13 ELECTRICAL CHARACTERISTICS

13.1 PARAMETER CONDITIONS

13.1.1 Minimum and Maximum Values

times the standard deviation (mean±3Σ).

13.1.2 Typical Values

given only as design guidelines and are not tested.

13.1.3 Typical Curves

given only as design guidelines and are not tested.

13.1.4 Loading Capacitor

measurement are shown in Figure 58. Figure 58. Pin Loading Conditions

13.1.5 Pin Input Voltage

vice is described in Figure 59. Figure 59. Pin Input Voltage

ST7L15, ST7L19 ELECTRICAL CHARACTERISTICS (cont’d)

13.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

13.2.1 Voltage Characteristics

13.2.2 Current Characteristics

13.2.3 Thermal Characteristics

Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an uni ntentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection must be made through a pull-up or pull-down resistor (typical: 4.7k Ω for RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if V IN maximum is respected. If V IN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN >V DD while a negative injection is induced by VIN <V SS. 3. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. No negative current injection allowed on PB0 pin. 6. When several inputs are submitted to a current injection, the maximum ΣI INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣIINJ(PIN) maxi- mum current injection on four I/O port pins of the device. Symbol Ratings Maximum value Unit VDD - VSS Supply voltage 7.0 VVIN Input voltage on any pin1) 2) VSS - 0.3 to VDD +0 . 3 VESD(HBM) Electrostatic discharge voltage (Human Body Model) See section 13.7.3 on page 112VESD(MM) Electrostatic discharge voltage (Machine Model) Symbol Ratings Maximum value Unit IVDD Total current into VDD power lines (source)3) 75 mA IVSS Total current out of VSS ground lines (sink)3) 150 IIO Output current sunk by any standard I/O and control pin 20 Output current sunk by any high sink I/O pin 40 Output current source by any I/Os and control pin - 25 IINJ(PIN) 2)4) Injected current on ISPSEL pin ± 5 Injected current on RESET pin ± 5 Injected current on OSC1 and OSC2 pins ± 5 Injected current on PB0 pin 5) +5 Injected current on any other pin6) ± 5 ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins)6) ± 20 Symbol Ratings Value Unit TSTG Storage temperature range -65 to +150 °C TJ Maximum junction temperature (see Table 23, “Thermal Characteristics,” on page 124)

13.3 OPERATING CONDITIONS

13.3.1 General Operating Conditions

TA = -40 to +125°C, unless otherwise specified. Figure 60. fCLKIN Maximum Operating Frequency vs VDD Supply Voltage

105 FOR PLL OPER-

The RC oscillator and PLL characteristics are temperature-dependent.

1. If the RC oscillator clock is sele cted, to improve clock stability and frequency accuracy, it is recommended to place a

decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.

1. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 21.
2. Minimum value is obtained for hot temperature and max value is obtained for cold temperature.
3. Data based on characterization results, not tested in production
4. Measurement made with RC calibrated at 1 MHz.
5. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy.
6. After the LOCKED bit is set ACCPLL is maximum 10% until tSTAB has elapsed. See Figure 11 on page 22.

Figure 61. Typical Accuracy with RCCR = RCCR0 vs VDD = 4.5 to 5.5V and Temperature

Figure 62. fRC vs VDD and Temperature for Calibrated RCCR0

1. Data based on characterization results, not tested in production.
2. If the RC oscillator clock is sele cted, to improve clock stability and frequency accuracy, it is recommended to place a

decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device.

1. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 21.
2. Minimum value is obtained for hot temperature and maximum value is obtained for cold temperature.
3. Measurement made with RC calibrated at 1 MHz.
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy.
5. After the LOCKED bit is set, ACCPLL is maximum 10% until tSTAB has elapsed. See Figure 11 on page 22.

ST7L15, ST7L19 OPERATING CONDITONS (cont’d)

13.3.2 Operating Conditions with Low Voltage Detector (LVD)

TA = -40 to +125°C, unless otherwise specified. Notes: 1. LVD functionality guaranteed only within the VDD operating range specified in section 13.3.1 on page 100. 2. Not tested in production. 3. Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU. 4. Based on design simulation. 5. Use of LVD with capacitive power supply: With this type of power supply, if power cuts occur in the application, it is rec- ommended to pull V DD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 95 on page 119 and note 4.

13.3.3 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte). Notes: 1. x4 PLL option only applicable on Flash devices. Symbol Parameter Conditions 1) Min Typ Max Unit Vhys LVD voltage threshold hysteresis V IT+(LVD)-VIT-(LVD) 200 mV VtPOR VDD rise time rate 3)5) 0.022) 1002) ms/V tg(VDD) Filtered glitch delay on VDD Not detected by the LVD 150 4) ns IDD(LVD) LVD current consumption 200 µA Symbol Parameter Conditions Min Typ Max Unit VDD(RC) Internal RC oscillator operating voltage Refer to operating range of VDD with TA, section 13.3.1 on page 100 3.0 5.5 VVDD(x4PLL) x4 PLL operating voltage1) 3.0 3.6 VDD(x8PLL) x8 PLL operating voltage 3.6 5.5 tSTARTUP PLL Start-up time 60 PLL input clock (fPLL) cycles

13.4 SUPPLY CURRENT CHARACTERISTICS

13.4.1 Supply Current

A = -40 to +125°C, unless otherwise specified.

1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals

in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)

driven by external square wave, LVD disabled.

1. SLOW mode selected with f CPU based on fOSC divided by 32. All I/O pins in i nput mode with a static value at V DD or

VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. SLOW-WAIT mode selected with f CPU based on f OSC divided by 32. All I/O pins in input mode with a static value at

VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,

tested in production at VDD max and fCPU max.

1. All I/O pins in input mode with a static value at V DD or VSS (no load). Data tested in production at VDD max. and fCPU
2. This consumption refers to the Halt period only and not the associated run period which is software dependent.

Figure 67. Typical IDD in RUN vs fCPU Figure 68. Typical IDD in RUN at fCPU = 8 MHz

ST7L15, ST7L19 SUPPLY CURRENT CHARACTERISTICS (cont’d)

13.4.2 On-chip Peripherals

Notes: 1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer running in PWM mode at fCPU =8 M H z . 2. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica- tion (data sent equal to 55h). 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.

13.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC and TA.

13.5.1 General Timings

Notes: 1. Guaranteed by Design. Not tested in production. 2. Data based on typical application software. 3. Time measured between interrupt ev ent and interrupt vector fetch. Dt c(INST) is the number of t CPU cycles needed to finish the current instruction execution.

13.5.2 Auto Wake-Up from Halt Oscillator (AWU)1)

Notes: 1. Guaranteed by Design. Not tested in production. Symbol Parameter Conditions Typ Unit IDD(AT) 12-bit Auto-Reload Timer supply current1) fCPU =4 M H z V DD = 3.3V 150 µA fCPU =8 M H z V DD = 5V 1000 IDD(SPI) SPI supply current2) fCPU =4 M H z V DD = 3.3V 50 fCPU =8 M H z V DD = 5V 200 IDD(ADC) ADC supply current when converting3) fADC =4 M H z VDD = 3.3V 250 VDD = 5V 1100 Symbol Parameter 1) Conditions Min Typ 2) Max Unit tc(INST) Instruction cycle time fCPU =8 M H z 23 1 2 t CPU 250 375 1500 ns tv(IT) Interrupt reaction time3) tv(IT) = ∆tc(INST) + 10 10 22 t CPU 1.25 2.75 µs Symbol Parameter Conditions Min Typ Max Unit fAWU AWU oscillator frequency 50 125 250 kHz tRCSRT AWU oscillator start-up time 50 µs

13.5.3 Crystal and Ceramic Resonator Oscillators

1. When PLL is used, please refer to the PLL characteristics chapter and to “SUPPLY, RESET AND CLOCK MANAGE-

MENT” on page 21 chapter (fCrOSC min. is 8 MHz with PLL).

1. Resonator characteristics given by the ceramic resonator manufacturer. Fo r more information on these resonators,
2. SMD = [-R0: Plastic tape package (∅ =180mm)]
3. () means load capacitor built in resonator

Figure 74. Typical Application with a Crystal or Ceramic Resonator

2 SMD CSTCC2M00G56Z-R0 (47) (47) 0

8 SMD CSTCE8M00G52Z-R0 (10) (10) 0

12 SMD CSTCE12M0G52Z-R0 (10) (10) 0

ST7L15, ST7L19 ELECTRICAL CHARACTERISTICS (cont’d)

13.6 MEMORY CHARACTERISTICS

13.6.1 RAM and Hardware Registers

TA = -40 to +125°C, unless otherwise specified.

13.6.2 Flash Program Memory

TA = -40 to +85°C, unless otherwise specified

13.6.3 EEPROM Data Memory

TA = -40 to +125°C, unless otherwise specified Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg- isters (only in HALT mode). Guaranteed by construction, not tested in production. 2. Up to 32 bytes can be programmed at a time. 3. The data retention time increases when the TA decreases. 4. Data based on reliability test results and monitored in production. 5. Guaranteed by Design. Not tested in production. Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode1) HALT mode (or RESET) 1.6 V Symbol Parameter Conditions Min Typ Max Unit VDD Operating voltage for Flash write/erase Refer to operating range of VDD with TA, section 13.3.1 on page 100 3.0 5.5 V tprog Programming time for 1~32 bytes2) TA =− 40 to +85°C 5 10 ms Programming time for 1.5 Kbytes T A = 25°C 0.24 0.48 s tRET 4) Data retention T A = 55°C3) 20 years NRW Write erase cycles TPROG = 25°C 1K cyclesTPROG = 85°C 300 IDD Supply current Read / Write / Erase modes fCPU = 8 MHz, VDD = 5.5V 2.65) mA No Read/No Write Mode 100 µAPower down mode / HALT 0 0.1 Symbol Parameter Conditions Min Typ Max Unit VDD Operating voltage for EEPROM write/ erase Refer to operating range of VDD with TA, section 13.3.1 on page 100 3.0 5.5 V tprog Programming time for 1~32 bytes T A =− 40 to +125°C 5 10 ms tRET Data retention with 1k cycling (TPROG = −40 to +125°C TA = 55°C3) yearsData retention with 10k cycling (TPROG = −40 to +125°C) 10 Data retention with 100k cycling (TPROG = −40 to +125°C) 1

ST7L15, ST7L19 ELECTRICAL CHARACTERISTICS (cont’d)

13.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba- sis during product characterization.

13.7.1 Functional EMS (Electro Magnetic

Susceptibility) Based on a simple running application on the product (toggling two LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ■ ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. This test conforms with the IEC 1000-4-2 standard. ■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4- 4 standard. A device reset allows normal operations to resume. The test results are given in the table be- low based on the EMS levels and classes defined in application note AN1709.

13.7.1.1 Designing Hardened Software to Avoid

EMC characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore, it is recommended that EMC software optimization and prequalification tests are made relative to the EMC level requested for the user's application. Software recommendations: The software flowchart must include the manage- ment of runaway conditions such as: – Corrupted program counter – Unexpected reset – Critical data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the RE- SET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be ap- plied directly on the device, over the range of specification values. Wh en unexpected behavior is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note AN1015).

13.7.2 Electro Magnetic Interference (EMI)

Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin. Notes: 1. Data based on characterization results, not tested in production. Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a function- al disturbance VDD = 5V, TA = 25°C, fOSC = 8M H z , conforms to IEC 1000-4-2 2B VFFTB Fast transient voltage burst limits to be applied through 100pF on VDD and VDD pins to induce a functional disturbance VDD = 5V, TA = 25°C, fOSC = 8M H z , conforms to IEC 1000-4-4 3B Symbol Parameter Conditions Monitored Frequency Band Max vs [fOSC/fCPU]U n i t 8/4 MHz 16/8 MHz SEMI Peak level1) VDD = 5V, TA = 25°C, SO20 package, conforming to SAE J 1752/3

0.1 MHz to 30 MHz 15 20

dBµV30 MHz to 130 MHz 17 21

130 MHz to 1 GHz 12 15

ST7L15, ST7L19 EMC CHARACTERISTICS (cont’d)

13.7.3 Absolute Maximum Ratings (Electrical

Sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer to application note AN1181.

13.7.3.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test con- forms to the JESD22-A114A/A115A standard. Absolute Maximum Ratings Notes: 1. Data based on characterization results, not tested in production.

13.7.3.2 Static and Dynamic Latch-Up (LU)

Three complementary static tests are required on six parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test co nforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to application note AN1181. Electrical Sensitivities Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, which means when a device belongs to Class A it exceeds the JEDEC standard. Class B strictly covers all the JEDEC criteria (international standard). Symbol Ratings Condi tions Maximum value 1) Unit VESD(HBM) Electro-static discharge voltage (Human Body Model) TA = 25°C 8000 VVESD(MM) Electro-static discharge voltage (Machine Model) 400 VESD(CDM) Electro-static discharge voltage (Charge Device Model) 1000 Symbol Parameter Conditions Class 1) LU Static latch-up class TA = 25°C TA = 125°C A DLU Dynamic latch-up class VDD = 5.5V, fOSC = 4 MHz, TA = 25°C A

13.8 I/O PORT PIN CHARACTERISTICS

13.8.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA, unless otherwise specified.

1. Data based on validation/design results.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: Using the output mode of the I/O for
3. The R PU pull-up equivalent resistor is based on a resistive transistor (corresponding I PU current characteristics de-

scribed in Figure 76 on page 115).

1. To generate an external interrupt, a minimum pulse width must be applied on an I/O port pin configured as an external

Figure 75. Two Typical Applications with Unused I/O Pin (external pull-up of 10k mandatory in This is to avoid entering ICC mode unexpectedly during a reset. noisy environment).

ST7L15, ST7L19 I/O PORT PIN CHARACTERISTICS (cont’d)

13.8.2 Output Driving Current

Subject to general operating conditions for V DD, fCPU and TA (-40 to +125°C), unless otherwise specified. Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 99 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in section 13.2.2 on page 99 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Not tested in production, based on characterization results. Symbol Parameter Conditions Min Typ Max Unit VOL Output low level voltage for a standard I/O pin when eight pins are sunk at same time (see Figure 77) VDD =5 V IIO =+ 5 m A 1 . 0 V IIO =+ 2 m A 0 . 4 Output low level voltage for a high sink I/O pin when four pins are sunk at same time (see Figure 80) I IO = +20mA 1.3 IIO =+ 8 m A 0 . 7 5 VOH Output high level voltage for an I/O pin when four pins are sourced at same time (see Figure 86) IIO =- 5 m A V DD -1 . 5 IIO =- 2 m A V DD -0 . 8 VOL 1)3) Output low level voltage for a standard I/O pin when eight pins are sunk at same time (see Figure 76) V DD =3 . 3 V IIO =+ 2 m A , TA ≤ +85°C 0.5 Output low level voltage for a high sink I/O pin when four pins are sunk at same time IIO = +8mA, TA ≤ +85°C VOH 2)3) Output high level voltage for an I/O pin when four pins are sourced at same time (Figure 85) I IO =- 2 m A , TA ≤ +85°C VDD -0 . 8

ST7L15, ST7L19 ELECTRICAL CHARACTERISTICS (cont’d)

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

TA = -40 to +125°C, unless otherwise specified. Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 99 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistiv e transistor. Specified for voltages on RESET pin between VILmax and VDD. 4. To guarantee the reset of the device, a minimum pulse must be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. Symbol Parameter Conditions Min Typ Max Unit VIL 1) Input low-level voltage V ss - 0.3 0.3xVDD V VIH 1) Input high-level voltage 0.7xV DD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis1) 2 VOL 1) Output low-level voltage2) VDD =5 V IIO = +5mA, IIO = +2mA, RON Pull-up equivalent resistor1)3) VDD = 5V 20 40 80 kΩVDD =3 . 3 V1) 40 70 120 tw(RSTL)ou t Generated reset pulse duration Internal reset sources 30 µs th(RSTL)in External reset pulse hold time4) 20 tg(RSTL)in Filtered glitch duration 200 ns

13.10 COMMUNICATION INTERFACE CHARACTERISTICS

13.10.1 SPI - Serial Peripheral Interface

fOSC, and TA unless otherwise specified. Figure 96. SPI Slave Timing Diagram with CPHA = 03)

1. Data based on design simulation, not tested in production.
2. When no communication is on-going, the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD.
2. Depends on fCPU. For example, if fCPU = 8 MHz, then tCPU =1/f CPU = 125ns and tsu(SS) = 550ns.

Subject to general operating conditions for VDD, fOSC and TA unless otherwise specified. Figure 99. Typical Application with ADC

1. Unless otherwise specified, typical data is based on T A = 25°C and V DD -V SS = 5V. They are given only as design

guidelines and are not tested.

1. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
2. Any added external serial resistor downgrades the ADC accuracy (especially for resistance greater than 10kΩ). Data

based on characterization results, not tested in production.

1. The stabilization time of the AD c onverter is masked by the first t LOAD. The first conversion after the enable is then

Table 21. ADC Accuracy with 3V < VDD < 3.6V Table 22. ADC Accuracy with 4.5V< VDD < 5.5V

1. Data based on characterization results over the whole temperature range, monitored in production.
2. ADC accuracy vs negative injection current: Injecting negative current on any of the analog input pins may reduce the

accuracy of the conversion being performed on another analog input.

1. Data based on characterization results, monitored in pr oduction to guarantee 99.73% within ± max value from -40°C

to +125°C (± 3σ distribution limits). Figure 100. ADC Accuracy Characteristics between the actual and the ideal transfer curves. al transition and the first ideal one. transition and the last actual one. tion between actual steps and the ideal one.

14 PACKAGE CHARACTERISTICS

offers these devices in ECOPACK® packages. fications are available at www.st.com.

14.1 PACKAGE MECHANICAL DATA

Figure 101. 20-Pin Plastic Small Outline Package, 300-mil Width Table 23. Thermal Characteristics

1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.

14.2 SOLDERING INFORMATION

Table 24. Soldering Compatibility (wave and reflow soldering process)

ST7L15, ST7L19

15 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro- grammable versions (Flash) as well as in factory coded versions (ROM). ST7L1x devices are ROM versions. ST7PL1x devices are Factory Advanced Service Technique ROM (FASTROM) versions: They are factory programmed Flash devices. ST7FL1x Flash devices are shipped to customers with a default program memory content (FFh), while ROM/FASTROM factory coded parts contain the code supplied by the customer. This implies that Flash devices have to be configured by the customer using the Option Bytes while the ROM/ FASTROM devices are factory-configured.

15.1 OPTION BYTES

The option bytes have no address in the memory map and are accessed only in programming mode (for example using a standard ST7 programming tool). Difference in option byte configuration be- tween Flash and ROM devices are presented in the following table and are described in Section 15.1.1 Flash Option Bytes and Section 15.1.2 ROM Option Bytes. OPTION BYTE 0 OPTION BYTE 1 7654321076543210 Flash Name Reserved CLKSEL SEC SEC FMP R FMP W PLL x4x8 PLL OFF Res OSC LVD 1:0 WDG SW WDGHALT Default value 0111010011101111 ROM Name AWUCK OSCRANGE 2:0 Reserved ROP ROP _D Res PLL OFF Res OSC LVD 1:0 WDG SW WDGHALT Default value 1111110011001111

ST7L15, ST7L19 OPTION BYTES (cont’d)

15.1.1 Flash Option Bytes

The 2 option bytes allow the hardware configura- tion of the microcontroller to be selected. OPTION BYTE 0 OPT7 = Reserved (must be set to 0) OPT6 = Reserved (must be set to 1) OPT5:4 = CLKSEL Clock Source Selection When the internal RC osc illator is not selected (Option OSC = 1), these option bits select the clock source: Re sonator oscillator or external clock. Note: When the internal RC oscillator is selected, the CLKSEL option bits must be kept at their de- fault value in order to select the 256 clock cycle delay (see Section 7.5). OPT 3:2 = SEC[1:0] Sector 0 size definition These option bits indicate the size of sector 0 ac- cording to the following table. OPT1 = FMP_R Readout protection Readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first and the device can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and section 4.5 on page 12 for more de- tails. 0: Readout protection off 1: Readout protection on OPT 0 = FMP_W Flash write protection This option indicates if the Flash program memory is write protected. Warning: When this option is selected, the pro- gram memory (and the option bit itself) can never be erased or programmed again. 0: Write protection off 1: Write protection on OPTION BYTE 1 OPT7 = PLLx4x8 PLL Factor selection 0: PLLx4 1: PLLx8 OPT 6 = PLLOFF PLL Disable This option bit enables or disables the PLL. 0: PLL enabled 1: PLL disabled (bypassed) OPT 5 = Reserved (must be set to 1) OPT 4 = OSC RC Oscillator Selection This option bit enables to select the internal RC oscillator. 0: RC oscillator on 1: RC oscillator off Note: If the RC oscillator is selected, then to im- prove clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the V DD and VSS pins as close as possible to the ST7 device. OPT 3:2 = LVD[1:0] Low Voltage Selection These option bits enable the voltage detection block (LVD) with a selected threshold to the LVD. Clock Source Port C CLKSEL Resonator Ext. Osc Enabled/ Port C Disabled 00 External clock source: CLKIN on PB4 Ext. Osc Disabled/ Port C Enabled on PC0 1 1 Reserved 1 0 Sector 0 Size SEC1 SEC0

0.5 Kbyte

Table 25. List of Valid Option Combinations

ST7L15, ST7L19 OPTION BYTES (cont’d)

15.1.2 ROM Option Bytes

The 2 option bytes allow the hardware configura- tion of the microcontroller to be selected. OPTION BYTE 0 OPT7 = AWUCK Auto Wake Up Clock Selection 0: 32 kHz oscillator (VLP) selected as AWU clock 1: AWU RC oscillator selected as AWU clock. Note: If this bit is reset, internal RC oscillator must be selected (Option OSC = 0). OPT6:4 = OSCRANGE[2:0] Oscillator Range When the internal RC osc illator is not selected (Option OSC = 1), these option bits select the range of the resonator oscillator current source or the external clock source. Note: OSCRANGE[2:0] has no effect when AWUCK option is set to 0. In this case, the VLP os- cillator range is automatically selected as AWU clock. OPT 3:2 = Reserved (must be set to 1:1) OPT1 = ROP_R Readout protection for ROM This option is for read protection of ROM 0: Readout protection off 1: Readout protection on OPT 0 = ROP_D Readout protection for Data EEPROM This option is for read protection of EEPROM memory. 0: Readout protection off 1: Readout protection on OPTION BYTE 1 OPT 7 = Reserved (must be set to 1) OPT 6 = PLLOFF PLL Disable This option bit enables or disables the PLL. 0: PLL enabled 1: PLL disabled (bypassed) OPT 5 = Reserved (must be set to 0) OPT 4 = OSC RC Oscillator Selection This option bit is used to select the internal RC os- cillator. 0: RC oscillator on 1: RC oscillator off Note: If the RC oscillator is selected, then to im- prove clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the V DD and VSS pins as close as possible to the ST7 device. OPT 3:2 = LVD[1:0] Low Voltage Selection These option bits enable the voltage detection block (LVD) with a selected threshold to the LVD. OPT 1 = WDGSW Hardware or Software Watch- dog 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) OPT 0 = WDG HALT Watchdog Reset on Halt This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No reset generation when entering HALT mode 1: Reset generation when entering HALT mode OSCRANGE 210 Typ. frequency range with resonator LP 1~2 MHz 0 0 0 MP 2~4 MHz 0 0 1 MS 4~8 MHz 0 1 0 HS 8~16 MHz 0 1 1 VLP 32.768~ kHz 1 0 0 External clock on OSC1 1 0 1 Reserved 1 1 0 Configuration VD1 VD0 LVD Off 1 1 LVD High Threshold 0

15.2 DEVICE ORDERING INFORMATION

Figure 102. Flash Commercial Product Code Structure Table 26. Flash User Programmable Device Types

Figure 103. FASTROM Commercial Product Code Structure Table 27. FASTROM Factory Coded Device Types

Figure 104. ROM Commercial Product Code Structure Table 28. ROM Factory Coded Device Types

ST7L15, ST7L19 ST7L1 FASTROM & ROM MICROCONTROLLER OPTION LIST (Last update: December 2006) *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): Conditioning (check only one option):[ ] Tape & Reel [ ] Tube Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ " (8 char. max) Authorized characters are letters, digits, '.', '-', '/' and spaces only. Temperature range: [ ] A (-40°C to +85°C) [ ] C (-40°C to +125°C°) PLL: [ ] Disabled [ ] Enabled LVD Reset: [ ] Disabled [ ] Enabled (highest voltage threshold) Watchdog Selection: [ ] Software Activation [ ] Hardware Activation Watchdog Reset on Halt: [ ] Disabled [ ] Enabled Flash Devices only Clock Source Selection: [ ] Resonator [ ] External clock [ ] on PB4 [ ] on OSC1 [ ] Internal RC oscillator Sector 0 size: [ ] 0.5 Kbyte [ ] 1 Kbyte [ ] 2 Kbytes [ ] 4 Kbytes Readout Protection: [ ] Disabled [ ] Enabled Flash Write Protection: [ ] Disabled [ ] Enabled ROM Devices only Clock Source Selection: [ ] Resonator [ ] VLP: Very Low power resonator (32 to 100 kHz) [ ] LP: Low power resonator (1 to 2 MHz) [ ] MP: Medium power resonator (2 to 4 MHz) [ ] MS: Medium speed resonator (4 to 8 MHz) [ ] HS: High speed resonator (8 to 16 MHz) [ ] External clock [ ] on PB4 [ ] on OSC1 [ ] Internal RC oscillator AWUCK Selection [ ] 32 kHz oscillator [ ] AWU RC oscillator Readout Protection for ROM: [ ] Disabled [ ] Enabled Readout Protection for E2data: [ ] Disabled [ ] Enabled Comments: Signature: Important note: Not all configurations are available. See section 15.1 on page 126 for authorized option byte combinations. FASTROM / 4 Kbytes / SO20 ROM / 4 Kbytes / SO20 [ ] ST7PL15F1M [ ] ST7PL19F1M [ ] ST7L15F1M [ ] ST7L19F1M

15.3 DEVELOPMENT TOOLS

program your microcontrollers.

15.3.1 Evaluation Tools and Starter Kits

serve as references for your application design.

15.3.2 Development and Debugging Tools

grated programming interface.

15.3.3 Programming Tools

15.3.4 Order Codes for Development and

Table 29. ST7L1 Development and Programming Tools

1. Available from ST or from Raisonance, www.raisonance.com
2. Add suffix /EU, /UK or /US for the power supply for your region
3. Includes connection kit for DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection guide
4. Parallel port connection to PC

ST7L15, ST7L19

15.4 ST7 APPLICATION NOTES

All relevant ST7 application notes can be found on www.st.com.

16 REVISION HISTORY

Table 30. Revision History