ST7F10BY1M3

ST7LITE1XB_08 STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 159

Technical content

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY , DATA EEPROM, ADC, 5 TIMERS, SPI ■ Memories – up to 4 Kbytes single voltage extended Flash (XFlash) Program memory with read-out pro- tection, In-Circuit Programming and In-Appli- cation programming (ICP and IAP). 10K write/ erase cycles guaranteed, data retention: 20 years at 55°C. – 256 bytes RAM – 128 bytes data EEPROM with read-out pro- tection. 300K write/erase cycles guaranteed, data retention: 20 years at 55°C. ■ Clock, Reset and Supply Management – Enhanced reset system – Enhanced low voltage supervisor (LVD) for main supply and an auxiliary voltage detector (AVD) with interrupt ca pability for implement- ing safe power-down procedures – Clock sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ ceramic resonator or external clock – Internal 32-MHz input clock for Auto-reload timer – Optional x4 or x8 PLL for 4 or 8 MHz internal clock – Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow ■ I/O Ports – Up to 17 multifunctional bidirectional I/O lines –7 high sink outputs ■ 5 Timers – Configurable watchdog timer – Two 8-bit Lite Timers with prescaler, 1 realtime base and 1 input capture – Two 12-bit Auto-reload Timers with 4 PWM outputs, 1 input capture, 4 output compare and one pulse functions ■ Communication Interface – SPI synchronous serial interface ■ Interrupt Management – 12 interrupt vectors plus TRAP and RESET – 15 external interrupt lines (on 4 vectors) ■ Analog Comparator ■ A/D Converter – 7 input channels – Fixed gain Op-amp – 13-bit precision for 0 to 430 mV (@ 5V V DD) – 10-bit precision for 430 mV to 5V (@ 5V VDD) ■ Instruction Set – 8-bit data manipulation – 63 basic instructions with illegal opcode de- tection – 17 main addressing modes – 8 x 8 unsigned multiply instructions ■ Development Tools – Full hardware/software development package – DM (Debug Module) Device Summary DIP20 DIP16 SO16 300” QFN20 SO20 Features ST7LITE10B ST7LITE15B ST7LITE19B Program memory - bytes 2K/4K RAM (stack) - bytes 256 (128) Data EEPROM - bytes - - 128 Peripherals Lite Timer with Wdg, Autoreload Timer, SPI, 10-bit ADC with Op-Amp Lite Timer with Wdg, Autoreload Timer with 32-MHz input clock, SPI, 10-bit ADC with Op-Amp, Analog Comparator Operating Supply 2.7V to 5.5V CPU Frequency Up to 8Mhz(w/ ext OSC at 16MHz) Up to 8Mhz (w/ ext OSC at 16MHz or int 1MHz RC 1%, PLLx8/4MHz) Operating Temperature -40°C to +85°C / -40°C to +125°C

13.14 CURRENT BIAS CHARACTERISTICS (FOR COMPARATOR AND INTERNAL VOLTAGE

REFERENCE) 143

1 INTRODUCTION

Application Programming (IAP) capability. Figure 1. General Block Diagram

2 PIN DESCRIPTION

Figure 2. 20-Pin SO and DIP Package Pinout Figure 3. 20-Pin QFN Package Pinout

16 PA0 (HS)/LTIC

Figure 4. 16-Pin SO and DIP Package Pinout

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 1. Device Pin Description

424 PB0/COMPIN+/

jection allowed on this pin.

868 PB4/AIN4/CLKIN/

Notes: 1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground. 2. When the pin is configured as analog input, positive and negative current injections are not allowed. 3. PCOR not implemented but p-transistor always active in output mode (refer to Figure 32 on page 50). 12 10 10 PA6 /MCO/ ICCCLK/BREAK I/O C T X ei1 XX Port A6 Main Clock Output or In Circuit Communication Clock or External BREAK Caution: During normal operation this pin must be pulled- up, inter- nally or externally (external pull-up of 10k mandatory in noisy environ- ment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in input pull-up 13 11 11 PA5 /ICCDATA/ ATPWM3 I/O C T HS X ei1 XX Port A5 In Circuit Communication Data or Auto-Reload Timer PWM3 14 12 12 PA4/ATPWM2 I/O C T HS X XX Port A4 Auto-Reload Timer PWM2 15 13 - PA3/ATPWM1 I/O C T HS X ei0 XX Port A3 Auto-Reload Timer PWM1 16 14 13 PA2/ATPWM0 I/O C T HS X XX Port A2 Auto-Reload Timer PWM0 17 15 - PA1/ATIC I/O C T HS X XX Port A1 Auto-Reload Timer Input Capture 18 16 14 PA0/LTIC I/O C T HS X XX Port A0 Lite Timer Input Capture 19 17 15 OSC2/PC1 I/O X X Port C13) Resonator oscillator inverter out- put 20 18 16 OSC1/CLKIN/PC0 I/O X X Port C03) Resonator oscillator inverter input or External clock input Pin No. Pin Name Type Level Port / Control Main Function (after reset) Alternate Function SO20/DPI20 QFN20 SO16/DIP16 Input Output Input Output float wpu int ana OD PP

3 REGISTER & MEMORY MAP

dressing 64K bytes of memories and I/O registers. 128 bytes for the stack from 180h to 1FFh. are located in Sector 0 (F000h-FFFFh). Figure 5. Memory Map

128 Bytes Stack

1 Kbyte

3 Kbytes

Table 2. Hardware Register Map

Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the Debug Module registers, see ICC protocol reference manual. 0002Fh FLASH FCSR Flash Control/Status Register 00h R/W 00030h EEPROM EECSR Data EEPROM Control/Status Register 00h R/W 0031h 0032h 0033h SPI SPIDR SPICR SPICSR SPI Data I/O Register SPI Control Register SPI Control Status Register xxh 0xh 00h R/W R/W R/W 0034h 0035h 0036h ADC ADCCSR ADCDRH ADCDRL A/D Control Status Register A/D Data Register High A/D Amplifier Control/Data Low Register 00h xxh 0xh R/W Read Only R/W 0037h ITC EICR External Interrupt Control Register 00h R/W 0038h MCC MCCSR Main Clock Contro l/Status Register 00h R/W 0039h 003Ah Clock and Reset RCCR SICSR RC oscillator Control Register System Integrity Control/Status Register FFh 0110 0xx0b R/W R/W 003Bh PLL clock select PLLTST PLL test register 00h R/W 003Ch ITC EISR External Interrupt Selection Register 0Ch R/W 003Dh to 0048h Reserved area (12 bytes) 0049h 004Ah AWU AWUPR AWUCSR AWU Prescaler Register AWU Control/Status Register FFh 00h R/W R/W 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h DM DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DMCR2 DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low DM Control Register 2 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W 0052h to 007Fh Reserved area (46 bytes) Address Block Register Label Register Name Reset Status Remarks

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Program- ming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ ICP (In-Circuit Programming) ■ IAP (In-Application Programming) ■ ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM ■ Sector 0 size configurable by option byte ■ Read-out and write protection

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different ways: – Insertion in a programming tool. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be pro- grammed or erased. – In-Circuit Programming. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board. – In-Application Programming. In this mode, sector 1 and data EEPROM (if present) can be programmed or erased without removing the device from the application board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Commu- nication) which allows an ST7 plugged on a print- ed circuit board (PCB) to communicate with an ex- ternal programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communi- cations). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory contain- ing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. – Download ICP Driver code in RAM from the ICCDATA pin – Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory ar- eas except Sector 0, which is write/erase protect- ed to allow recovery in case errors occur during the programming operation.

4.4 ICC interface

1. If the ICCCLK or ICCDATA pins are only used
2. During the ICP session, the programming tool

high level (push pull output or pull-up resistor<1K). sistor>1K, no additional components are needed.

1. The use of pin 7 of the ICC connector depends
2. Pin 9 has to be connected to the OSC1 pin of
3. In 38-pulse ICC mode, the internal RC oscillator

pulse ICC mode entry, clock provided by the tool). Figure 6. Typical ICC Interface

FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection

There are two different types of memory protec- tion: Read Out Protection and Write/Erase Protec- tion which can be applied individually.

4.5.1 Read out Protection

Readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data E 2 memory are protected. In flash devices, this protection is removed by re- programming the option. In this case, both pro- gram and data E 2 memory are automatically erased and the device can be reprogrammed. Read-out protection selection depends on the de- vice type: – In Flash devices it is enabled and removed through the FMP_R bit in the option byte. – In ROM devices it is enabled by mask option specified in the Option List.

4.5.2 Flash Write/Erase Protection

Write/erase protection, when set, makes it impos- sible to both overwrite and erase program memo- ry. It does not apply to E 2 data. Its purpose is to provide advanced security to applications and pre- vent any change being made to the memory con- tent. Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6 Related Documentation

For details on Flash programming and ICC proto- col, refer to the ST7 Flash Programming Refer- ence Manual and to the ST7 ICC Protocol Refer- ence Manual

4.7 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing op- erations. When an EPB or anothe r programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

00000 O P T L A T P G M

5 DATA EEPROM

5.1 INTRODUCTION

basic access protocol described in this chapter.

5.2 MAIN FEATURES

Figure 7. EEPROM Block Diagram

0 E2LAT00 0 0 0 E2PGM

5.3 MEMORY ACCESS

set by software (the E2PGM bit remains cleared). Significant Bits of the address can change. LAT bits are cleared simultaneously. It is not possible to read the latched data. This note is illustrated by the Figure 10. Figure 8. Data EEPROM Programming Flowchart

Figure 9. Data E2PROM Write Operation

5.4 POWER SAVING MODES

function in progress, and data may be corrupted.

5.5 ACCESS ERROR HANDLING

data bus will not be driven. data on the bus will not be latched.

5.6 Data EEPROM Read-out Protection

tion bit (see option byte section). against read-out (including a re-write protection). are protected using the same option bit. Figure 10. Data EEPROM Programming Cycle

5.7 REGISTER DESCRIPTION

Bits 7:2 = Reserved, forced by hardware to 0. Table 3. DATA EEPROM Register Map and Reset Values

000000 E 2 L A T E 2 P G M

6 CENTRAL PROCESSING UNIT

6.1 INTRODUCTION

6.2 MAIN FEATURES

6.3 CPU REGISTERS

temporary storage areas for data manipulation. (Program Counter High which is the MSB). Figure 11. CPU Registers

CPU REGISTERS (cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions. These bits can be individually tested and/or con- trolled by specific instructions. Bit 4 = H Half carry This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested usin g the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines. Bit 3 = I Interrupt mask This bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET in- structions and is tested by the JRM and JRNM in- structions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. Bit 2 = N Negative This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- tions. Bit 1 = Z Zero This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. 111HINZC

ways pointing to the next free location in the stack. popped from the stack (see Figure 12). mented and the context is pushed on the stack. and the context is popped from the stack. terrupt five locations in the stack area. Figure 12. Stack Manipulation Example

1 SP6 SP5 SP4 SP3 SP2 SP1 SP0

7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a ran ge of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. Main features ■ Clock Management – 1 MHz internal RC oscillator (enabled by op- tion byte, available on ST7LITE15B and ST7LITE19B devices only) – 1 to 16 MHz External crystal/ceramic resona- tor (selected by option byte) – External Clock Input (enabled by option byte) – PLL for multiplying the frequency by 8 or 4 (enabled by option byte) – For clock ART counter only: PLL32 for multi- plying the 8 MHz frequency by 4 (enabled by option byte). The 8 MHz input frequency is mandatory and can be obtained in the follow- ing ways: –1 MHz RC + PLLx8 –16 MHz external clock (internally divided by 2) –2 MHz. external clock (internally divided by 2) + PLLx8 –Crystal oscillator with 16 MHz output fre- quency (internally divided by 2) ■ Reset Sequence Manager (RSM) ■ System Integrity Management (SI) – Main supply Low voltage detection (LVD) with reset generation (enabled by option byte) – Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply (en- abled by option byte)

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT

The device contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5V-5.5V). It must be calibrat- ed to obtain the frequency required in the applica- tion. This is done by soft ware writing a 10-bit cali- bration value in the RC CR (RC Control Register) and in the bits 6:5 in the SICSR (SI Control Status Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be load- ed in the RCCR. Predefined calibration values are stored in EEPROM for 3 and 5V V DD supply volt- ages at 25°C, as shown in the following table. 1. DEE0h, DEE1h, DEE2h and DEE3h addresses are located in a reserved area of non-volatile memory. They are read-only bytes for the applica- tion code. This area cannot be erased or pro- grammed by any ICC operation. For compatibility reasons with the SICSR register, CR[1:0] bits are stored in the 5th and 6th position of DEE1 and DEE3 addresses. Notes: – In 38-pulse ICC mode, the internal RC oscillator is forced as a clock source, regardless of the se- lection in the option byte. For ST7LITE10B devic- es which do not support the internal RC oscillator, the “option byte disabled” mode must be used (35-pulse ICC mode entry, clock provid- ed by the tool). – See “ELECTRICAL CHARACTERISTICS” on page 110. for more information on the frequency and accuracy of the RC oscillator. – To improve clock stability and frequency accura- cy, it is recommended to place a decoupling ca- pacitor, typically 100nF, between the V DD and VSS pins as close as possible to the ST7 device. – These bytes are systematically programmed by ST, including on FASTROM devices. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the RC frequency using an ex- ternal reference signal.

7.2 PHASE LOCKED LOOP

The PLL can be used to multiply a 1MHz frequen- cy from the RC oscillator or the external clock by 4 or 8 to obtain f OSC of 4 or 8 MHz. The PLL is ena- bled and the multiplication factor of 4 or 8 is select- ed by 2 option bits. – The x4 PLL is intended for operation with V DD in the 2.7V to 3.3V range RCCR Conditions ST7LITE1xB Address RCCRH0 V DD=5V TA=25°C fRC=1MHz DEE0h 1) (CR[9:2]) RCCRL0 DEE1h 1) (CR[1:0]) RCCRH1 V DD=3.3V TA=25°C fRC=1MHz DEE2h 1) (CR[9:2]) RCCRL1 DEE3h 1) (CR[1:0])

fOSC is driven by the external clock. Figure 13. PLL Output Frequency Timing

13.3.5 Internal RC Oscillator and PLL)

of the LOCKED bit in the SICSR register.

7.3 REGISTER DESCRIPTION

MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:2 = Reserved, must be kept cleared. Bit 1 = MCO Main Clock Out enable This bit is read/write by software and cleared by hardware after a reset. This bit allows to enable the MCO output clock. 0: MCO clock disabled, I/O port free for general purpose I/O. 1: MCO clock enabled. Bit 0 = SMS Slow Mode select This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock f OSC or fOSC/32. 0: Normal mode (fCPU = fOSC 1: Slow mode (fCPU = fOSC/32) RC CONTROL REGISTER (RCCR) Read / Write Reset Value: 1111 1111 (FFh) Bits 7:0 = CR[9:2] RC Oscillator Frequency Ad- justment Bits These bits must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. The application can store the correct value for each voltage range in EEPROM and write it to this register at start-up. 00h = maximum available frequency FFh = lowest available frequency These bits are used with the CR[1:0] bits in the SICSR register. Refer to section 7.6.4 on page 35. Note: To tune the oscillator, write a series of differ- ent values in the register until the correct frequen- cy is reached. The fastest method is to use a di- chotomy starting with 80h.

000000 MCO SMS

CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2

Figure 14. Clock Management Block Diagram

7.4 MULTI-OSCILLATOR (MO)

electrical characteristics section for more details. the OSC1 pin while the OSC2 pin is tied to ground. selected by default as external clock. cording to the selected oscillator. else can be found as general purpose IO. Table 4. ST7 Clock Sources

7.5 RESET SEQUENCE MANAGER (RSM)

7.5.1 Introduction

ways kept low during the delay phase. dresses FFFEh-FFFFh in the ST7 memory map. Figure 15. RESET Sequence Phases

7.5.2 Asynchronous External RESET pin

output with integrated R ON weak pull-up resistor. Electrical Characteristic section for more details. can enter reset state even in HALT mode.

Figure 16. Reset Block Diagram Note 1: See “Illegal Opcode Reset” on page 107. for more details on illegal opcode reset conditions.

7.5.3 External Power-On RESET

level specified for the selected fOSC frequency. work connected to the RESET pin.

7.5.4 Internal Low Voltage Detector (LVD)

VDD<VIT- (falling edge) as shown in Figure 17.

7.5.5 Internal Watchdog RESET

Watchdog counter overflow is shown in Figure 17. low during at least tw(RSTL)out. Figure 17. RESET Sequences

7.6 SYSTEM INTEGRITY MANAGEMENT (SI)

7.6.1 Low Voltage Detector (LVD)

The LVD function is illustrated in Figure 18. byte to be low, medium or high. Figure 18. Low Voltage Detector vs Reset

Figure 19. Reset and Supply Management Block Diagram

00 LVDRFLOCKEDWDGRF0

7.6.2 Auxiliary Voltage Detector (AVD)

asitic detection (hysteresis). abled through the option byte.

7.6.2.1 Monitoring the VDD Main Supply

(see section 15.1 on page 149). VIT-(AVD) threshold (AVDF bit is set). Figure 20. Using the AVD to Monitor V

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.3 Low Power Modes

7.6.3.1 Interrupts

The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is re- set (RIM instruction). Mode Description WAIT No effect on SI. AVD interrupts cause the device to exit from Wait mode. HALT The SICSR register is frozen. The AVD remains active. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0110 0xx0 (6xh) Bit 7 = LOCK32 PLL 32Mhz Locked Flag This bit is set and cleared by hardware. It is set au- tomatically when the PLL 32Mhz reaches its oper- ating frequency 0: PLL32 not locked 1: PLL32 locked Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad- justment bits These bits, as well as CR[9:2] bits in the RCCR register must be written immediately after reset to adjust the RC oscillator frequency and to obtain an accuracy of 1%. Refer to section 7.3 on page 25. Bit 4 = WDGRF Watchdog Reset flag This bit indicates that the last Reset was generat- ed by the Watchdog peripheral. It is set by hard- ware (watchdog reset) and cleared by software (reading the SICSR register or writing 0 to this bit) or by an LVD Reset (to ensure a stable cleared state of the WDGRF flag when the CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table. Bit 3 = LOCKED PLL Locked Flag This bit is set and cleared by hardware. It is set au- tomatically when the PLL reaches its operating fre- quency. 0: PLL not locked 1: PLL locked Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generat- ed by the LVD block. It is set by hardware (LVD re- set) and cleared by software (by reading). When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Bit 1 = AVDF Voltage Detector Flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is gen- erated when the AVDF bit is set. Refer to Figure 20 and to Section 7.6.2.1 for additional details. 0: V DD over AVD threshold 1: VDD under AVD threshold Bit 0 = AVDIE Voltage Detector Interrupt Enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automati- cally cleared when software enters the AVD inter- rupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Application notes The LVDRF flag is not cleared when another RE- SET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the origi- nal failure. In this case, a watchdog reset can be detected by software while an external reset can not. PLL TEST REGISTER (PLLTST) Read/Write Reset Value: 0000 0000 (00h) Bit 7 : PLLdiv2 PLL clock divide by 2 This bit is read or write by software and cleared by hardware after re set. This bit will divide the PLL output clock by 2. 0 : PLL output clock 1 : Divide by 2 of PLL output clock Refer “Clock Management Block Diagram” on page 26 Note : Write of this bit will be effective after 2 Tcpu cycles (if system clock is 8mhz) else 1 cycle (if system clock is 4mhz) i.e. effective time is 250ns. Bit 6:0 : Reserved , Must always be cleared LOCK

32 CR1 CR0 WDG

RF LOCKED LVDRF AVDF AVDIE RESET Sources LVDRF WDGRF External RESET pin 0 0 Watchdog 0 1 LVD 1 X PLLdiv2 0 0 0 0 0 0 0

8 INTERRUPTS

The ST7 core may be interrupted by one of two dif- ferent methods: Maskable hardware interrupts as listed in the “interrupt mapping” table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 1. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: – Normal processing is suspended at the end of the current instruction execution. – The PC, X, A and CC registers are saved onto the stack. – The I bit of the CC register is set to prevent addi- tional interrupts. – The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping table for vector address- es). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit is cleared and the main program resumes. Priority Management By default, a servicing interrupt cannot be inter- rupted because the I bit is set by hardware enter- ing in interrupt routine. In the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the Interrupt Map- ping table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifi- cally mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT” column in the Interrupt Mapping ta- ble).

8.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc- tion is executed regardless of the state of the I bit. It is serviced according to the flowchart in Figure 1.

8.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to le ave the HALT low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt tr iggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the Mis- cellaneous or Interrupt register (if available) ap- plies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity.

8.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: – The I bit of the CC register is cleared. – The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status register or – Access to the status register while the flag is set followed by a read or write of an associated reg- ister. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear se- quence is executed.

Figure 21. Interrupt Processing Flowchart Table 5. Interrupt Mapping Note 1: This interrupt exits the MCU from “Auto Wake-up from Halt” mode only. Note 2 : These interrupts exit the MCU from “ACTIVE-HALT” mode only.

0 AWU Auto Wake Up Interrupt AWUCSR yes 1) FFFAh-FFFBh

5 LITE TIMER LITE TIMER RTC2 interrupt LTCSR2 no FFF0h-FFF1h

6 Comparator Comparator Interrupt CMPCR no FFEEh-FFEFh

7 SI AVD interrupt SICSR no FFECh-FFEDh

8 AT TIMER

9 AT TIMER Overflow Interrupt ATCSR yes

10 LITE TIMER LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h

11 LITE TIMER RTC1 Interrupt LTCSR yes 2) FFE4h-FFE5h

12 SPI SPI Peripheral Interrupts SPICSR yes FFE2h-FFE3h

13 AT TIMER AT TIMER Overflow Interrupt ATCSR2 no FFE0h-FFE1h

(Port B0) according to Table 6. (Port B3) according to Table 6. (Port A7) according to Table 6. (Port A0) according to Table 6.

1. These 8 bits can be written only when the I bit in
2. Changing the sensitivity of a particular external

Table 6. Interrupt Sensitivity Bits

1. PB4 cannot be used as an external interrupt in

INTERRUPTS (Cont’d) Bit 3:2 = ei1[1:0] ei1 pin selection These bits are written by software. They select the Port A I/O pin used for the ei1 external interrupt ac- cording to the table below. External Interrupt I/O pin selection * Reset State Bit 1:0 = ei0[1:0] ei0 pin selection These bits are written by software. They select the Port A I/O pin used for the ei0 external interrupt ac- cording to the table below. External Interrupt I/O pin selection * Reset State ei11 ei10 I/O Pin 0 0 PA4 0 1 PA5 1 0 PA6 1 1 PA7* ei01 ei00 I/O Pin 0 0 PA0 * 0 1 PA1 1 0 PA2 1 1 PA3

9 POWER SAVING MODES

9.1 INTRODUCTION

Figure 22. Power Saving Mode Transitions

9.2 SLOW MODE

the available supply voltage.

1. The CPU and peripherals are clocked at this

Figure 23. SLOW Mode Clock Transition

9.3 WAIT MODE

sumption mode by stopping the CPU. the interrupt or Reset service routine. or an Interrupt occurs, causing it to wake up. Figure 24. WAIT Mode Flow-chart

1. Before servicing an interrupt, the CC register is

256 OR 4096 CPU CLOCK

9.4 HALT MODE

cluding the operation of the on-chip peripherals. tion 15.1 on page 149 for more details). Figure 25. HALT Timing Overview Figure 26. HALT Mode Flow-chart

1. WDGHALT is an option bit. See option byte sec-
2. Peripheral clocked with an external clock source
3. Only some specific interrupts can exit the MCU

fer to Table 5 Interrupt Mapping for more details.

1. Before servicing an interrupt, the CC register is
2. If the PLL is enabled by option byte, it outputs

POWER SAVING MODES (Cont’d)

9.4.1 Halt Mode Recommendations

– Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, re-initialize the corresponding I/ O as “Input Pull-up with Interrupt” before execut- ing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference or by an unforeseen logical condition. – For the same reason, re-initialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. – The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memo- ry. For example, avoid defining a constant in pro- gram memory with the value 0x8E. – As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits be- fore executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corre- sponding to the wake-up event (reset or external interrupt).

9.5 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power con- sumption mode of the MCU with a real time clock available. It is entered by executing the ‘HALT’ in- struction. The decision to enter either in ACTIVE- HALT or HALT mode is given by the LTCSR/ATC- SR register status as shown in the following table: The MCU can exit ACTIVE-HALT mode on recep- tion of a specific interrupt (see Table 5, “Interrupt Mapping,” on page 37) or a RESET. – When exiting ACTIVE-HALT mode by means of a RESET, a 256 or 4096 CPU cycle delay oc- curs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see Figure 28). – When exiting ACTIVE-HALT mode by means of an interrupt, the CPU immediately resumes oper- ation by servicing the interrupt vector which woke it up (see Figure 28). When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately (see Note 3). In ACTIVE-HALT mode, on ly the main oscillator and the selected timer counter (LT/AT) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as ex- ternal or auxiliary oscillator). Note: As soon as ACTIVE-HALT is enabled, exe- cuting a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. LTCSR1 TB1IE bit ATCSR OVFIE bit ATCSR CK1 bit ATCSR CK0 bit Meaning 0x x 0 ACTIVE-HALT mode disabled00 x x 1x x x ACTIVE-HALT mode enabledx1 0 1

Figure 27. ACTIVE-HALT Timing Overview Figure 28. ACTIVE-HALT Mode Flow-chart

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

1. Peripherals clocked with an external clock
2. Only the RTC1 interrupt and some specific inter-

rupts can exit the MCU from ACTIVE-HALT mode.

1. Before servicing an interrupt, the CC register is

9.6 AUTO WAKE UP FROM HALT MODE

curate realtime clock available. Figure 29. AWUFH Mode Block Diagram software reading the AWUCSR register.

set (see Section 9.4 HALT MODE). cluding the operation of the on-chip peripherals. lator like the AWU oscillator). Figure 30. AWUF Halt Timing Diagram

Figure 31. AWUFH Mode Flow-chart Notes:

1. WDGHALT is an option bit. See option byte sec-
2. Peripheral clocked with an external clock source
3. Only an AWUFH interrupt and some specific in-

Mapping,” on page 37 for more details.

1. Before servicing an interrupt, the CC register is
2. If the PLL is enabled by option byte, it outputs

9.6.0.1 Register Description

viding the right value in the AWUPRE register. before waking up automatically. Table 7. AWU Register Map and Reset Values

00000 AWU

10 I/O PORTS

10.1 INTRODUCTION

The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include exter- nal interrupt, alternate signal input/output for on- chip peripherals or analog input.

10.2 FUNCTIONAL DESCRIPTION

A Data Register (DR) and a Data Direction Regis- ter (DDR) are always associated with each port. The Option Register (OR), which allows input/out- put options, may or may not be implemented. The following description take s into account the OR register. Refer to the Port Configuration table for device specific information. An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit x corre- sponding to pin x of the port. Figure 32 shows the generic I/O block diagram.

10.2.1 Input Modes

Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin. If an OR bit is available, different input modes can be configured by software: floating or pull-up. Re- fer to I/O Port Implementation section for configu- ration. Notes: 1. Writing to the DR modifies the latch value but does not change the state of the input pin. 2. Do not use read/mod ify/write instructions (BSET/BRES) to modify the DR register.

10.2.1.1 External Interrupt Function

Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or lev- el input on the I/O generates an interrupt request via the corresponding interrupt vector (eix). Falling or rising edge sensitivity is programmed in- dependently for each interrupt vector. The Exter- nal Interrupt Control Register (EICR) or the Miscel- laneous Register controls this sensitivity, depend- ing on the device. Each external interrupt vector is linked to a dedi- cated group of I/O port pins (see pinout description and interrupt section). If several I/O interrupt pins on the same interrupt vector are selected simulta- neously, they are logically combined. For this rea- son if one of the interrupt pins is tied low, it may mask the others. External interrupts are hardware interrupts. Fetch- ing the corresponding interrupt vector automatical- ly clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spu- rious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disa- bled by the OR register. To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the OR register bit and configuring the appropriate sensitivity again. Caution: In case a pin level change occurs during these operations (asynchro nous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts be- fore and to reenable them after the complete pre- vious sequence in order to avoid an external inter- rupt occurring on the unwanted edge. This corresponds to the following steps: 1. To enable an external interrupt: – set the interrupt mask with the SIM instruction (in cases where a pin level change could oc- cur) – select rising edge – enable the external interrupt through the OR register – select the desired sensitivity if different from rising edge – reset the interrupt ma sk with the RIM instruc- tion (in cases where a pin level change could occur) 2. To disable an external interrupt: – set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could occur) – select falling edge – disable the external interrupt through the OR register

– select rising edge – reset the interrupt ma sk with the RIM instruc- tion (in cases where a pin level change could occur)

10.2.2 Output Modes

Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value. If an OR bit is available, different output modes can be selected by software: push-pull or open- drain. Refer to I/O Port Implementation section for configuration. DR Value and Output Pin Status

10.2.3 Alternate Functions

Many ST7s I/Os have one or more alternate func- tions. These may include output signals from, or input signals to, on-chip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports. A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripher- al’s control register). The peripheral configures the I/O as an output and takes priority over standard I/ O programming. The I/O’s state is readable by ad- dressing the corresponding I/O data register. Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current con- sumption. Before using an I/O as an alternate in- put, configure it without interrupt. Otherwise spuri- ous interrupts can occur. Configure an I/O as input floating for an on-chip peripheral signal which can be input and output. Caution: I/Os which can be configured as both an analog and digital alternate function need special atten- tion. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function. DR Push-Pull Open-Drain 0V OL VOL 1V OH Floating

Figure 32. I/O Port General Block Diagram Table 8. I/O Port Mode Options table for device specific information.

Table 9. I/O Configurations

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

1. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

rail, connected to the ADC input.

10.3 I/O PORT IMPLEMENTATION

spurious interrupt generation. Figure 33. Interrupt I/O Port State Transitions

10.4 UNUSED I/O PINS

age levels. Refer to Section 13.8.

10.5 LOW POWER MODES

10.6 INTERRUPTS

register is cleared (RIM instruction). cause the device to exit from WAIT mode. cause the device to exit from HALT mode.

10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION

Table 10. Port Configuration (Standard ports) Table 11. I/O Port Register Map and Reset Values

10.8 MULTIPLEXED INPUT/OUTPUT PORTS

OSC1/PC0 are multiplexed on one pin (pin20) and OSC2/PC1 are multiplexed on another pin (pin 19). 0002h PAOR Reset Value MSB 01 00000 LSB 0003h PBDR Reset Value MSB 11 11111 LSB 0004h PBDDR Reset Value MSB 00 00000 LSB 0005h PBOR Reset Value MSB 00 00000 LSB 0006h PCDR Reset Value MSB 00 00001 LSB 0007h PCDDR Reset Value MSB 00 00000 LSB Address (Hex.) Register Label 76543210

11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

11.1.2 Main Features

11.1.3 Functional Description

programmed by the user in 64 increments. Figure 34. Watchdog Block Diagram

activated it cannot be disabled, except by a reset. set (the WDGA bit is set and the T6 bit is cleared).

1. The timing variation shown in Table 12 is due to
2. The number of CPU clock cycles applied during

into account in addition to these timings.

11.1.4 Hardware Watchdog Option

11.1.4.1 Using Halt Mode with the WDG

11.1.5 Interrupts

11.1.6 Register Description

Bit 7 = WDGA Activation bit. watchdog can generate a reset. dog option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). Table 13. Watchdog Timer Register Map and Reset Values

11.2 DUAL 12-BIT AUTORELOAD TIMER 4 (AT4)

11.2.1 Introduction

capture register and four PWM output channels.

11.2.2 Main Features

Figure 35. Single Timer Mode (ENCNTR2=0)

Figure 36. Dual Timer Mode (ENCNTR2=1)

11.2.3 Functional Description

11.2.3.1 PWM Mode

ent frequency controlled by CNTR2 and ATR2. minimum value is 1 kHz (ATR register value = 0). minimum value is 8 kHz (ATR register value = 0).

1. The maximum value of ATR is 4094 because it
2. To update the DCRx registers at 32 MHz, the

after a write to the DCRx registers. ing transfer bit (TRANx bit) is set. PWMx outputs driven by counter 2. At reset, the counter starts counting from 0. Figure 37. PWM Polarity Inversion sion when triggered by the counter overflow input. bled using the OEx bits in the PWMCR register.

11.2.3.2 Dead Time Generation

mable dead time by setting the DTE bit. will take place only after an overflow.

1. Dead time is generated only when DTE=1 and

put signals will be at their reset state.

1. Half Bridge driving is possible only if polarities of

PWM0/PWM1 signals will be generated.

1. Dead Time generation does not work at 1 ms

Figure 40. Dead Time Generation

11.2.3.3 Break Function

BPEN bit in the BREAKCR register. if respective OEx bit is set in PWMCR register. enables the break for all PWM channels. respective OEx is set. (after the inverter). set value, i.e. 00h (if BREN1 = 1). set value,i.e. 00h (if BREN2 = 1). ware), Timer takes the control of PWM ports. Figure 41. Block Diagram of Break Function

11.2.3.4 Output Compare Mode

Preload DCRxH and DCRxL registers. CNTR2 is compared with DCR2 or DCR3.

1. The output compare function is only available

for DCRx values other than 0 (reset value).

1. Duty cycle registers are buffered internally. The

Figure 42. Block Diagram of Output Compare Mode (single timer)

11.2.3.5 Input Capture Mode

Figure 43. Block Diagram of Input Capture Mode Figure 44. Input Capture timing diagram

32 MHz

ture value. Refer to Figure 11. Figure 45. Long Range Input Capture Block Diagram

1. Since the input capture flags (ICF) for both tim-
2. If the ICS bit changes (from 0 to 1 or from 1 to

– First, reset both ICIE bits. – And then set the ICIE bit of desired interrupt.

1. How to compute a pulse length with long input

8 LSB bits

12 MSB bits

where N = No of overflows of 12-bit CNTR1. Figure 46. Long Range Input Capture Timing Diagram

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)

11.2.3.6 One Pulse Mode

One Pulse Mode can be used to control PWM2/3 signal with an external LTIC pin. This mode is available only in dual timer mode i.e. only for CNTR2, when the OP_EN bit in PWM3CSR regis- ter is set. One Pulse Mode is activated by the external LTIC input. The active edge of the LTIC pin is selected by the OPEDGE bit in the PWM3CSR register. After getting the active edge of the LTIC pin, CNTR2 is reset (000h) and PWM3 is set to high. CNTR2 starts counting from 000h, when it reaches the active DCR3 value then the PWM3 output goes low. Till this time, any further tr ansitions on the LTIC signal will have no effect. If there are LTIC transitions after CNTR2 reaches the DCR3 value, CNTR2 is reset again and the PWM3 output goes high. If there is no LTIC ac tive edge then CNTR2 will count till it reaches the ATR2 value, and then it will be reset again and the PWM3 output is set to high. The counter again starts counting from 000h, when it reaches the active DCR3 value the PWM3 output goes low, the coun ter counts till it reaches the ATR2 value, it resets and the PWM3 output is set to high and it goes on the same way. The same operation applies for the PWM2 output, but in this case the comparison is done on the DCR2 value. The OP_EN and OPEDGE bits take effect on the fly and are not synchronized with the CNTR2 over- flow. The OP2/3 bits can be used to inverse the polarity of the PWM2/3 outputs in one-pulse mode. The update of these bits (OP2/3) is synchronized with the CNTR2 overflow, they will be updated if the TRAN2 bit is set. Notes: 1. If CNTR2 is running at 32 MHz, the time taken from activation of LTIC input and CNTR2 reset is between 2 and 3 t CNTR2 cycles, i.e. 66 ns to 99 ns (with 8 MHz fcpu). 2. The Lite Timer input capture interrupt must be disabled while 12-bit AR Timer is in One Pulse Mode. This is to avoid spurious interrupts. 3. The priority of various events affecting PWM3 is as follows: – Break (Highest priority) – One-pulse mode with active LTIC edge – Forced overflow (by FORCE2 bit) – One-pulse mode without active LTIC edge – Normal PWM operation. (Lowest priority) 4. It is possible to synchronize the update of DCR2/3 registers and OP2/3 bits with the CNTR2 reset. This is managed by the overflow interrupt which is generated if CNTR2 is reset either due to an ATR match or an active pulse on the LTIC pin. 5. Updating the DCR2/3 registers and OP2/3 bits in one-pulse mode is done dynamically by soft- ware using force update (FORCE2 bit in the ATCSR2 register). 6. DCR3 update in this mode is not synchronized with any event. Consequently the next PWM3 cy- cle just after the change may be longer than ex- pected (refer to Figure 15). 7. In One Pulse Mode the ATR2 value must be greater than the DCR2/3 value for the PWM2/3 outputs. (contrary to normal PWM mode) 8. If there is an active edge on the LTIC pin after the CNTR2 has reset due to an ATR2 match, then the timer gets reset again. The duty cycle may be modified depending on whether the new DCR val- ue is less than or more than the previous value. 9. The TRAN2 bit must be set simultaneously with the FORCE2 bit in the same instruction after a write to the DCR register. 10. The ATR2 value should be changed after an overflow in one pulse mode to avoid an irregular PWM cycle. 11. When exiting from one pulse mode, the OP_EN bit in the PWM3CSR register must be re- set first and then the ENCNTR2 bit (if CNTR2 is to be stopped). How to Enter One Pulse Mode: 1. Load the ATR2H/ATR2L registers with required value. 2. Load the DCR3H/DCR3L registers for PWM3 output. The ATR2 value must be greater than DCR3. 3. Set the OP3 bit in the PWM3CSR register if po- larity change is required. 4. Start the CNTR2 counter by setting the ENCNTR2 bit in the ATCSR2 register. 5. Set TRAN2 bit in ATCSR2 to enable transfer. 6. Wait for an overflow event by polling the OVF2 flag in the ATCSR2 register. 7. Select the counter clock using the CK[1:0] bits in the ATCSR register.

1. Set the OP_EN bit in the PWM3CSR register to
2. Enable the PWM3 output by setting the OE3 bit

placed by forced update (writing the FORCE2 bit). the CNTR2, DCR2/3 & ATR2 registers are reset. ized again when break is removed. Figure 47. Block Diagram of One Pulse Mode Figure 48. One Pulse Mode and PWM Timing Diagram

000 DCR2/3 000 DCR2/3 ATR2 000

Note 1: When OP_EN=0, LTIC edges are not taken into account as the timer runs in PWM mode.

Figure 49. Dynamic DCR2/3 update in One Pulse Mode

11.2.3.7 Force Update

pare, Input Capture, One-pulse (refer to Figure 15. Figure 50. Force Overflow Timing Diagram

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)

11.2.4 Low Power Modes

11.2.5 Interrupts

Note: The CMP and AT4 IC events are connected to the same interrupt vector. The OVF event is mapped on a separate vector (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on AT timer HALT AT timer halted. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Exit from Active- Halt Overflow Event OVF1 OVIE1 Yes No Yes AT4 IC Event ICF ICIE Yes No No CMP Event CMPFx CMPIE Yes No No Overflow Event2 OVF2 OVIE2 Yes No No

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)

11.2.6 Register Description

TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0x00 0000 (x0h) Bit 7 = Reserved. Bit 6 = ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the ATICR register (a read access to ATICRH or ATICRL will clear this flag). Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Bit 5 = ICIE IC Interrupt Enable. This bit is set and cleared by software. 0: Input capture interrupt disabled 1: Input capture interrupt enabled Bits 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter. Bit 2 = OVF1 Overflow Flag. This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter1 CNTR1 from FFFh to ATR1 value. 0: No counter overflow occurred 1: Counter overflow occurred Bit 1 = OVFIE1 Overflow Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. 0: Overflow interrupt disabled. 1: Overflow interrupt enabled. Bit 0 = CMPIE Compare Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. It can be used to mask the interrupt generated when any of the CMPFx bit is set. 0: Output compare interrupt disabled. 1: Output Compare interrupt enabled. COUNTER REGISTER 1 HIGH (CNTR1H) Read only Reset Value: 0000 0000 (00h) COUNTER REGISTER 1 LOW (CNTR1L) Read only Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved. Bits 11:0 = CNTR1[11:0] Counter Value. This 12-bit register is read by software and cleared by hardware after a reset. The counter CNTR1 in- crements continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. As there is no latch, it is recom- mended to read LSB first. In this case, CNTR1H can be incremented between the two read opera- tions and to have an accurate result when f timer=fCPU, special care must be taken when CNTR1L values close to FFh are read. When a counter overflow occurs, the counter re- starts from the value specified in the ATR1 regis- ter.

0 ICF ICIE CK1 CK0 OVF1 OVFIE1 CMPIE

Counter Clock Selection CK1 CK0 OFF 0 0

32 MHz 1 1

fLTIMER (1 ms timebase @ 8 MHz) 0 1 fCPU 10 15 8

0000 CNTR1_

CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) AUTORELOAD REGISTER (ATR1H) Read / Write Reset Value: 0000 0000 (00h) AUTORELOAD REGISTER (ATR1L) Read / Write Reset Value: 0000 0000 (00h) Bits 11:0 = ATR1[11:0] Autoreload Register 1. This is a 12-bit register which is written by soft- ware. The ATR1 register value is automatically loaded into the upcounter CNTR1 when an over- flow occurs. The register value is used to set the PWM frequency. PWM OUTPUT CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) Bits 7:0 = OE[3:0] PWMx output enable. These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled. PWMx Output Alternate Function disabled (I/O pin free for general pur- pose I/O) 1: PWM mode enabled PWMx CONTROL STATUS REGISTER (PWMxCSR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:4= Reserved, must be kept cleared. Bit 3 = OP_EN One Pulse Mode Enable This bit is read/write by software and cleared by hardware after a reset. This bit enables the One Pulse feature for PWM2 and PWM3. (Only availa- ble for PWM3CSR) 0: One Pulse mode disabled for PWM2/3. 1: One Pulse mode enabled for PWM2/3. Bit 2 = OPEDGE One Pulse Edge Selection. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the LTIC signal for One Pulse feature. This bit will be effective only if OP_EN bit is set. (Only available for PWM3CSR) 0: Falling edge of LTIC is selected. 1: Rising edge of LTIC is selected. Bit 1 = OPx PWMx Output Polarity. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM signal. 0: The PWM signal is not inverted. 1: The PWM signal is inverted. Bit 0 = CMPFx PWMx Compare Flag. This bit is set by hardware and cleared by software by reading the PWMxCSR register. It indicates that the upcounter value matches the Active DCRx register value. 0: Upcounter value does not match DCRx value. 1: Upcounter value matches DCRx value. 15 8 0 0 0 0 ATR11 ATR10 ATR9 ATR8 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 0O E 30O E 20O E 10O E 0

0000 O P _ E N OPEDG

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) BREAK CONTROL REGISTER (BREAKCR) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = BRSEL Break Input Selection This bit is read/write by software and cleared by hardware after reset. It selects the active Break signal from external BREAK pin and the output of the comparator. 0: External BREAK pin is selected for break mode. 1: Comparator output is selected for break mode. Bit 6 = BREDGE Break Input Edge Selection This bit is read/write by software and cleared by hardware after reset. It selects the active level of Break signal. 0: Low level of Break selected as active level. 1: High level of Break selected as active level. Bit 5 = BA Break Active. This bit is read/write by software, cleared by hard- ware after reset and set by hardware when the ac- tive level defined by the BREDGE bit is applied on the BREAK pin. It activates/deactivates the Break function. 0: Break not active 1: Break active Bit 4 = BPEN Break Pin Enable. This bit is read/write by software and cleared by hardware after Reset. 0: Break pin disabled 1: Break pin enabled Bits 3:0 = PWM[3:0] Break Pattern. These bits are read/write by software and cleared by hardware after a reset. They are used to force the four PWMx output signals into a stable state when the Break function is active and correspond- ing OEx bit is set. PWMx DUTY CYCLE REGISTER HIGH (DCRxH) Read / Write Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved. PWMx DUTY CYCLE REGISTER LOW (DCRxL) Read / Write Reset Value: 0000 0000 (00h) Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value This 12-bit value is writ ten by software. It defines the duty cycle of the corresponding PWM output signal (see Figure 4). In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see Figure 4 ). In Output Compare mode, they define the value to be com- pared with the 12-bit upcounter value. INPUT CAPTURE REGISTER HIGH (ATICRH) Read only Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved. INPUT CAPTURE REGISTER LOW (ATICRL) Read only Reset Value: 0000 0000 (00h) BRSEL BREDGE BA BPEN PWM3 PWM2 PWM1 PWM0 15 8 0 0 0 0 DCR11 DCR10 DCR9 DCR8 DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 15 8 0 0 0 0 ICR11 ICR10 ICR9 ICR8 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) Bits 11:0 = ICR[11:0] Input Capture Data. This is a 12-bit register which is readable by soft- ware and cleared by hardware after a reset. The ATICR register contains captured the value of the 12-bit CNTR1 register when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS). Capture will only be performed when the ICF flag is cleared. BREAK ENABLE REGISTER (BREAKEN) Read/Write Reset Value: 0000 0011 (03h) Bits 7:2 = Reserved, must be kept cleared. Bit 1 = BREN2 Break Enable for Counter 2 This bit is read/write by software. It enables the break functionality for Counter2 if BA bit is set in BREAKCR. It controls PWM2/3 if ENCNTR2 bit is set. 0: No Break applied for CNTR2 1: Break applied for CNTR2 Bit 0 = BREN1 Break Enable for Counter 1 This bit is read/write by software. It enables the break functionality for Counter1. If BA bit is set, it controls PWM0/1 by default, and controls PWM2/3 also if ENCNTR2 bit is reset. 0: No Break applied for CNTR1 1: Break applied for CNTR1 TIMER CONTROL REGISTER2 (ATCSR2) Read/Write Reset Value: 0000 0011 (03h) Bit 7 = FORCE2 Force Counter 2 Overflow This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It is reset by hard- ware one CPU clock cycle after counter 2 overflow has occurred. 0 : No effect on CNTR2 1 : Loads FFFh in CNTR2 Note: This bit must not be reset by software Bit 6 = FORCE1 Force Counter 1 Overflow This bit is read/set by software. When set, it loads FFFh in CNTR1 register. It is reset by hardware one CPU clock cycle after counter 1 overflow has occurred. 0 : No effect on CNTR1 1 : Loads FFFh in CNTR1 Note: This bit must not be reset by software Bit 5 = ICS Input Capture Shorted This bit is read/write by software. It allows the AT- timer CNTR1 to use the LTIC pin for long input capture. 0 : ATIC for CNTR1 input capture 1 : LTIC for CNTR1 input capture Bit 4 = OVFIE2 Overflow interrupt 2 enable This bit is read/write by software and controls the overflow interrupt of counter2. 0: Overflow interrupt disabled. 1: Overflow interrupt enabled. Bit 3 = OVF2 Overflow Flag. This bit is set by hardware and cleared by software by reading the ATCSR2 register. It indicates the transition of the counter2 from FFFh to ATR2 val- ue. 0: No counter overflow occurred 1: Counter overflow occurred Bit 2 = ENCNTR2 Enable counter2 for PWM2/3 This bit is read/write by software and switches the PWM2/3 operation to the CNTR2 counter. If this bit is set, PWM2/3 will be generated using CNTR2. 0: PWM2/3 is generated using CNTR1. 1: PWM2/3 is generated using CNTR2. Note: Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the counter will restart from the last value.

000000 B R E N 2 B R E N 1

1 ICS OVFIE2 OVF2 ENCNT

DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d) Bit 1= TRAN2 Transfer enable2 This bit is read/write by software, cleared by hard- ware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2. It allows the value of the Preload DCRx registers to be transferred to the Active DCRx registers after the next overflow event. The OPx bits are transferred to the shadow OPx bits in the same way. Notes: 1. DCR2/3 transfer will be controlled using this bit if ENCNTR2 bit is set. 2. This bit must not be reset by software Bit 0 = TRAN1 Transfer enable 1 This bit is read/write by software, cleared by hard- ware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR1. It allows the value of the Preload DCRx registers to be transferred to the Active DCRx reg- isters after the next overflow event. The OPx bits are transferred to the shadow OPx bits in the same way. Notes: 1. DCR0,1 transfers are always controlled using this bit. 2. DCR2/3 transfer will be controlled using this bit if ENCNTR2 is reset. 3.This bit must not be reset by software AUTORELOAD REGISTER2 (ATR2H) Read / Write Reset Value: 0000 0000 (00h) AUTORELOAD REGISTER (ATR2L) Read / Write Reset Value: 0000 0000 (00h) Bits 11:0 = ATR2[11:0] Autoreload Register 2. This is a 12-bit register which is written by soft- ware. The ATR2 register value is automatically loaded into the upcounter CNTR2 when an over- flow of CNTR2 occurs. The register value is used to set the PWM2/PWM3 frequency when ENCNTR2 is set. DEAD TIME GENERATOR REGISTER (DTGR) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = DTE Dead Time Enable This bit is read/write by software. It enables a dead time generation on PWM0/PWM1. 0: No Dead time insertion. 1: Dead time insertion enabled. Bits 6:0 = DT[6:0] Dead Time Value These bits are read/write by software. They define the dead time inserted between PWM0/PWM1. Dead time is calculated as follows: Dead Time = DT[6:0] x Tcounter1 Note: 1. If DTE is set and DT[6:0]=0, PWM output sig- nals will be at their reset state. 15 8 0 0 0 0 ATR11 ATR10 ATR9 ATR8 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 DTE DT6 DT5 DT4 DT3 DT2 DT1 DT0

Table 14. Register Map and Reset Values

10 ATR1H

11 ATR1L

12 PWMCR

13 PWM0CSR

14 PWM1CSR

15 PWM2CSR

16 PWM3CSR

17 DCR0H

18 DCR0L

19 DCR1H

20 ATICRL

21 ATCSR2

22 BREAKCR

23 ATR2H

24 ATR2L

25 DTGR

26 BREAKEN

Reset Value 0 0 0 0 0 0 BREN2 BREN1 Address (Hex.) Register Label 765 4 3 2 1 0

11.3 LITE TIMER 2 (LT2)

11.3.1 Introduction

bit upcounters and an 8-bit input capture register.

11.3.2 Main Features

Figure 51. Lite Timer 2 Block Diagram

11.3.3 Functional Description

11.3.3.1 Timebase Counter 1

riod between two counter overflow events is 1 ms. software reading the LTCSR1 register.

11.3.3.2 Input Capture

bit is cleared by reading the LTICR register. capture is inhibited if the ICF bit is set.

11.3.3.3 Timebase Counter 2

rupt request is generated if the TB2IE bit is set. Figure 52. Input Capture Timing Diagram. 04h8-bit COUNTER 1

LITE TIMER (Cont’d)

11.3.4 Low Power Modes

11.3.5 Interrupts

Note: The TBxF and ICF interrupt events are con- nected to separate interrupt vectors (see Inter- rupts chapter). They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction).

11.3.6 Register Description

LITE TIMER CONTROL/STATUS REGISTER 2 (LTCSR2) Read / Write Reset Value: 0000 0000 (00h) Bits 7:2 = Reserved, must be kept cleared. Bit 1 = TB2IE Timebase 2 Interrupt enable This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled Bit 0 = TB2F Timebase 2 Interrupt Flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred LITE TIMER AUTO RELOAD REGISTER (LTARR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:0 = AR[7:0] Counter 2 Reload Value These bits register is read/write by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. LITE TIMER COUNTER 2 (LTCNTR) Read only Reset Value: 0000 0000 (00h) Bits 7:0 = CNT[7:0] Counter 2 Reload Value This register is read by software. The LTARR val- ue is automatically loaded into Counter 2 (LTCN- TR) when an overflow occurs. LITE TIMER CONTROL/STATUS REGISTER (LTCSR1) Read / Write Reset Value: 0x00 0000 (x0h) Bit 7 = ICIE Interrupt Enable This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Mode Description SLOW No effect on Lite timer (this peripheral is driven directly by f OSC/32) WAIT No effect on Lite timer ACTIVE HALT No effect on Lite timer HALT Lite timer stops counting Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Active Halt Exit from Halt Timebase 1 Event TB1F TB1IE Yes Yes NoTimebase 2 Event TB2F TB2IE No IC Event ICF ICIE No

000000 T B 2 I E T B 2 F

A R 7A R 6A R 5A R 4A R 3A R 2A R 1A R 0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 ICIE ICF TB TB1IE TB1F - - -

LITE TIMER (Cont’d) Bit 6 = ICF Input Capture Flag This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Note: After an MCU reset, software must initialize the ICF bit by reading the LTICR register Bit 5 = TB Timebase period selection This bit is set and cleared by software. 0: Timebase period = t OSC * 8000 (1ms @ 8 MHz) 1: Timebase period = tOSC * 16000 (2ms @ 8 MHz) Bit 4 = TB1IE Timebase Interrupt enable This bit is set and cleared by software. 0: Timebase (TB1) interrupt disabled 1: Timebase (TB1) interrupt enabled Bit 3 = TB1F Timebase Interrupt Flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No counter overflow 1: A counter overflow has occurred Bits 2:0 = Reserved LITE TIMER INPUT CAPTURE REGISTER (LTICR) Read only Reset Value: 0000 0000 (00h) Bits 7:0 = ICR[7:0] Input Capture Value These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin. ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

Table 15. Lite Timer Register Map and Reset Values

08 LTCSR2

09 LTARR

ON-CHIP PERIPHERALS (cont’d)

11.4 SERIAL PERIPHERAL INTERFACE (SPI)

11.4.1 Introduction

The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves.

11.4.2 Main Features

■ Full duplex synchronous transfers (on three lines) ■ Simplex synchronous transfers (on two lines) ■ Master or slave operation ■ 6 master mode frequencies (fCPU/4 max.) ■ fCPU/2 max. slave mode frequency (see note) ■ SS Management by software or hardware ■ Programmable clock polarity and phase ■ End of transfer interrupt flag ■ Write collision, Master Mode Fault and Overrun flags Note: In slave mode, continuous transmission is not possible at maximum frequency due to the software overhead for clearing status flags and to initiate the next transmission sequence.

11.4.3 General Description

Figure 1 on page 3 shows the serial peripheral in- terface (SPI) block diagram. There are three regis- ters: – SPI Control Register (SPICR) – SPI Control/Status Register (SPICSR) – SPI Data Register (SPIDR) The SPI is connected to external devices through four pins: – MISO: Master In / Slave Out data – MOSI: Master Out / Slave In data – SCK: Serial Clock out by SPI masters and in- put by SPI slaves –S S : Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves indi- vidually and to avoid contention on the data lines. Slave SS inputs can be driven by stand- ard I/O ports on the master Device.

Figure 53. Serial Peripheral Interface Block Diagram

11.4.3.1 Functional Description

slave (most significant bit first). the master device via the SCK pin). simplex communication is possible). Figure 54. Single Master/ Single Slave Application

11.4.3.2 Slave Select Management

shift register (see Section 0.1.5.3). Figure 55. Generic SS Timing Diagram Figure 56. Hardware/Software Slave Select Management

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.3.3 Master Mode Operation

In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0). How to operate the SPI in master mode To operate the SPI in master mode, perform the following steps in order: 1. Write to the SPICR register: – Select the clock frequency by configuring the SPR[2:0] bits. – Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 5 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: – Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: – Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high). Important note: if the SPICSR register is not writ- ten first, the SPICR register setting (MSTR bit) may be not taken into account. The transmit sequence begins when software writes a byte in the SPIDR register.

11.4.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most sig- nificant bit first. When data transfer is complete: – The SPIF bit is set by hardware. – An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register Note: While the SPIF bit is se t, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read.

11.4.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the fol- lowing actions: – Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 5). Note: The slave must have the same CPOL and CPHA settings as the master. – Manage the SS pin as described in Section 0.1.3.2 and Figure 3. If CPHA = 1 SS must be held low continuously. If CPHA = 0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions.

11.4.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most sig- nificant bit first. The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. When data transfer is complete: – The SPIF bit is set by hardware. – An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICS R register while the SPIF bit is set 2. A write or a read to the SPIDR register Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 0.1.5.2).

11.4.4 Clock Phase and Clock Polarity

master and the slave device. Figure 57. Data Clock Timing Diagram Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

11.4.5 Error Flags

11.4.5.1 Master Mode Fault (MODF)

vice’s SS pin is pulled low. quest is generated if the SPIE bit is set.

1. A read access to the SPICSR register while the
2. A write to the SPICR register.

inal state during or after this clearing sequence. the MODF bit clearing sequence. slave mode with the MODF bit set.

11.4.5.2 Overrun Condition (OVR)

generated if the SPIE bit is set.

11.4.5.3 Write Collision Error (WCOL)

the software write will be unsuccessful. is set (the WCOL bit is a status flag only). Figure 58. Clearing the WCOL Bit (Write Collision Flag) Software Sequence

11.4.5.4 Single Master and Multimaster

that time, thus disabling the slave devices. through the serial peripheral interface system. Figure 59. Single Master / Multiple Slave Configuration

SERIAL PERIPHERAL INTERFACE (cont’d)

11.4.6 Low Power Modes

11.4.6.1 Using the SPI to wake up the device

In slave configuration, the SPI is able to wake up the device from HALT mode through a SPIF inter- rupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from HALT mode, if the SPI remains in Slave mode, it is recommended to perform an extra communications cycle to bring the SPI from HALT mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake up the device from HALT mode only if the Slave Select signal (exter- nal SS pin or the SSI bit in the SPICSR register) is low when the device enters HALT mode. So, if Slave selection is configured as external (see Sec- tion 0.1.3.2 ), make sure the master drives a low level on the SS pin when the slave enters HALT mode.

11.4.7 Interrupts

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ation resumes when the device is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the soft- ware is running (interrupt vector fetching). If several data are received before the wake- up event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Transfer Event SPIF SPIE Yes Yes Master Mode Fault Event MODF No Overrun Error OVR

11.4.8 Register Description

This bit is set and cleared by software. Note: This bit has no effect in slave mode. tions of the MISO and MOSI pins are reversed. This bit is set and cleared by software. CPHA settings as the master. Note: These 2 bits have no effect in slave mode. Table 16. SPI Master Mode SCK Frequency

SERIAL PERIPHERAL INTERFACE (cont’d) SPI CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only) This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the device and an exter- nal device has been completed. Note: While the SPIF bit is se t, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read. Bit 6 = WCOL Write Collision status (Read only) This bit is set by hardware when a write to the SPIDR register is done during a transmit se- quence. It is cleared by a software sequence (see Figure 6). 0: No write collision occurred 1: A write collision has been detected Bit 5 = OVR SPI Overrun error (Read only) This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 0.1.5.2). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Bit 4 = MODF Mode Fault flag (Read only) This bit is set by hardware when the SS pin is pulled low in master mode (see Section 0.1.5.1 Master Mode Fault (MODF)). An SPI interrupt can be generated if SPIE = 1 in the SPICR register. This bit is cleared by a software sequence (An ac- cess to the SPICSR register while MODF = 1 fol- lowed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bit 3 = Reserved, must be kept cleared. Bit 2 = SOD SPI Output Disable This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE = 1) 1: SPI output disabled Bit 1 = SSM SS Management This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section 0.1.3.2 Slave Select Management. 0: Hardware management (SS managed by exter- nal pin) 1: Software management (internal SS signal con- trolled by SSI bit. External SS pin free for gener- al-purpose I/O) Bit 0 = SSI SS Internal Mode This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the SS slave select signal when the SSM bit is set. 0: Slave selected 1: Slave deselected SPI DATA I/O REGISTER (SPIDR) Read/Write Reset Value: Undefined The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will init iate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value lo- cated in the buffer and not the content of the shift register (see Figure 1). SPIF WCOL OVR MODF - SOD SSM SSI D7 D6 D5 D4 D3 D2 D1 D0

Table 17. SPI Register Map and Reset Values

11.5.1 Introduction

levels from up to 7 different sources. through a Control/Status Register.

11.5.2 Main Features

The block diagram is shown in Figure 60.

11.5.3 Functional Description

11.5.3.1 Analog Power Supply

loaded or badly decoupled power supply lines. Figure 60. ADC Block Diagram

10-BIT A/D CONVERTER (ADC) (Cont’d)

11.5.3.2 Input Voltage Amplifier

The input voltage can be amplified by a factor of 8 by enabling the AMPSEL bit in the ADCDRL regis- ter. When the amplifier is enabled, the input range is 0V to VDD/8. For example, if VDD = 5V, then the ADC can con- vert voltages in the range 0V to 430mV with an ideal resolution of 0.6mV (equivalent to 13-bit res- olution with reference to a V SS to VDD range). For more details, refer to the Electrical character- istics section. Note: The amplifier is switched on by the ADON bit in the ADCCSR register, so no additional start- up time is required when the amplifier is selected by the AMPSEL bit.

11.5.3.3 Digital A/D Conversion Result

The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V AIN) is greater than V DDA (high-level voltage reference) then the conversion result is FFh in the A DCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (low- level voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and AD- CDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section. R AIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time.

11.5.3.4 A/D Conversion

The analog input ports must be configured as in- put, no pull-up, no interrupt. Refer to the «I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the ADCCSR register: – Select the CH[2:0] bits to assign the analog channel to convert. ADC Conversion mode In the ADCCSR register: Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete: – The EOC bit is set by hardware. – The result is in the ADCDR registers. A read to the ADCDRH or a write to any bit of the ADCCSR register resets the EOC bit. To read the 10 bits, perform the following steps: 1. Poll the EOC bit 2. Read ADCDRL 3. Read ADCDRH. This clears EOC automati- cally. To read only 8 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRH. This clears EOC automati- cally.

11.5.3.5 Changing the conversion channel

The application can change channels during con- version. When software modifies the CH[2:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is cleared, and the A/D con- verter starts converting the newly selected chan- nel.

11.5.4 Low Power Modes

Note: The A/D converter may be disabled by re- setting the ADON bit. This feature allows reduced power consumption when no conversion is need- ed and between single shot conversions.

11.5.5 Interrupts

None. Mode Description WAIT No effect on A/D Converter HALT A/D Converter disabled. After wakeup from Halt mode, the A/D Con- verter requires a stabilization time tSTAB (see Electrical Characteristics) before accurate conversions can be performed.

10-BIT A/D CONVERTER (ADC) (Cont’d)

11.5.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by hard- ware when software reads the ADCDRH register or writes to any bit of the ADCCSR register. 0: Conversion is not complete 1: Conversion complete Bit 6 = SPEED ADC clock selection This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit de- scription (ADCDRL register). Bit 5 = ADON A/D Converter on This bit is set and cleared by software. 0: A/D converter and amplifier are switched off 1: A/D converter and amplifier are switched on Bits 4:3 = Reserved. Must be kept cleared. Bits 2:0 = CH[2:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. *The number of channels is device dependent. Refer to the device pinout description. DATA REGISTER HIGH (ADCDRH) Read Only Reset Value: xxxx xxxx (xxh) Bits 7:0 = D[9:2] MSB of Analog Converted Value AMP CONTROL/DATA REGISTER LOW (AD- CDRL) Read/Write Reset Value: 0000 00xx (0xh) Bits 7:5 = Reserved. Forced by hardware to 0. Bit 4 = AMPCAL Amplifier Calibration Bit This bit is set and cleared by software. It is advised to use this bit to calibra te the ADC when amplifier is ON. Setting this bit internally connects amplifier input to 0V. Hence, corresponding ADC output can be used in software to eliminate amplifier-offset er- ror. 0: Calibration off 1: Calibration on. (The input voltage of the amplifi- er is set to 0V) Bit 3 = SLOW Slow mode This bit is set and cleared by software. It is used together with the SPEED bit in the ADCCSR regis- ter to configure the ADC clock speed as shown on the table below. Note: max f ADC allowed = 4MHz (see section 13.11 on page 139) EOC SPEED ADON 0 0 CH2 CH1 CH0 Channel Pin* CH2 CH1 CH0 A I N 0 000 A I N 1 001 A I N 2 010 A I N 3 011 A I N 4 100 A I N 5 101 A I N 6 110 D9 D8 D7 D6 D5 D4 D3 D2

000 AMP

This bit is set and cleared by software. be less than or equal to 2 MHz. Table 18. ADC Register Map and Reset Values

11.6 ANALOG COMPARATOR (CMP)

11.6.1 Introduction

11.6.2 Main Features

11.6.2.1 On-chip Analog Comparator

connected to VP and VN at the comparator input. COMPIN-, the output of the comparator is 1. POUT is shown in Figure 62 on page 101. Table 19. Comparison Result

11.6.2.2 Programmable External/Internal

fixed voltage reference of 1.2V on the VN input.

11.6.3 Functional Description

also connected to ADC channel 0. when the COUT bit in the CMPCR register is set.

0 VP > VN 1

1 VP > VN 0

11.6.4 Register Description

connect it to comparator input VN. Table 20. Voltage Reference Programming Bits 1:0 = Reserved, Must be kept cleared. ence, it is recommended to enable the hysteresis.

this bit does not change the value. (see section 13.12 on page 143). current bias which provides 4µA current to both. to rising or falling edge of interrupt generated. Table 21. Analog Comparator Register Map and Reset Values

12 INSTRUCTION SET

12.1 ST7 ADDRESSING MODES

Table 22. ST7 Addressing Mode Overview

1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.

ST7 ADDRESSING MODES (cont’d)

12.1.1 Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation.

12.1.2 Immediate

Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value.

12.1.3 Direct

In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub- modes: Direct (Short) The address is a byte, thus requires only 1 byte af- ter the opcode, but only allows 00 - FF addressing space. Direct (Long) The address is a word, thus allowing 64 Kbyte ad- dressing space, but requires 2 bytes after the op- code.

12.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three submodes: Indexed (No Offset) There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE addressing space. Indexed (Long) The offset is a word, thus allowing 64 Kbyte ad- dressing space and requires 2 bytes after the op- code.

12.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (point- er). The pointer address follows the opcode. The indi- rect addressing mode consists of two submodes: Indirect (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Subroutine Return IRET Interrupt Subroutine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations

12.1.6 Indirect Indexed (Short, Long)

er address follows the opcode. and requires 1 byte after the opcode. and requires 1 byte after the opcode. Table 23. Instructions Supporting Direct,

12.1.7 Relative Mode (Direct, Indirect)

register value by adding an 8-bit signed offset to it. The offset follows the opcode.

12.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Using a prebyte The instructions are described with 1 to 4 bytes. In order to extend the number of available op- codes for an 8-bit CPU (256 opcodes), three differ- ent prebyte opcodes are defined. These prebytes modify the meaning of the instruction they pre- cede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, di- rect bit or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruc- tion using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

12.2.1 Illegal Opcode Reset

In order to provide enhanced robustness to the de- vice against unexpected behavior, a system of ille- gal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, com- bined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. Note: A valid prebyte associated with a valid op- code forming an unauthorized combination does not generate a reset. Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF

INSTRUCTION GROUPS (cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >

INSTRUCTION GROUPS (cont’d) Mnemo Description Function/Example Dst Src H I N Z C JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2's compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z

13 ELECTRICAL CHARACTERISTICS

13.1 PARAMETER CONDITIONS

13.1.1 Minimum and Maximum values

times the standard deviation (mean±3Σ).

13.1.2 Typical values

as design guidelines and are not tested.

13.1.3 Typical curves

given only as design guidelines and are not tested.

13.1.4 Loading capacitor

measurement are shown in Figure 63. Figure 63. Pin loading conditions

13.1.5 Pin input voltage

vice is described in Figure 64. Figure 64. Pin input voltage

13.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

13.2.1 Voltage Characteristics

13.2.2 Current Characteristics

13.2.3 Thermal Characteristics

Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an uni ntentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if V IN maximum is respected. If V IN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected 3. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. No negative current injection allowed on PB0 pin. 6. When several inputs are submitted to a current injection, the maximum ΣI INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi- mum current injection on four I/O port pins of the device. Symbol Ratings Maximum value Unit VDD - VSS Supply voltage 7.0 V VIN Input voltage on any pin 1) & 2) VSS-0.3 to VDD+0.3 VESD(HBM) Electrostatic discharge voltage (Human Body Model) see section 13.7.3 on page 128 VESD(MM) Electrostatic discharge voltage (Machine Model) Symbol Ratings Maximum value Unit IVDD Total current into VDD power lines (source) 3) 75 mA IVSS Total current out of VSS ground lines (sink) 3) 150 IIO Output current sunk by any standard I/O and control pin 20 Output current sunk by any high sink I/O pin 40 Output current source by any I/Os and control pin - 25 IINJ(PIN) 2) & 4) Injected current on ISPSEL pin ± 5 Injected current on RESET pin ± 5 Injected current on OSC1 and OSC2 pins ± 5 Injected current on PB0 pin 5) +5 Injected current on any other pin 6) ± 5 ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 6) ± 20 Symbol Ratings Value Unit TSTG Storage temperature range -65 to +150 °C TJ Maximum junction temperature (see Table 24, “THERMAL CHARACTERISTICS,” on page 147)

13.3 OPERATING CONDITIONS

13.3.1 General Operating Conditions: Suffix 6 Devices

TA = -40 to +85°C unless otherwise specified.

13.3.2 General Operating Conditions: Suffix 3 Devices

TA = -40 to +125°C unless otherwise specified. Figure 65. fCPU Maximum Operating Frequency Versus VDD Supply Voltage

13.3.3 Operating Conditions with Low Voltage Detector (LVD)

13.3.3.1 Operating Conditions with LVD at TA = -40 to 125°C, unless otherwise specified

Notes: 1. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production. 2. Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur in the application, it is rec- ommended to pull V DD down to 0V to ensure optimum restart conditions. Refer to circuit example in Figure 106 on page 136 and note 4. Symbol Parameter Conditions Min Typ Max Unit VIT+(LVD) Reset release threshold (VDD rise) High Threshold Med. Threshold Low Threshold 3.80 3.20 2.65 4.20 3.55 2.85 4.60 3.90 3.10 V VIT-(LVD) Reset generation threshold (VDD fall) High Threshold Med. Threshold Low Threshold 3.70 3.10 2.50 4.00 3.35 2.70 4.35 3.70 2.90 V hys LVD voltage threshold hysteresis V IT+(LVD)-VIT-(LVD) 200 mV VtPOR VDD rise time rate 1)2) 100 ms/V tg(VDD) Filtered glitch delay on VDD 1) Not detected by the LVD 150 ns IDD(LVD) LVD/AVD current consumption 200 µA

13.3.4 Auxiliary Voltage Detector (AVD) Thresholds

TA = -40 to 125°C, unless otherwise specified

13.3.5 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte). Symbol Parameter Conditions Typ Unit VIT+(AVD) 1=>0 AVDF flag toggle threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.50 4.00 3.35 V V IT-(AVD) 0=>1 AVDF flag toggle threshold (VDD fall) High Threshold Med. Threshold Low Threshold 4.40 3.85 3.20 Vhys AVD voltage threshold hysteresis V IT+(AVD)-VIT-(AVD) 170 mV ΔVIT- Voltage drop between AVD flag set and LVD reset activation VDD fall 0.15 V Symbol Parameter Conditions Min Typ Max Unit VDD(RC) Internal RC Oscillator operating voltage Refer to operating range of VDD with TA, section 13.3.1 on page 112 2.7 5.5 VVDD(x4PLL) x4 PLL operating voltage 2.7 3.7 VDD(x8PLL) x8 PLL operating voltage 3.3 5.5 tSTARTUP PLL Startup time 60 PLL input clock (fPLL) cycles

OPERATING CONDITIONS (Cont’d) The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables.

13.3.5.1 Devices with ‘”6” or “3”order code suffix (tested for TA = -40 to +125°C) @ VDD = 5V

Notes: 1. If the RC oscillator clock is select ed, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. 2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23 3. Data based on characterization results, not tested in production 4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy. 5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 13 on page 24. 6. This period is the phase servo loop period. During this period, the frequency remains unchanged. 7. Guaranteed by design. Symbol Parameter Conditions Min Typ Max Unit fRC Internal RC oscillator fre- quency 1) RCCR = FF (reset value), TA=25°C,VDD=5V 700 kHzRCCR = RCCR02 ),TA=25°C,VDD=5V 992 1000 1008 ACCRC Accuracy of Internal RC oscillator with RCCR=RCCR0 TA=25°C,VDD=5V -0.8 +0.8 % TA=25°C, VDD=4.5 to 5.5V3) -1 +1 % TA=25°C to +85°C,VDD=5V -3 +3 % TA=25°C to +85°C,VDD=4.5 to 5.5V3) -3.5 +3.5 % TA=85°C to +125°C,VDD=5V -3.5 +5 % TA=85°C to +125°C,VDD=4.5 to 5.5V3) -3.5 +6 % TA=-40 to +25°C, VDD=5V3) -3 +7 % IDD(RC) RC oscillator current con- sumption TA=25°C,VDD=5V 600 3) μA tsu(RC) RC oscillator setup time T A=25°C,VDD=5V 10 2) μs fPLL x8 PLL input clock 1 3) MHz tLOCK PLL Lock time5) 2m s tSTAB PLL Stabilization time5) 4m s ACCPLL x8 PLL Accuracy fRC = 1MHz@TA=25°C,VDD=4.5 to 5.5V 0.1 4) % fRC = 1MHz@TA=-40 to +85°C,VDD=5V 0.1 4) % tw(JIT) PLL jitter period 6) fRC = 1MHz 120 µs JITPLL PLL jitter (ΔfCPU/fCPU)1 7) % IDD(PLL) PLL current consumption T A=25°C 600 3) μA

OPERATING CONDITIONS (Cont’d) Notes: 1. If the RC oscillator clock is select ed, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. 2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 23. 3. Data based on characterization results, not tested in production 4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy 5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 13 on page 24. 6. This period is the PLL servoing period. During this period, the frequency remains unchanged. 7. Guaranteed by design. Symbol Parameter Conditions Min Typ Max Unit fRC Internal RC oscillator fre- quency 1) RCCR = FF (reset value), TA=25°C, VDD= 3.3V 700 kHzRCCR=RCCR12) ,TA=25°C,VDD= 3.3V 992 1000 1008 ACCRC Accuracy of Internal RC oscillator when calibrated with RCCR=RCCR12) TA=25°C,VDD=3.3V -0.8 +0.8 % TA=25°C,VDD=3.0 to 3.6V 3) -1 +1 % TA=25 to +85°C,VDD=3.3V -3 +3 % TA=25 to +125°C,VDD=3.0 to 3.6V 3) -5 +6.5 % TA=-40 to +25°C,VDD=3.0 to 3.6V 3) -3.5 +4 % IDD(RC) RC oscillator current con- sumption TA=25°C,VDD=3.3V 400 3) μA tsu(RC) RC oscillator setup time T A=25°C,VDD=3.3V 10 2) μs fPLL x4 PLL input clock 0.7 3) MHz tLOCK PLL Lock time5) 2m s tSTAB PLL Stabilization time5) 4m s ACCPLL x4 PLL Accuracy fRC = 1MHz@TA=25°C, VDD=2.7 to 3.3V 0.1 4) % fRC = 1MHz@TA=40 to +85°C, VDD= 3.3V 0.1 4) % tw(JIT) PLL jitter period 6) fRC = 1MHz 120 µs JITPLL PLL jitter (ΔfCPU/fCPU) 1 7) % IDD(PLL) PLL current consumption T A=25°C 190 3) μA

Figure 70. PLL ΔfCPU/fCPU versus time

1. 32 MHz is guaranteed within this voltage range.

13.3.6 Operating conditions with ADC

TA = -40 to 125°C, unless otherwise specified Note: 1. Current injection (negative or positive) not allowed on any analog pin. Symbol Parameter Typ Unit IINJ(ANA) 1) Injected current on any analog pin 0 mA

13.4 SUPPLY CURRENT CHARACTERISTICS

13.4.1 Supply Current

1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals

in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)

driven by external square wave, LVD disabled.

1. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in i nput mode with a static value at V DD or

VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. SLOW-WAIT mode selected with f CPU based on f OSC divided by 32. All I/O pins in input mode with a static value at

VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,

tested in production at VDD max and fCPU max.

1. All I/O pins in input mode with a static value at V DD or VSS (no load). Data tested in production at VDD max. and fCPU
2. This consumption refers to the Halt period only and not the associated run period which is software dependent.

Figure 71. Typical IDD in RUN vs. fCPU Figure 72. Typical IDD in RUN at fCPU = 8MHz

13.4.2 On-chip peripherals

Notes: 1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer running in PWM mode at fcpu=8MHz. 2. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica- tion (data sent equal to 55h). 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions with am- plifier disabled. Symbol Parameter Conditions Typ Unit IDD(AT) 12-bit Auto-Reload Timer supply current 1) fCPU=4MHz V DD=3.0V 150 μA fCPU=8MHz V DD=5.0V 1000 IDD(SPI) SPI supply current 2) fCPU=4MHz V DD=3.0V 50 fCPU=8MHz V DD=5.0V 200 IDD(ADC) ADC supply current when converting 3) fADC=4MHz VDD=3.0V 250 VDD=5.0V 1100

13.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA.

13.5.1 General Timings

1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles needed to fin-

ish the current instruction execution.

1. Data based on design simulation and/or technology characteristics, not tested in production.

13.5.2 External Clock Source

Figure 78. Typical Application with an External Clock Source

13.5.3 Auto Wakeup from Halt Oscillator (AWU)

Note: 1. Guaranteed by Design. Not tested in production.

13.5.4 Crystal and Ceramic Resonator Oscillators

1. Resonator characteristics given by the ceramic resonator manufacturer. Fo r more information on these resonators,
2. SMD = [-R0: Plastic tape package (∅ =180mm)]
3. () means load capacitor built in resonator

Figure 79. Typical Application with a Crystal or Ceramic Resonator

2 SMD CSTCC2M00G56Z-R0 (47) (47) 0

8 SMD CSTCE8M00G52Z-R0 (10) (10) 0

12 SMD CSTCE12M0G52Z-R0 (10) (10) 0

13.6 MEMORY CHARACTERISTICS

TA = -40°C to 125°C, unless otherwise specified

13.6.1 RAM and Hardware Registers

13.6.2 FLASH Program Memory

13.6.3 EEPROM Data Memory

Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg- isters (only in HALT mode). Guaranteed by construction, not tested in production. 2. Up to 32 bytes can be programmed at a time. 3. The data retention time increases when the TA decreases. 4. Data based on reliability test results and monitored in production. 5. Data based on characterization results, not tested in production. 6. Guaranteed by Design. Not tested in production. Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode 1) HALT mode (or RESET) 1.6 V Symbol Parameter Conditions Min Typ Max Unit VDD Operating voltage for Flash write/erase Refer to operating range of VDD with TA, section 13.3.1 on page 112 2.7 5.5 V tprog Programming time for 1~32 bytes 2) TA=−40 to +125°C 5 10 ms Programming time for 1.5 kBytes TA=+25°C 0.24 0.48 s tRET Data retention 4) TA=+55°C3) 20 years NRW Write erase cycles TA=+25°C 10K cycles IDD Supply current 6) Read / Write / Erase modes fCPU = 8MHz, VDD = 5.5V 2.6 mA No Read/No Write Mode 100 μA Power down mode / HALT 0 0.1 μA Symbol Parameter Conditions Min Typ Max Unit VDD Operating voltage for EEPROM write/erase Refer to operating range of VDD with TA, section 13.3.1 on page 112 2.7 5.5 V tprog Programming time for 1~32 bytes TA=−40 to +125°C 5 10 ms tret Data retention 4) TA=+55°C 3) 20 years NRW Write erase cycles TA=+25°C 300K cycles

13.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba- sis during product characterization.

13.7.1 Functional EMS (Electro Magnetic

Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ■ ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. This test conforms with the IEC 1000-4-2 standard. ■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4- 4 standard. A device reset allows normal operations to be re- sumed. The test results are given in the table be- low based on the EMS levels and classes defined in application note AN1709.

13.7.1.1 Designing hardened software to avoid

EMC characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the manage- ment of runaway conditions such as: – Corrupted program counter – Unexpected reset – Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the RE- SET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be ap- plied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note AN1015).

13.7.2 Electro Magnetic Interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin. Note: 1. Data based on characterization results, not tested in production. Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD=5V, TA=+25°C, fOSC=8MHz conforms to IEC 1000-4-2 2B VFFTB Fast transient voltage burst limits to be applied through 100pF on VDD and VSS pins to induce a func- tional disturbance VDD=5V, TA=+25°C, fOSC=8MHz conforms to IEC 1000-4-4 3B Symbol Parameter Conditions Monitored Frequency Band Max vs. [fOSC/fCPU] Unit 8/4MHz 16/8MHz SEMI Peak level VDD=5V, TA=+25°C, SO20 package, conforming to SAE J 1752/3 0.1MHz to 30MHz 15 21 dBμV30MHz to 130MHz 22 29 130MHz to 1GHz 17 22 SAE EMI Level 3.5 3.5 -

EMC CHARACTERISTICS (Cont’d)

13.7.3 Absolute Maximum Ratings (Electrical

Sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer to the application note AN1181.

13.7.3.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test con- forms to the JESD22-A114A/A115A standard. Absolute Maximum Ratings Note: 1. Data based on characterization results, not tested in production.

13.7.3.2 Static Latch-Up

■ LU: 3 complementary static tests are required on 6 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Electrical Sensitivities Symbol Ratings Conditions Maximum value 1) Unit VESD(HBM) Electro-static discharge voltage (Human Body Model) TA=+25°C 8000 V VESD(MM) Electro-static discharge voltage (Machine Model) TA=+25°C 400 Symbol Parameter Conditions Class LU Static latch-up class TA=+25°C TA=+85°C A A

13.8 I/O PORT PIN CHARACTERISTICS

13.8.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

1. Data based on validation/design results.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
3. The RPU pull-up equivalent resistor is based on a resistive transistor.
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

Figure 80. Two typical Applications with unused I/O Pin (external pull-up of 10k mandatory in This is to avoid entering ICC mode unexpectedly during a reset. noisy environment).

I/O PORT PIN CHARACTERISTICS (Cont’d)

13.8.2 Output Driving Current

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Not tested in production, based on characterization results. Symbol Parameter Conditions Min Max Unit VOL Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 83) VDD=5V IIO=+5mA TA≤125°C 1.0 V IIO=+2mA TA≤125°C 0.4 Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 89) IIO=+20mA,TA≤125°C 1.3 IIO=+8mA TA≤125°C 0.75 VOH Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 95) I IO=-5mA, TA≤125°C VDD-1.5 IIO=-2mA T A≤125°C VDD-0.8 VOL 1)3) Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 82) VDD=3.3V IIO=+2mA TA≤125°C 0.5 Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time IIO=+8mA TA≤125°C 0.5 VOH 2)3) Output high level voltage for an I/O pin when 4 pins are sourced at same time (Figure 94) IIO=-2mA T A≤125°C VDD-0.8 VOL 1)3) Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 87) VDD=2.7V IIO=+2mA TA≤125°C 0.6 Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time IIO=+8mA TA≤125°C 0.6 VOH 2)3) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 101) I IO=-2mA T A≤125°C VDD-0.9

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

TA = -40°C to 125°C, unless otherwise specified Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistiv e transistor. Specified for voltages on RESET pin between VILmax and VDD 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage 1) Vss - 0.3 0.3xVDD VVIH Input high level voltage 1) 0.7xVDD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis 1) 2V VOL Output low level voltage 1)2) VDD=5V IIO=+5mA TA≤85°C 0.5 1.0 VIIO=+2mA TA≤85°C 0.2 0.4 RON Pull-up equivalent resistor 3) VDD=5V 20 40 80 kΩVDD=3V 1) 40 70 120 tw(RSTL)out Generated reset pulse duration Internal reset sources 30 μs th(RSTL)in External reset pulse hold time 4) 20 μs tg(RSTL)in Filtered glitch duration 200 ns

13.10 COMMUNICATION INTERFACE CHARACTERISTICS

13.10.1 SPI - Serial Peripheral Interface

fOSC, and TA unless otherwise specified. Figure 107. SPI Slave Timing Diagram with CPHA=0 3)

1. Data based on design simulation, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. Depends on fCPU. For example, if fCPU=8MHz, then TCPU = 1/fCPU =125ns and tsu(SS)=550ns

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified. Figure 110. Typical Application with ADC

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data

based on characterization results, not tested in production.

1. The stabilization time of the AD c onverter is masked by the first t LOAD. The first conversion after the enable is then

1. Data based on characterization results. Not tested in production.
2. Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being

performed on any analog input. current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins.

1. Data based on characterization results over the whole temperature range, monitored in production.

Figure 111. ADC Accuracy Characteristics with amplifier disabled between the actual and the ideal transfer curves. transition and the first ideal one. transition and the last actual one. between actual steps and the ideal one.

Figure 112. ADC Accuracy Characteristics with amplifier enabled

1. When the AMPSEL bit in the ADCDRL regist er is set, it is mandatory that f ADC be less than or equal to 2 MHz. (if

fCPU=8MHz. then SPEED=0, SLOW=1). between the actual and the ideal transfer curves. transition and the first ideal one. transition and the last actual one. between actual steps and the ideal one.

ADC CHARACTERISTICS (Cont’d) Notes: 1. Data based on characterization results over the whole temperature range, not tested in production. 2. For precise conversion results it is recommended to calibrate the amplifier at the following two points: – offset at VINmin = 0V – gain at full scale (for example VIN=430mV) 3. Monotonicity guaranteed if VIN increases or decreases in steps of min. 5mV. 4. Please refer to the Application Note AN1830 for details of TE% vs Vin. 5. Refer to the offset variation in temperature below Amplifier output offset variation The offset is quite sensitive to temperature varia- tions. In order to ensure a good reliability in meas- urements, the offset must be recalibrated periodi- cally i.e. during power on or whenever the device is reset depending on the customer application and during temperature variation. The table below gives the typical offset variation over temperature: Symbol Parameter Conditions Min Typ Max Unit VDD(AMP) Amplifier operating voltage 3.6 5.5 V VIN Amplifier input voltage4) VDD=3.6V 0 350 mVVDD=5V 0 500 VOFFSET 1) Amplifier output offset voltage5) VDD=5V 200 mV VSTEP 1) Step size for monotonicity3) VDD=3.6V 3.5 mVVDD=5V 4.89 Linearity 1) Output Voltage Response Linear Gain factor 1) Amplified Analog input Gain2) 8 Vmax 1) Output Linearity Max Voltage VINmax = 430mV, VDD=5V 3.65 V Vmin 1) Output Linearity Min Voltage 200 mV Typical Offset Variation (LSB) UNIT -45 -20 +25 +90 °C -12 -7 - +13 LSB

13.12 ANALOG COMPARATOR CHARACTERISTICS

13.13 PROGRAMMABLE INTERNAL VOLTAGE REFERENCE CHARACTERISTICS

13.14 CURRENT BIAS CHARACTERISTICS (for Comparator and Internal Voltage Reference)

Notes: 1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide- lines and are not tested. 2. Since startup time for internal volt age reference and bias is 1 µs, comparat or correct output should not be expected before 1 µs during startup. Symbol Parameter Conditions Min Typ 1) Max Unit VDDA Supply range 4.5 5.5 V VIN Comparator input voltage range 0V DDA V Temp Temperature range -40 125 °C Voffset Comparator offset error 20 mV IDD(CMP) Analog Comparator Consumption 120 µA Analog Comparator Consumption during power-down 200 pA tpropag Comparator propagation delay 40 ns tstartup Startup filter duration 5002) ns tstab Stabilisation time 500 ns Symbol Parameter Conditions Min Typ 1) Max Unit VDDA Supply range 45 5 . 5 V Temp Temperature range -40 27 125 °C IDD(VOLTREF) Internal Voltage Reference Consumption 50 µA Internal Voltage Reference Consumption during power-down 200 pA t startup Startup duration 1 2) µs Symbol Parameter Conditions Min Typ 1) Max Unit VDDA Supply range 4.5 5 5.5 V Temp Temperature range -40 27 125 °C IDD (Bias) Bias Consumption in run mode 50 µA Bias Consumption during power- down 36 pA tstartup Startup time 1 2) µs

14 PACKAGE CHARACTERISTICS

offers these devices in ECOPACK® packages. fications are available at: www.st.com.

14.1 PACKAGE MECHANICAL DATA

Figure 113. 16-Pin Plastic Dual In-Line Package, 300-mil Width and rounded to 3 decimal digits.

Table 24. THERMAL CHARACTERISTICS

1. The maximum chip-junction temperature is based on technology characteristics.
2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA.

chip internal power (IDDxVDD) and PPORT is the port power dissipation depending on the ports used in the application.

14.2 SOLDERING INFORMATION

dering process is the temperature range. Table 25. Soldering Compatibility (wave and reflow soldering process) is compatible with their Lead-free soldering process.

15 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro- grammable versions (FLASH). ST7FLITE1xB devices are shipped to customers with a default program memory content (FFh). This implies that FLASH devices have to be con- figured by the customer using the Option Bytes.

15.1 OPTION BYTES

The two option bytes allow the hardware configu- ration of the microcontroller to be selected. The option bytes can be accessed only in pro- gramming mode (for example using a standard ST7 programming tool). OPTION BYTE 0 OPT7 = Reserved, must always be 1. OPT6 = PKG Package selection 0: 16-pin package 1: 20-pin package OPT5:4 = CLKSEL Clock Source Selection When the internal RC osc illator is not selected (Option OSC=1), these option bits select the clock source: resonator oscillator or external clock Note: When the internal RC oscillator is selected, the CLKSEL option bits must be kept at their de- fault value in order to select the 256 clock cycle delay (see Section 7.5). OPT3:2 = SEC[1:0] Sector 0 size definition These option bits indicate the size of sector 0 ac- cording to the following table. OPT1 = FMP_R Read-out protection Readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first and the device can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and section 4.5 on page 14 for more de- tails 0: Read-out protection off 1: Read-out protection on OPT0 = FMP_W FLASH write protection This option indicates if the FLASH program mem- ory is write protected. Warning: When this option is selected, the pro- gram memory (and the option bit itself) can never be erased or programmed again. 0: Write protection off 1: Write protection on Clock Source Port C CLKSEL Resonator Ext. Osc Disabled/ Port C Enabled 00 Ext. Clock source: CLKIN on PB4 Ext. Osc Enabled/ Port C Disabled on PC0 1 1 Reserved 1 0 Sector 0 Size SEC1 SEC0 0.5k 00 1k 01 2k 10 4k 11 OPTION BYTE 0 OPTION BYTE 1 Res. PKG CLKSEL SEC1 SEC0 FMP R FMP W PLL x4x8 PLL OFF PLL32 OFF OSC LVD1 LVD0 WDG SW WDG HALT Default Value 1111010011 1 01111

OPT7 = PLLx4x8 PLL Factor selection. OPT5 = PLL32OFF 32MHz PLL disable. close as possible to the ST7 device. lected threshold as shown in Table 26. Table 26. LVD Threshold Configuration This option bit selects the watchdog type. Table 27. List of valid option combinations

15.2 DEVICE ORDERING INFORMATION

Figure 118. Ordering information scheme further information on any aspect of this device, please contact the ST Sales Office nearest to you.

ST7LITE1xB FASTROM microcontroller option list *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): Warning: Addresses DEE0h, DEE1h, DEE2h and DEE3h are reserved areas for ST to program RCCR0 and RCCR1 (see section 7.1 on page 23). Conditioning (check only one option, do not specify for DIP package) : Special marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ " Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: 8 char. max _ _ _ _ _ _ _ _ Temperature range: [ ] -40°C to +85°C [ ] -40°C to +125°C Watchdog selection (WDG_SW): [ ] Softwa re activation [ ] Hardware activation Watchdog reset on Halt (WDG_HALT): [ ] Reset [ ] No Reset LVD reset (LVD): [ ] Disabled [ ] Enabled [ ] Highest threshold [ ] Medium threshold [ ] Lowest threshold Sector 0 size (SEC): [ ] 0.5K [ ] 1K [ ] 2K [ ] 4K Readout protection (FMP_R): [ ] Disabled [ ] Enabled Flash write protection (FMP_W): [ ] Disabled [ ] Enabled RC oscillator (OSC) : [ ] Disabled [ ] Enabled Clock source selection (CKSEL): (if OSC disabled) [ ] External crystal / ceramic resonator: [ ] External Clock on PB4 [ ] External Clock on PC0 PLL (PLLOFF): [ ] Disabled [ ] Enabled PLL factor (PLLx4x8): [ ] PLLx4 [ ] PLLx8 PLL32 (PLL32OFF): [ ] Disabled [ ] Enabled Important note : Not all configurations are available. See Table 27 on page 150 for authorized option byte combinations. VFQFPN20: | [ ] ST7PLIT19BF0Ux | [ ] ST7PLIT19BF1Ux | SO20: | [ ] ST7PLIT19BF0Mx | [ ] ST7PLIT19BF1Mx | PDIP20: | [ ] ST7PLIT19BF0Bx | [ ] ST7PLIT19BF1Bx | SO16: | [ ] ST7PLIT19BY0Mx | [ ] ST7PLIT19BY1Mx | PDIP16: | [ ] ST7PLIT19BY0Bx | [ ] ST7PLIT19BY1Bx | VFQFPN [ ] Tape & Reel [ ] Tray SO [ ] Tape & Reel [ ] Tube

15.3 DEVELOPMENT TOOLS

program your microcontrollers.

15.3.1 Starter kits

quickly start developing your application.

15.3.2 Development and debugging tools

grated programming interface.

15.3.3 Programming tools

15.3.4 Order Codes for Development and

15.3.5 Order codes for ST7LITE1xB development tools

Table 28. Development tool order codes for the ST7LITE1xB family

1. Available from ST or from Raisonance, www.raisonance.com
2. Add suffix /EU, /UK or /US for the power supply for your region
3. Includes connection kit for DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection guide
4. Parallel port connection to PC

15.4 ST7 APPLICATION NOTES

Table 29. ST7 Application Notes

16 REVISION HISTORY

Date Revision Main changes 20-Dec-05 1 Initial release on internet 20-July-06 2 Added reset default state in bold for RESET, PC0 and PC1 in Table 1, “Device Pin Descrip- tion,” on page 7 Changed note below Figure 9 on page 17 and the last paragraph of “ACCESS ERROR HAN- DLING” on page 18 Modified note 3 in Table 2, “Hardware Register Map,” on page 10, changed LTICR reset val- ue and replaced h by b for LTCSR1, ATCSR and SICSR reset values Added note to Figure 14 on page 26 Modified caution in section 7.2 on page 23 Added note 2 in “EXTERNAL INTERRUPT CONTROL REGISTER (EICR)” on page 38 and changed “External Interrupt Function” on page 48 Removed references to true open drain in Table 8 on page 50, Table 9 on page 51 and notes Replaced Auto reload timer 3 by Auto reload timer 4 in section 11.2 on page 57 Modified the BA bit description in the BREAKCR register in section 11.2.6 on page 70 graphs before section 11.3.4 on page 81 Modified Section 11.3.3.2 Modified bit names in the description of LTARR and LTCNTR registers in section 11.3.6 on page 81 Added important note in section 11.6.3 on page 100 and added note to CHYST bit descrip- tion in section 11.6.4 on page 102 Modified CINV bit description in section 11.6.4 on page 102 and Figure 62 on page 101 Changed LTCSR2 reset values in Table 2 on page 10 and in section 11.3.6 on page 81 Modified section 13.2.2 on page 111 (I IO values) Modified Section 13.3.1 and section 13.3.2 on page 112 Removed VtPOR min value in section 13.3.3.1 on page 113 Modified section 13.3.4 on page 114 Modified section 13.3.5 on page 114 Modified temperature range in section 13.3.5.3 on page 119 Modified section 13.4.1 on page 121 Added note in section 13.5.3 on page 124 Removed figures “PLLx4 and PLLx8 Output vs CLKIN frequency” Updated section 13.5.4 on page 125 Modified section 13.6 on page 126 Modified Section 13.7.1 and section 13.7.2 on page 127 Modified section 13.10.1 on page 137 (t su(SS), tv(MO) and th(MO)) Modified Figure 108 (CPHA=1) and Figure 109 on page 138 (tv(MO) , th(MO)) Removed empty figure “Typical IPU vs. VDD with VIN=VSS” in section 13.8.1 on page 129 and modified note 3 Modified temperature range in section 13.8.2 on page 130 Modified section 13.9.1 on page 135 Added “related Application notes” in section 13.11 on page 139 Removed EMC protection circuitry in Figure 106 on page 136 (device works correctly without these components) Modified ADC accuracy table in section 13.11 on page 139 Modified temperature range in Section 13.12, Section 13.13 and section 13.14 on page 143 Modified Table 27 on page 150 Added note 3 to E D and EL in Table “ADC Accuracy with VDD=5.0V” on page 140 Modified section 14.2 on page 148 Modified section 15.2 on page 151 (part numbers in QFN20 package) Updated section 15.3 on page 153 15-Sept-06 3 Removed QFN20 pinout and mechanical data. Modified description of CNTR[11:0] bits in section 11.2.6 on page 72 Added “External Clock Source” on page 124 and Figure 78 on page 124 Modified Table 1.

Added QFN20 pinout with new mechanical data (Figure 3 on page 5 and Figure 117 on page 145) Added ST7FLI19BY1M3TR sales type in Table 1, “Supported Flash part numbers,” Modifed “DEVELOPMENT TOOLS” on page 153 23-April-07 5 Added note 1 to Table 1 on page 7 Modified note 1 in section 7.1 on page 23 Added caution to section 7.5.1 on page 28 Modified section 11.2.3.6 on page 67 Modified title of Figure 48 on page 68 and added note 1 Modified Figure 49 on page 69 Modified EOC bit description in section 11.5.6 on page 98 Modified VFFTB parameter in section 13.7.1 on page 127 Modified Table 28 on page 153 17-June-08 6 Modified first page Added note 2 in Table 1, “Device Pin Description,” on page 7 Modified WDGRF bit description in section 7.6.4 on page 35 Modified note 1 in section 11.2.3.6 on page 67 Added section 13.3.6 on page 120 Modified CLKSEL option bits description in section 15.1 on page 149 Modified section 15.2 on page 151 and option list Date Revision Main changes