ST7DALI

ST7DALI STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 141

Technical content

Rev 2.0 ST7DALI 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY , DATA EEPROM, ADC, TIMERS, SPI, DALI ■ Memories – 8 Kbytes single voltage Flash Program mem- ory with read-out protection, In-Circuit Pro- gramming and In-Application programming (ICP and IAP). 10K write/erase cycles guar- anteed, data retention: 20 years at 55°C. – 384 bytes RAM – 256 bytes data EEPROM with read-out pro- tection. 300K write/erase cycles guaranteed, data retention: 20 years at 55°C. ■ Clock, Reset and Supply Management – Enhanced reset system – Enhanced low voltage supervisor (LVD) for main supply and an auxiliary voltage detector (AVD) with interrupt ca pability for implement- ing safe power-down procedures – Clock sources: Internal 1% RC oscillator, crystal/ceramic resonator or external clock – Internal 32-MHz input clock for Auto-reload timer – Optional x4 or x8 PLL for 4 or 8 MHz internal clock – Five Power Saving Modes: Halt, Active-Halt, Wait and Slow, Auto Wake Up From Halt ■ I/O Ports – Up to 15 multifunctional bidirectional I/O lines –7 high sink outputs ■ 4 Timers – Configurable Watchdog Timer – Two 8-bit Lite Timers with prescaler, watch- dog, 1 realtime base and 1 input capture – One 12-bit Auto-reload Timer with 4 PWM outputs, input capture and output compare functions ■ 2 Communication Interfaces – SPI synchronous serial interface – DALI communication interface ■ Interrupt Management – 10 interrupt vectors plus TRAP and RESET – 15 external interrupt lines (on 4 vectors) ■ A/D Converter – 7 input channels – Fixed gain Op-amp – 13-bit resolution for 0 to 430 mV (@ 5V V DD) – 10-bit resolution for 430 mV to 5V (@ 5V VDD) ■ Instruction Set – 8-bit data manipulation – 63 basic instructions with illegal opcode de- tection – 17 main addressing modes – 8 x 8 unsigned multiply instructions ■ Development Tools – Full hardware/software development package – DM (Debug module) Device Summary SO20 300” Features ST7DALI Program memory - bytes 8K RAM (stack) - bytes 384 (128) Data EEPROM - bytes 256 Peripherals Lite Timer with Watchdog, Autoreload Timer with 32-MHz input clock, SPI, 10-bit ADC with Op-Amp, DALI Operating Supply 2.4V to 5.5V CPU Frequency Up to 8Mhz (w/ ext OSC up to 16MHz and int 1MHz RC 1% PLLx8/4MHz) Operating Temperature -40°C to +85°C

To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet Please also pay special attention to the Section “IMPORTANT NOTES” on page 138.

1 INTRODUCTION

plication Programming (IAP) capability. Figure 1. General Block Diagram

2 PIN DESCRIPTION

Figure 2. 20-Pin SO Package Pinout

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state. Table 1. Device Pin Description

3 RESET I/O C T XX Top priority non maskable interrupt (active

4 PB0/AIN0/SS/

injection allowed on this pin.

5 PB1/AIN1/SCK/

injection allowed on this pin.

6 PB2/AIN2/MISO I/O C

7 PB3/AIN3/MOSI/

8 PB4/AIN4/CLKIN I/O C

9 PB5/AIN5 I/O C T X XXX Port B5 ADC Analog Input 5

10 PB6/AIN6/DALIIN I/O C T X XXX Port B6 ADC Analog Input 6 or DALI

CKIN_BK/DAL- IOUT I/O C T HS X ei1 XX Port A7 Backup Clock inputDALI Out- put PA6 /MCO/ ICCCLK CNTRST//BREAK I/O C T X XX Port A6 Main Clock Output or In Circuit Communication Clock Testmode Counter Reset/ or External BREAK Caution: During normal oper- ation this pin must be pulled- up, internally or externally (ex- ternal pull-up of 10k mandato- ry in noisy environment). This is to avoid entering ICC mode unexpectedly during a reset. In the application, even if the pin is configured as output, any reset will put it back in in- put pull-up. PA5 /ATPWM3/ CNTCLK/ ICCDATA/ PLLQ9 I/O C T HS X XX Port A5 Auto-Reload Timer PWM3 or In Circuit Communication Data/Testmode Counter Clock/ PLL Q9 Counter PA4/ JTDI/ PLLQ8/ATPWM2 I/O C T HS X XX Port A4 Serial Test Contoller Input/ PLL Q8 CounterAuto-Reload Timer PWM2 PA3/ JTCK/ PLLLOCKED/ ATPWM1 I/O C T HS X ei0 XX Port A3 Serial Test Contoller Clock/ PLL Locked Serial Test Con- toller Input/ PLL Q8 CounterAuto-Reload Timer PWM1 PA2/ATPWM0/ JTMS/PLLND- WNTST I/O C T HS X XX Port A2 Auto-Reload Timer PWM0/ Serial Test Contoller Mode Select/ PLL down-up counter selec- tion PA1/ JTDO/ PLLADDTST/ ATIC I/O C T HS X XX Port A1 Serial Test Controller Output/ PLL Counter clockAuto-Re- load Timer Input Capture

18 PA0 /LTIC/

T HS X XX Port A0 Lite Timer Input Capture/PLL start test

19 OSC2 O Resonator oscillator inverter output

20 OSC1/CLKIN I Resonator oscillator inverter input or Exter-

No. Pin Name Type Level Port / Control Main Function (after reset) Alternate Function SO20 Input Output Input Output float wpu int ana OD PP

3 REGISTER & MEMORY MAP

dressing 64K bytes of memories and I/O registers. bytes for the stack from 180h to 1FFh. are located in Sector 0 (F000h-FFFFh). Figure 3. Memory Map

128 Bytes Stack

1 Kbyte

7 Kbytes

Table 2. Hardware Register Map

Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the Debug Module registers, see ICC reference manual. 0037h ITC EICR External Interrupt Control Register 00h R/W 0038h MCC MCCSR Main Clock Contro l/Status Register 00h R/W 0039h 003Ah Clock and Reset RCCR SICSR RC oscillator Control Register System Integrity Control/Status Register FFh 0000 0XX0h R/W R/W 003Bh Reserved area (1 byte) 003Ch ITC EISR External Interrupt Selection Register 0Ch R/W 003Dh to 003Fh Reserved area (3 bytes) 0040h 0041h 0042h 0043h 0044h 0045h DALI DCMCLK DCMFA DCMFD DCMBD DCMCR DCMCSR DALI Clock Register DALI Forward Address Register DALI Forward Data Register DALI Backward Data Register DALI Control Register DALI Control/Status Register 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W 0046h to 0048h Reserved area (3 bytes) 0049h 004Ah AWU AWUPR AWUCSR AWU Prescaler Register AWU Control/Status Register FFh 00h R/W R/W 004Bh 004Ch 004Dh 004Eh 004Fh 0050h DM DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W 0051h to 007Fh Reserved area (47 bytes) Address Block Register Label Register Name Reset Status Remarks

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Program- ming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ ICP (In-Circuit Programming) ■ IAP (In-Application Programming) ■ ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM ■ Sector 0 size configurable by option byte ■ Read-out and write protection

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different ways: – Insertion in a programming tool. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be pro- grammed or erased. – In-Circuit Programming. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM (if present) can be programmed or erased without removing the device from the application board. – In-Application Programming. In this mode, sector 1 and data EEPROM (if present) can be programmed or erased without removing the device from the application board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Commu- nication) which allows an ST7 plugged on a print- ed circuit board (PCB) to communicate with an ex- ternal programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communi- cations). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory contain- ing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. – Download ICP Driver code in RAM from the ICCDATA pin – Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc). IAP mode can be used to program any memory ar- eas except Sector 0, which is write/erase protect- ed to allow recovery in case errors occur during the programming operation.

4.4 ICC interface

1. If the ICCCLK or ICCDATA pins are only used
2. During the ICP session, the programming tool

high level (push pull output or pull-up resistor<1K). sistor>1K, no additional components are needed.

1. The use of Pin 7 of the ICC connector depends
2. Pin 9 has to be connected to the OSC1 pin of
3. With the ICP option disabled with ST7 MDT10-

Figure 4. Typical ICC Interface

FLASH PROGRAM MEMORY (Cont’d)

4.5 Memory Protection

There are two different types of memory protec- tion: Read Out Protection and Write/Erase Protec- tion which can be applied individually.

4.5.1 Read out Protection

Readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. Both program and data E 2 memory are protected. In flash devices, this protection is removed by re- programming the option. In this case, both pro- gram and data E 2 memory are automatically erased and the device can be reprogrammed. Read-out protection selection depends on the de- vice type: – In Flash devices it is enabled and removed through the FMP_R bit in the option byte. – In ROM devices it is enabled by mask option specified in the Option List.

4.5.2 Flash Write/Erase Protection

Write/erase protection, when set, makes it impos- sible to both overwrite and erase program memo- ry. It does not apply to E 2 data. Its purpose is to provide advanced security to applications and pre- vent any change being made to the memory con- tent. Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte.

4.6 Related Documentation

For details on Flash programming and ICC proto- col, refer to the ST7 Flash Programming Refer- ence Manual and to the ST7 ICC Protocol Refer- ence Manual

4.7 Register Description

FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing op- erations. When an EPB or anothe r programming tool is used (in socket or ICP mode), the RASS keys are sent automatically.

00000 O P T L A T P G M

5 DATA EEPROM

5.1 INTRODUCTION

basic access protocol described in this chapter.

5.2 MAIN FEATURES

Figure 5. EEPROM Block Diagram

0 E2LAT00 0 0 0 E2PGM

5.3 MEMORY ACCESS

put on the data bus in less than 1 CPU clock cycle. set by software (the E2PGM bit remains cleared). Significant Bits of the address can change. LAT bits are cleared simultaneously. It is not possible to read the latched data. This note is ilustrated by the Figure 8. Figure 6. Data EEPROM Programming Flowchart

Figure 7. Data E2PROM Write Operation

5.4 POWER SAVING MODES

function in progress, and data may be corrupted.

5.5 ACCESS ERROR HANDLING

data bus will not be driven. data on the bus will not be latched.

5.6 Data EEPROM Read-out Protection

tion bit (see section 15.1 on page 130). against read-out (including a re-write protection). are protected using the same option bit. Figure 8. Data EEPROM Programming Cycle

5.7 REGISTER DESCRIPTION

Bits 7:2 = Reserved, forced by hardware to 0. Table 3. DATA EEPROM Register Map and Reset Values

000000 E 2 L A T E 2 P G M

6 CENTRAL PROCESSING UNIT

6.1 INTRODUCTION

6.2 MAIN FEATURES

6.3 CPU REGISTERS

temporary storage areas for data manipulation. (Program Counter High which is the MSB). Figure 9. CPU Registers

CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions. These bits can be individually tested and/or con- trolled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested usin g the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET in- structions and is tested by the JRM and JRNM in- structions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- tions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. 111HINZC

ways pointing to the next free location in the stack. popped from the stack (see Figure 10). mented and the context is pushed on the stack. and the context is popped from the stack. terrupt five locations in the stack area. Figure 10. Stack Manipulation Example

1 SP6 SP5 SP4 SP3 SP2 SP1 SP0

7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a ran ge of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. Main features ■ Clock Management – 1 MHz internal RC oscillator (enabled by op- tion byte) – 1 to 16 MHz or 32kHz External crystal/ceramic resonator (selected by option byte) – External Clock Input (enabled by option byte) – PLL for multiplying the frequency by 8 or 4 (enabled by option byte) – For clock ART counter only: PLL32 for multi- plying the 8 MHz frequency by 4 (enabled by option byte). The 8 MHz input frequency is mandatory and can be obtained in the follow- ing ways: –1 MHz RC + PLLx8 –16 MHz external clock (internally divided by 2) –2 MHz. external clock (internally divided by 2) + PLLx8 –Crystal oscillator with 16 MHz output fre- quency (internally divided by 2) ■ Reset Sequence Manager (RSM) ■ System Integrity Management (SI) – Main supply Low voltage detection (LVD) with reset generation (enabled by option byte) – Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply (en- abled by option byte)

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT

The device contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage range (4.5V-5.5V). It must be calibrat- ed to obtain the frequency required in the applica- tion. This is done by so ftware writing a calibration value in the RCCR (RC Control Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be load- ed in the RCCR. Predefined calibration values are stored in EEPROM for 3 and 5V V DD supply volt- ages at 25°C, as shown in the following table. Note: – See “ELECTRICAL CHARACTERISTICS” on page 100. for more information on the frequency and accuracy of the RC oscillator. – To improve clock stability, it is recommended to place a decoupling capacitor between the VDD and VSS pins. – These two bytes are systematically programmed by ST, including on FASTROM devices. Conse- quently, customers intending to use FASTROM service must not use these two bytes. – RCCR0 and RCCR1 calibration values will be erased if the read-out protection bit is reset after it has been set. See “Read out Protection” on page 14. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the RC frequency using an ex- ternal reference signal.

7.2 PHASE LOCKED LOOP

The PLL can be used to multiply a 1MHz frequen- cy from the RC oscillator or the external clock by 4 or 8 to obtain fOSC of 4 or 8 MHz. The PLL is ena- bled and the multiplication factor of 4 or 8 is select- ed by 2 option bits. – The x4 PLL is intended for operation with VDD in the 2.4V to 3.3V range – The x8 PLL is intended for operation with VDD in the 3.3V to 5.5V range Refer to Section 15.1 for the option byte descrip- tion. If the PLL is disabled and the RC oscillator is ena- bled, then fOSC = 1MHz. If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock. RCCR Conditions ST7DALI Address RCCR0 VDD=5V TA=25°C fRC=1MHz 1000h and FFDEh RCCR1 VDD=3V TA=25°C fRC=700KHz 1001h and FFDFh

Figure 11. PLL Output Frequency Timing

13.3.4 Internal RC Oscillator and PLL)

of the LOCKED bit in the SICSR register.

7.3 REGISTER DESCRIPTION

Bits 7:2 = Reserved, must be kept cleared. and write it to this register at start-up.

000000 MCO SMS

Figure 12. Clock Management Block Diagram

7.4 MULTI-OSCILLATOR (MO)

electrical characteristics section for more details. the OSC1 pin while the OSC2 pin is tied to ground. selected by default as external clock. Table 4. ST7 Clock Sources

7.5 RESET SEQUENCE MANAGER (RSM)

7.5.1 Introduction

ways kept low during the delay phase. dresses FFFEh-FFFFh in the ST7 memory map. Figure 13. RESET Sequence Phases

7.5.2 Asynchronous External RESET pin

output with integrated R ON weak pull-up resistor. Electrical Characteristic section for more details. can enter reset state even in HALT mode. Figure 14. Reset Block Diagram

7.5.3 External Power-On RESET

level specified for the selected fOSC frequency. work connected to the RESET pin.

7.5.4 Internal Low Voltage Detector (LVD)

VDD<VIT- (falling edge) as shown in Figure 15.

7.5.5 Internal Watchdog RESET

Watchdog counter overflow is shown in Figure 15. low during at least tw(RSTL)out. Figure 15. RESET Sequences

7.6 SYSTEM INTEGRITY MANAGEMENT (SI)

fer to section 12.2.1 on page 97 for further details.

7.6.1 Low Voltage Detector (LVD)

The LVD function is illustrated in Figure 16. byte to be low, medium or high. Figure 16. Low Voltage Detector vs Reset

Figure 17. Reset and Supply Management Block Diagram

00 LVDRFLOCKEDWDGRF0

7.6.2 Auxiliary Voltage Detector (AVD)

asitic detection (hysteresis). abled through the option byte.

7.6.2.1 Monitoring the VDD Main Supply

(see section 15.1 on page 130). VIT-(AVD) threshold (AVDF bit is set). Figure 18. Using the AVD to Monitor V

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.3 Low Power Modes

7.6.3.1 Interrupts

The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is re- set (RIM instruction). Mode Description WAIT No effect on SI. AVD interrupts cause the device to exit from Wait mode. HALT The SICSR register is frozen. The AVD remains active. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

7.6.4 Register Description

SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write Reset Value: 0000 0xx0 (0xh) Bit 7:5 = Reserved, must be kept cleared. Bit 4 = WDGRF Watchdog reset flag This bit indicates that the last Reset was generat- ed by the Watchdog peripheral. It is set by hard- ware (watchdog reset) and cleared by software (writing zero) or an LVD Reset (to ensure a stable cleared state of the WDGRF flag when CPU starts). Combined with the LVDRF flag information, the flag description is given by the following table. Bit 3 = LOCKED PLL Locked Flag This bit is set and cleared by hardware. It is set au- tomatically when the PLL reaches its operating fre- quency. 0: PLL not locked 1: PLL locked Bit 2 = LVDRF LVD reset flag This bit indicates that the last Reset was generat- ed by the LVD block. It is set by hardware (LVD re- set) and cleared by software (by reading). When the LVD is disabled by OPTION BYTE, the LVDRF bit value is undefined. Bit 1 = AVDF Voltage Detector flag This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an interrupt request is gen- erated when the AVDF bit is set. Refer to Figure 18 and to Section 7.6.2.1 for additional details. 0: V DD over AVD threshold 1: VDD under AVD threshold Bit 0 = AVDIE Voltage Detector interrupt enable This bit is set and cleared by software. It enables an interrupt to be generated when the AVDF flag is set. The pending interrupt information is automati- cally cleared when software enters the AVD inter- rupt routine. 0: AVD interrupt disabled 1: AVD interrupt enabled Application notes The LVDRF flag is not cleared when another RE- SET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the origi- nal failure. In this case, a watchdog reset can be detected by software while an external reset can not.

000 WDG

RF LOCKED LVDRF AVDF AVDIE RESET Sources LVDRF WDGRF External RESET pin 0 0 Watchdog 0 1 LVD 1 X

8 INTERRUPTS

The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 19. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: – Normal processing is suspended at the end of the current instruction execution. – The PC, X, A and CC registers are saved onto the stack. – The I bit of the CC register is set to prevent addi- tional interrupts. – The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector address- es). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be inter- rupted because the I bit is set by hardware enter- ing in interrupt routine. In the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the Interrupt Map- ping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifi- cally mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT“ column in th e Interrupt Mapping Ta- ble).

8.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc- tion is executed regardless of the state of the I bit. It will be serviced acco rding to the flowchart on Figure 19.

8.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to le ave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt tr iggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the Mis- cellaneous or Interrupt register (if available) ap- plies to the ei source.

8.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: – The I bit of the CC register is cleared. – The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status register or – Access to the status register while the flag is set followed by a read or write of an associated reg- ister. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed.

Figure 19. Interrupt Processing Flowchart Table 5. Interrupt Mapping Note 1: This interrupt exits the MCU from “Auto Wake-up from Halt” mode only.

0 AWU Auto Wake Up Interrupt AWUCSR yes 1) FFFAh-FFFBh

5 LITE TIMER LITE TIMER RTC2 interrupt LTCSR2 no FFF0h-FFF1h

6 DALI DALI DCMCSR no FFEEh-FFEFh

7 SI AVD interrupt SICSR

8 AT TIMER

9 AT TIMER Overflow Interrupt ATCSR yes FFE8h-FFE9h

10 LITE TIMER LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h

11 LITE TIMER RTC1 Interrupt LTCSR yes FFE4h-FFE5h

12 SPI SPI Peripheral Interrupts SPICSR yes no FFE2h-FFE3h

13 Not used FFE0h-FFE1h

(Port B0) according to Table 6. (Port B3) according to Table 6. (Port A7) according to Table 6. (Port A0) according to Table 6. bit in the CC register is set. Table 6. Interrupt Sensitivity Bits

INTERRUPTS (Cont’d) Bit 3:2 = ei1[1:0] ei1 pin selection These bits are written by software. They select the Port A I/O pin used for the ei1 external interrupt ac- cording to the table below. External Interrupt I/O pin selection * Reset State Bit 1:0 = ei0[1:0] ei0 pin selection These bits are written by software. They select the Port A I/O pin used for the ei0 external interrupt ac- cording to the table below. External Interrupt I/O pin selection * Reset State Bits 1:0 = Reserved. ei11 ei10 I/O Pin 0 0 PA4 0 1 PA5 1 0 PA6 1 1 PA7* ei01 ei00 I/O Pin 0 0 PA0 * 0 1 PA1 1 0 PA2 1 1 PA3

9 POWER SAVING MODES

9.1 INTRODUCTION

Figure 20. Power Saving Mode Transitions

9.2 SLOW MODE

the available supply voltage.

1. The CPU and peripherals are clocked at this

Figure 21. SLOW Mode Clock Transition

9.3 WAIT MODE

sumption mode by stopping the CPU. the interrupt or Reset service routine. or an Interrupt occurs, causing it to wake up. Figure 22. WAIT Mode Flow-chart

1. Before servicing an interrupt, the CC register is

256 OR 4096 CPU CLOCK

9.4 HALT MODE

cluding the operation of the on-chip peripherals. tion 15.1 on page 130 for more details). Figure 23. HALT Timing Overview Figure 24. HALT Mode Flow-chart

1. WDGHALT is an option bit. See option byte sec-
2. Peripheral clocked with an external clock source
3. Only some specific interrupts can exit the MCU

fer to Table 5 Interrupt Mapping for more details.

1. Before servicing an interrupt, the CC register is
2. If the PLL is enabled by option byte, it outputs

POWER SAVING MODES (Cont’d)

9.4.1 Halt Mode Recommendations

– Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. – For the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. – The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memo- ry. For example, avoid defining a constant in pro- gram memory with the value 0x8E. – As the HALT instruction clears the interrupt mask in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits be- fore executing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corre- sponding to the wake-up event (reset or external interrupt).

9.5 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power con- sumption mode of the MCU with a real time clock available. It is entered by executing the ‘HALT’ in- struction. The decision to enter either in ACTIVE- HALT or HALT mode is given by the LTCSR/ATC- SR register status as shown in the following table: The MCU can exit ACTIVE-HALT mode on recep- tion of a specific interrupt (see Table 5, “Interrupt Mapping,” on page 35) or a RESET. – When exiting ACTIVE-HALT mode by means of a RESET, a 256 or 4096 CPU cycle delay oc- curs. After the start up delay, the CPU resumes operation by fetching the reset vector which woke it up (see Figure 26). – When exiting ACTIVE-HALT mode by means of an interrupt, the CPU immediately resumes oper- ation by servicing the interrupt vector which woke it up (see Figure 26). When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately (see Note 3). In ACTIVE-HALT mode, on ly the main oscillator and the selected timer counter (LT/AT) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as ex- ternal or auxiliary oscillator). Note: As soon as ACTIVE-HALT is enabled, exe- cuting a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power saving mode. LTCSR1 TB1IE bit ATCSR OVFIE bit ATCSR CK1 bit ATCSR CK0 bit Meaning 0x x 0 ACTIVE-HALT mode disabled00 x x 1 xxx ACTIVE-HALT mode enabledx 101

Figure 25. ACTIVE-HALT Timing Overview Figure 26. ACTIVE-HALT Mode Flow-chart

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

1. Peripherals clocked with an external clock
2. Only the RTC1 interrupt and some specific inter-

rupts can exit the MCU from ACTIVE-HALT mode.

1. Before servicing an interrupt, the CC register is

9.6 AUTO WAKE UP FROM HALT MODE

curate realtime clock available. Figure 27. AWUFH Mode Block Diagram software reading the AWUCSR register.

set (see Section 9.4 HALT MODE). cluding the operation of the on-chip peripherals. lator like the AWU oscillator). Figure 28. AWUF Halt Timing Diagram

Figure 29. AWUFH Mode Flow-chart Notes:

1. WDGHALT is an option bit. See option byte sec-
2. Peripheral clocked with an external clock source
3. Only an AWUFH interrupt and some specific in-

Mapping,” on page 35 for more details.

1. Before servicing an interrupt, the CC register is
2. If the PLL is enabled by option byte, it outputs

9.6.0.1 Register Description

viding the right value in the AWUPRE register. before waking up automatically. Table 7. AWU Register Map and Reset Values

00000 AWU

10 I/O PORTS

10.1 INTRODUCTION

The I/O ports allow data transfer. An I/O port can contain up to 8 pins. Each pin can be programmed independently either as a digital input or digital output. In addition, specific pins may have several other functions. These functions can include exter- nal interrupt, alternate signal input/output for on- chip peripherals or analog input.

10.2 FUNCTIONAL DESCRIPTION

A Data Register (DR) and a Data Direction Regis- ter (DDR) are always associated with each port. The Option Register (OR), which allows input/out- put options, may or may not be implemented. The following description take s into account the OR register. Refer to the Port Configuration table for device specific information. An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers: bit x corre- sponding to pin x of the port. Figure 30 shows the generic I/O block diagram.

10.2.1 Input Modes

Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital value from that I/O pin. If an OR bit is available, different input modes can be configured by software: floating or pull-up. Re- fer to I/O Port Implementation section for configu- ration. Notes: 1. Writing to the DR modifies the latch value but does not change the state of the input pin. 2. Do not use read/mod ify/write instructions (BSET/BRES) to modify the DR register. External Interrupt Function Depending on the device, setting the ORx bit while in input mode can configure an I/O as an input with interrupt. In this configuration, a signal edge or lev- el input on the I/O generates an interrupt request via the corresponding interrupt vector (eix). Falling or rising edge sensitivity is programmed in- dependently for each interrupt vector. The Exter- nal Interrupt Control Register (EICR) or the Miscel- laneous Register controls this sensitivity, depend- ing on the device. External interrupts are hardware interrupts. Fetch- ing the corresponding interrupt vector automatical- ly clears the request latch. Modifying the sensitivity bits will clear any pending interrupts.

10.2.2 Output Modes

Setting the DDRx bit selects output mode. Writing to the DR bits applies a digital value to the I/O through the latch. Reading the DR bits returns the previously stored value. If an OR bit is available, different output modes can be selected by software: push-pull or open- drain. Refer to I/O Port Implementation section for configuration. DR Value and Output Pin Status

10.2.3 Alternate Functions

Many ST7s I/Os have one or more alternate func- tions. These may include output signals from, or input signals to, on-chip peripherals. The Device Pin Description table describes which peripheral signals can be input/output to which ports. A signal coming from an on-chip peripheral can be output on an I/O. To do this, enable the on-chip peripheral as an output (enable bit in the peripher- al’s control register). The peripheral configures the I/O as an output and takes priority over standard I/ O programming. The I/O’s state is readable by ad- dressing the corresponding I/O data register. Configuring an I/O as floating enables alternate function input. It is not recommended to configure an I/O as pull-up as this will increase current con- sumption. Before using an I/O as an alternate in- put, configure it without interrupt. Otherwise spuri- ous interrupts can occur. Configure an I/O as input floating for an on-chip peripheral signal which can be input and output. Caution: I/Os which can be configured as both an analog and digital alternate function need special atten- tion. The user must control the peripherals so that the signals do not arrive at the same time on the same pin. If an external clock is used, only the clock alternate function should be employed on that I/O pin and not the other alternate function. DR Push-Pull Open-Drain 0V OL VOL 1V OH Floating

Figure 30. I/O Port General Block Diagram Table 8. I/O Port Mode Options vice against positive stress. table for device specific information.

Table 9. I/O Configurations

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

1. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

1. For true open drain, these elements are not implemented.

rail, connected to the ADC input.

10.3 I/O PORT IMPLEMENTATION

spurious interrupt generation. Figure 31. Interrupt I/O Port State Transitions

10.4 UNUSED I/O PINS

age levels. Refer to Section 13.8.

10.5 LOW POWER MODES

10.6 INTERRUPTS

register is cleared (RIM instruction). cause the device to exit from WAIT mode. cause the device to exit from HALT mode.

10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION

Table 10. Port Configuration (Standard ports) Table 11. I/O Port Register Map and Reset Values

11 ON-CHIP PERIPHERALS

11.1 WATCHDOG TIMER (WDG)

11.1.1 Introduction

11.1.2 Main Features

11.1.3 Functional Description

programmed by the user in 64 increments. Figure 32. Watchdog Block Diagram

WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. This downcounter is free- running: it counts down even if the watchdog is disabled. The value to be stored in the CR register must be between FFh and C0h (see Table 12 .Watchdog Timing): – The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme- diate reset – The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software re- set (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset. Table 12.Watchdog Timing Notes: 1. The timing variation shown in Table 12 is due to the unknown status of the prescaler when writing to the CR register. 2. The number of CPU clock cycles applied during the RESET phase (256 or 4096) must be taken into account in addition to these timings.

11.1.4 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the Option Byte description in section 15 on page 130.

11.1.4.1 Using Halt Mode with the WDG

(WDGHALT option) If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruc- tion to refresh the WDG counter, to avoid an unex- pected WDG reset immediately after waking up the microcontroller. Same behavior in active-halt mode. fCPU = 8MHz WDG Counter Code min [ms] max [ms] C0h 1 2 FFh 127 128

WATCHDOG TIMER (Cont’d)

11.1.5 Interrupts

None.

11.1.6 Register Description

CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh) Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watch- dog option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). WDGA T6 T5 T4 T3 T2 T1 T0

Table 13. Watchdog Timer Register Map and Reset Values

11.2.1 Introduction

11.2.2 Main Features

Figure 33. Block Diagram

32 MHz

4 PWM Channels

11.2.3 Functional Description

mum value is 1 KHz (ATR register value = 0). At reset, the counter starts counting from 0. be greater than the contents of the ATR register. Figure 34. PWM Inversion Diagram Figure 35. PWM Function

Figure 36. PWM Signal from 0% to 100% Duty Cycle ble for DCRx values other than 0 (reset value). cy shutdown of the power converter. function without using the BREAK pin. – The 12-bit PWM counter is set to its reset value. registers are set to their reset values. – The PWMCR register is reset.

Figure 37. Block Diagram of Break Function

11.2.3.1 Input Capture

ing or falling edge is detected on the ATIC pin. Figure 38. Input Capture Timing Diagram The BREAK pin value is latched by the BA bit.

12-BIT AUTORELOAD TIMER (Cont’d)

11.2.4 Low Power Modes

11.2.5 Interrupts

Note 1: The CMP and IC events are connected to the same interrupt vector. The OVF event is mapped on a separate vector (see Interrupts chapter). They generate an interrupt if the enable bit is set in the ATCSR register and the interrupt mask in the CC register is reset (RIM instruction). Note 2: Only if CK0=1 and CK1=0 (f COUNTER = fLTIMER) Mode Description SLOW The input frequency is divided by 32 WAIT No effect on AT timer ACTIVE-HALT AT timer halted except if CK0=1, CK1=0 and OVFIE=1 HALT AT timer halted Interrupt Event1) Event Flag Enable Control Bit Exit from Wait Exit from Halt Exit from Active- Halt Overflow Event OVF OVIE Yes No Yes 2) IC Event ICF ICIE Yes No No CMP Event CMPF0 CMPIE Yes No No

12-BIT AUTORELOAD TIMER (Cont’d)

11.2.6 Register Description

TIMER CONTROL STATUS REGISTER (ATCSR) Read / Write Reset Value: 0x00 0000 (x0h) Bit 7 = Reserved. Bit 6 = ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the ATICR register (a read access to ATICRH or ATICRL will clear this flag). Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Bit 5 = ICIE IC Interrupt Enable. This bit is set and cleared by software. 0: Input capture interrupt disabled 1: Input capture interrupt enabled Bits 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter. Note 1: PWM mode and Output Compare modes are not available at this frequency. Note 2: ATICR counter may return inaccurate re- sults when read. It is therefore not recommended to use Input Capture mode at this frequency. Bit 2 = OVF Overflow Flag. This bit is set by hardware and cleared by software by reading the TCSR register. It indicates the tran- sition of the counter from FFFh to ATR value. 0: No counter overflow occurred 1: Counter overflow occurred Bit 1 = OVFIE Overflow Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. 0: OVF interrupt disabled. 1: OVF interrupt enabled. Bit 0 = CMPIE Compare Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. It can be used to mask the interrupt generated when the CMPF bit is set. 0: CMPF interrupt disabled. 1: CMPF interrupt enabled. COUNTER REGISTER HIGH (CNTRH) Read only Reset Value: 0000 0000 (000h) COUNTER REGISTER LOW (CNTRL) Read only Reset Value: 0000 0000 (000h) Bits 15:12 = Reserved. Bits 11:0 = CNTR[11:0] Counter Value. This 12-bit register is read by software and cleared by hardware after a reset. The counter is incre- mented continuously as soon as a counter clok is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations, LSB first. When a counter over- flow occurs, the counter restarts from the value specified in the ATR register. 76 0

0 ICF ICIE CK1 CK0 OVF OVFIE CMPIE

Counter Clock Selection CK1 CK0 OFF 0 0 fLTIMER (1 ms timebase @ 8 MHz) 1) 01 fCPU 10

32 MHz 2) 11

0000 CNTR

10 CNTR9 CNTR8

CNTR7 CNTR6 CNTR5 CNTR4 CNTR3 CNTR2 CNTR1 CNTR0

12-BIT AUTORELOAD TIMER (Cont’d) AUTORELOAD REGISTER (ATRH) Read / Write Reset Value: 0000 0000 (00h) AUTORELOAD REGISTER (ATRL) Read / Write Reset Value: 0000 0000 (00h) Bits 11:0 = ATR[11:0] Autoreload Register. This is a 12-bit register which is written by soft- ware. The ATR register value is automatically loaded into the upcounter when an overflow oc- curs. The register value is used to set the PWM frequency. PWM OUTPUT CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) Bits 7:0 = OE[3:0] PWMx output enable. These bits are set and cleared by software and cleared by hardware after a reset. 0: PWM mode disabled. PWMx Output Alternate Function disabled (I/O pin free for general pur- pose I/O) 1: PWM mode enabled PWMx CONTROL STATUS REGISTER (PWMxCSR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:2= Reserved, must be kept cleared. Bit 1 = OPx PWMx Output Polarity. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM signal. 0: The PWM signal is not inverted. 1: The PWM signal is inverted. Bit 0 = CMPFx PWMx Compare Flag. This bit is set by hardware and cleared by software by reading the PWMxCSR register. It indicates that the upcounter value matches the DCRx regis- ter value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value. BREAK CONTROL REGISTER (BREAKCR) Read/Write Reset Value: 0000 0000 (00h) Bits 7:6 = Reserved. Forced by hardware to 0. Bit 5 = BA Break Active. This bit is read/write by software, cleared by hard- ware after reset and set by hardware when the BREAK pin is low. It acti vates/deactivates the Break function. 0: Break not active 1: Break active 15 8 0 0 0 0 ATR11 ATR10 ATR9 ATR8 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 0O E 30O E 20O E 10O E 0 76 0

000000 O P x C M P F x

0 0 BA BPEN PWM3 PWM2 PWM1 PWM0

12-BIT AUTORELOAD TIMER (Cont’d) Bit 4 = BPEN Break Pin Enable. This bit is read/write by software and cleared by hardware after Reset. 0: Break pin disabled 1: Break pin enabled Bit 3:0 = PWM[3:0] Break Pattern. These bits are read/write by software and cleared by hardware after a reset. They are used to force the four PWMx output signals into a stable state when the Break function is active. PWMx DUTY CYCLE REGISTER HIGH (DCRxH) Read / Write Reset Value: 0000 0000 (00h) PWMx DUTY CYCLE REGISTER LOW (DCRxL) Read / Write Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved. Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value This 12-bit value is wri tten by software. It defin- esthe duty cycle of the corresponding PWM output signal (see Figure 35). In PWM mode (OEx=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWMx output signal (see Figure 35 ). In Output Compare mode, they define the value to be com- pared with the 12-bit upcounter value. INPUT CAPTURE REGISTER HIGH (ATICRH) Read only Reset Value: 0000 0000 (00h) INPUT CAPTURE REGISTER LOW (ATICRL) Read only Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved. Bits 11:0 = ICR[11:0] Input Capture Data. This is a 12-bit register which is readable by soft- ware and cleared by hardware after a reset. The ATICR register contains captured the value of the 12-bit CNTR register when a rising or falling edge occurs on the ATIC pin. Capture will only be per- formed when the ICF flag is cleared. TRANSFER CONTROL REGISTER (TRANCR) Read/Write Reset Value: 0000 0001 (01h) Bits 7:1 Reserved. Forced by hardware to 0. Bit 0 = TRAN Transfer enable This bit is read/write by software, cleared by hard- ware after each completed transfer and set by hardware after reset. It allows the value of the DCRx registers to be transferred to the DCRx shadow registers after the next overflow event. The OPx bits are transferred to the shadow OPx bits in the same way. 15 8 0 0 0 0 DCR11 DCR10 DCR9 DCR8 DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 15 8 0 0 0 0 ICR11 ICR10 ICR9 ICR8 ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

0000000 T R A N

Table 14. Register Map and Reset Values

10 ATRH

11 ATRL

12 PWMCR

13 PWM0CSR

14 PWM1CSR

15 PWM2CSR

16 PWM3CSR

17 DCR0H

18 DCR0L

19 DCR1H

20 ATICRL

21 TRANCR

22 BREAKCR

(Hex.) Register Label 76543210

11.3 LITE TIMER 2 (LT2)

11.3.1 Introduction

bit upcounters, an 8-bit input capture register.

11.3.2 Main Features

Figure 39. Lite Timer 2 Block Diagram

11.3.3 Functional Description

11.3.3.1 Timebase Counter 1

riod between two counter overflow events is 1 ms. software reading the LTCSR1 register.

11.3.3.2 Timebase Counter 2

rupt request is generated if the TB2IE bit is set.

11.3.3.3 Input Capture

LTICR1 register contains the MSB of Counter 1. ICF bit is cleared by reading the LTICR register. capture is inhibited if the ICF bit is set. Figure 40. Input Capture Timing Diagram.

LITE TIMER (Cont’d) – The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memo- ry. For example, avoid defining a constant in ROM with the value 0x8E. – As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

11.3.4 Low Power Modes

11.3.5 Interrupts

Note: The TBxF and ICF interrupt events are con- nected to separate interrupt vectors (see Inter- rupts chapter). They generate an interrupt if the enable bit is set in the LTCSR1 or LTCSR2 register and the interrupt mask in the CC register is reset (RIM instruction).

11.3.6 Register Description

LITE TIMER CONTROL/STATUS REGISTER 2 (LTCSR2) Read / Write Reset Value: 0x00 0000 (x0h) Bits 7:2 = Reserved, must be kept cleared. Bit 1 = TB2IE Timebase 2 Interrupt enable. This bit is set and cleared by software. 0: Timebase (TB2) interrupt disabled 1: Timebase (TB2) interrupt enabled Bit 0 = TB2F Timebase 2 Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No Counter 2 overflow 1: A Counter 2 overflow has occurred LITE TIMER AUTO RELOAD REGISTER (LTARR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:0 = AR[7:0] Counter 2 Reload Value. These bits register is read/write by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. Mode Description SLOW No effect on Lite timer (this peripheral is driven directly by f OSC/32) WAIT No effect on Lite timer ACTIVE-HALT No effect on Lite timer HALT Lite timer stops counting Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Active Halt Exit from Halt Timebase 1 Event TB1F TB1IE Yes Yes No Timebase 2 Event TB2F TB2IE Yes No No IC Event ICF ICIE Yes No No

000000 T B 2 I E T B 2 F

AR7 AR7 AR7 AR7 AR3 AR2 AR1 AR0

LITE TIMER (Cont’d) LITE TIMER COUNTER 2 (LTCNTR) Read only Reset Value: 0000 0000 (00h) Bits 7:0 = CNT[7:0] Counter 2 Reload Value. This register is read by software. The LTARR val- ue is automatically loaded into Counter 2 (LTCN- TR) when an overflow occurs. LITE TIMER CONTROL/STATUS REGISTER (LTCSR1) Read / Write Reset Value: 0x00 0000 (x0h) Bit 7 = ICIE Interrupt Enable. This bit is set and cleared by software. 0: Input Capture (IC) interrupt disabled 1: Input Capture (IC) interrupt enabled Bit 6 = ICF Input Capture Flag. This bit is set by hardware and cleared by software by reading the LTICR register. Writing to this bit does not change the bit value. 0: No input capture 1: An input capture has occurred Note: After an MCU reset, software must initialise the ICF bit by reading the LTICR register Bit 5 = TB Timebase period selection. This bit is set and cleared by software. 0: Timebase period = t OSC * 8000 (1ms @ 8 MHz) 1: Timebase period = tOSC * 16000 (2ms @ 8 MHz) Bit 4 = TB1IE Timebase Interrupt enable. This bit is set and cleared by software. 0: Timebase (TB1) interrupt disabled 1: Timebase (TB1) interrupt enabled Bit 3 = TB1F Timebase Interrupt Flag. This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect. 0: No counter overflow 1: A counter overflow has occurred Bits 2:0 = Reserved LITE TIMER INPUT CAPTURE REGISTER (LTICR) Read only Reset Value: 0000 0000 (00h) Bits 7:0 = ICR[7:0] Input Capture Value These bits are read by software and cleared by hardware after a reset. If the ICF bit in the LTCSR is cleared, the value of the 8-bit up-counter will be captured when a rising or falling edge occurs on the LTIC pin. CNT7 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0 ICIE ICF TB TB1IE TB1F - - - ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0

Table 15. Lite Timer Register Map and Reset Values

08 LTCSR2

09 LTARR

11.4 DALI COMMUNICATION MODULE

11.4.1 Introduction

cations standard (IEC standard).

11.4.2 Main Features

Figure 41. Dali Communication Module Block Diagram except when in Halt mode or if the DCME bit = 0.

11.4.3 DALI Standard Protocol

phase bit period is 833.33 us ±10%. bits do not contain any change of phase. frames is 9.17 ms (minimum). this is interpreted as "no answer". In the event of code violation, the frame is ignored. ready again for data reception. Figure 42. DALI Standard Frame

DALI COMMUNICATION MODULE (Cont’d)

11.4.4 General Description

The DCM is able to receive or transmit a serial DALI signal using a 16-bit shift register, an edge detector, several data/control registers and arbi- tration logic. The DCM receives the DALI standard signal from the lighting control network, checks for errors and loads the address/data bytes of a "forward frame" to the corresponding DCMFA/DCMFD registers and sends back the data byte of the "backward frame" (written by software to the DCMBD regis- ter) in DALI standard format. The data rate can be changed by writing in the DC- MCLK register ( f DATA = 2* fDALI). fDATA = fCPU/[(N+1)*16] The DALI standard data rate f DALI is 1.2 kHz. N is the integer value of the DCMCLK register. Follow- ing the above formula, if f CPU is 8 MHz, the integer value of the DCMCLK register is "207". The bi- phase bit period is 833.33 us ±10%. The polarity of the bi-phase start bit is not config- urable. The start bit is a logical ’1’. The polarity of the 2 stop bits is not configurable. The 2 stop bits are set to high level. If an error is detected during reception, the frame will be ignored and the DCM will return to Receive state.

11.4.5 Functional Description

The user must write to the DCMCLK register to se- lect the data rate according to the DALI signal fre- quency. After Reset, the DCM is in Receive state and waits for the bi-phase start bit (logical ’1’) of the "forward frame". The DCM checks the data format of the "forward frame" with the 4-bit pre-shift register. If an error occurs during reception, the DCM will skip the data and return to the Receive state. If there is no error in the "forward frame", the data will be shifted Most Significant Bit-first into the 16- bit shift register. The address byte and the data byte will be loaded to the corresponding DCMFA and DCMFD registers. The DCM will send an in- terrupt signal by setting the ITF bit in the DCMCSR register. If the software receives an interrupt signal from the DCM, it reads the DCMFA and DCMFD registers. Depending on the command, the DCM is able to send back or receive data. In an interrupt routine, the RTS bit has to be set ei- ther before or at the same time as the RTA bit. If the software asks the DCM to send back a "backward frame", the software must first write to the DCMBD register and switch the DCM to Trans- mit state by setting the RTS and RTA bits in the DCMCR register during the interrupt routine. The DCMBD register will be shifted out from the 16-bit shift register in DALI fo rmat, the Most Significant Bit-first. When the "backward frame" has been transmitted, the DCM will send an interrupt signal by setting the ITF bit in the DCMCSR register. If the software asks the DCM to receive a "forward frame", the software must switch the DCM to Re- ceive state by clearing the RTS bit and setting the RTA bit in the DCMCR register during the interrupt routine. If the ITF interrupt flag is set in the DCMCSR reg- ister, the software must set the RTA bit in the DC- MCR register to allow the DCM to perform the next DALI signal reception or transmission. The DALIIN signal is always taken into account by the 4-bit pre-shifter.

DALI COMMUNICATION MODULE (Cont’d)

11.4.6 Special Functions

11.4.6.1 Forced Transmission (Test mode)

The DCM must receive a "forward frame" before sending back a "backward frame". But it is possi- ble to force the DCM into Transmit state by setting the FTS bit in the DCMCR register. The DCMBD register will be shifted out in DALI format, the Most Significant Bit-first. Preferably before forcing the DCM into Transmit state, the user should reset/set the DCME bit in the DCMCR register. An interrupt flag will be generated afte r a forced transmission (the ITF bit in the DCMCSR register). Procedure – Reset the DCME bit in the DCMCR register. – Write the backward value in the DCMBD reg- ister. – Set both the DCME and the FTS bits in the DCMCR register. – When an interrupt is generated (end of trans- mission, the ITF bit is set in the DCMCSR reg- ister), set the RTA bit in the DCMCR register to re-start a transmission. – To return to normal DALI communications, re- set/set the DCME bit and reset the FTS bit in the DCMCR register.

11.4.6.2 Normal Transmission

After the "forward frame" reception, the software must write the backward data byte to the DCMBD register and set both the RTS and RTA bits in the DCMCR register to start the transmission. It is not possible to send a backward frame just af- ter having sent a backward frame (see DALI standard protocol).

11.4.6.3 DCM Enable

The user can enable or disable the DCM by writing the DCME bit in the DCMCR register. This bit is also used to reset the entire internal finite state machine.

11.4.7 DALI Interface Failure

If the DALI input signal is set to low level for a 2-bit period (1.66 ms), then the DCM generates an er- ror flag by setting the EF bit in the DCMCSR regis- ter. This bit can be cleared by reading the DCMC- SR register. The interface failure is detected if the DCM is in Receive state only.

11.4.8 Low Power Modes

11.4.9 Interrupts

HALT DCM registers are frozen ACTIVE HALT No effect on DCM Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt EOT ITF ITE Yes No

11.4.10 Bi-phase Bit Detection

at the 9th sample clock pulse. shifted into the 16-bit shifter. Figure 43. DALI Signal Sampling

Figure 44. Example of DALI Signal Sampling

DALI COMMUNICATION MODULE (Cont’d)

11.4.11 Register Description

DCM DATA RATE CONTROL REGISTER (DCMCLK) Read / Write Reset Value: 0000 0000 (00h) Bits 7:0 = DCMCLK[7:0] Clock Prescaler. These bits are set/cleared by software and cleared by hardware after a reset. These 8 bits are used for tuning the DALI data rate. f DATA = fCPU/[(N+1)*16] where N is the inte- ger value of the DCMCLK register. DCM FORWARD ADDRESS REGISTER (DCMFA) Read only Reset Value: 0000 0000 (00h) Bits 7:0 = DCMFA[7:0] Forward Address. These bits are read by software and set/cleared by hardware. These 8 bits are used to store the "forward frame" address byte. DCM FORWARD DATA REGISTER (DCMFD) Read only Reset Value: 0000 0000 (00h) Bits 7:0 = DCMFD[7:0] Forward Data. These bits are read by software and set/cleared by hardware. These 8 bits are used to store the "forward frame" data byte. DCM BACKWARD DATA REGISTER (DCMBD) Read / Write Reset Value: 0000 0000 (00h) Bits 7:0 = DCMBD[7:0] Backward Data. These bits are set/cleared by software and cleared by hardware after a reset. These 8 bits are used to store the "backward frame" data byte. The sofware writes to this regis- ter before enabling the transmit operation. CK7 CK6 CK5 CK4 CK3 CK2 CK1 CK0 FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0

DALI COMMUNICATION MODULE (cont’d) DCM CONTROL REGISTER (DCMCR) Read / Write Reset Value: 0000 0000 (00h) Bits 7:4 = Reserved. Forced by hardware to 0. Bit 3 = DCME DALI Communication Enable. This bit is set/cleared by software and cleared by hardware after a reset. When set, it enables DALI communication. It also resets the entire internal finite state machine. 0: The DCM is not enable to receive/transmit 1: The DCM is enable to receive/transmit Bit 2 = RTA Receive/Transmit Acknowledge. This bit is reset by hardware after it has been set by software. It is cleared after a reset. This bit must be set, after a first DALI frame recep- tion or transmission, to allow the DCM to perform the next DALI communication. 0: No acknowledge 1: Acknowledge Bit 1 = RTS Receive/Transmit state. This bit is set/cleared by software and cleared by hardware after a reset. This bit must be set to ’1’ after a forward frame is received, if a backward fr ame is required. This bit must be cleared after a backward frame is trans- mitted, if a forward frame is required. 0: The DCM is set to Receive state 1: The DCM is set to Transmit state Bit 0 = FTS Force Transmit state. This bit is set/cleared by software and cleared by hardware after a reset. When this bit is set, the DCM is forced into Trans- mit state. Preferably before forcing the DCM into Transmit state, the user should reset and set the DCME bit in the DCMCR register. An interrupt flag (ITF) is generated after a forced transmission. 0: The DCM is not forced to Transmit state 1: The DCM is forced to Transmit state DCM CONTROL/STATUS REGISTER (DCMCSR) Read only (except for bit 7) Reset Value: 0000 0000 (00h) Bit 7 = ITE Interrupt Enable. This bit is set/cleared by software and cleared by hardware after a reset. When set, this bit allows the generation of DALI in- terrupts. 0: DCM interrupt (ITF) disabled 1: DCM interrupt (ITF) enabled Bit 6 = ITF Interrupt Flag. (Read only) This bit is set/cleared by hardware and read by software. This bit is set after the end of the "backward frame" transmission or the "forward frame" reception. It is cleared by setting the RTA bit in the DCMCR reg- ister. It is set after a forced transmission (see the FTS bit). 0: Not the end of reception/transmission 1: End of reception/transmission Bit 5 = EF Error Flag. (Read only) This bit is set/cleared by hardware. It is cleared by reading the DCMCSR register. This bit is set when either the DALI data format re- ceived is wrong or an interface failure is detected. 0: No data format error during reception 1: Data format error during reception Bit 4 = RTF Receive/Transmit Flag. (Read only) This bit is set/reset by hardware and read by soft- ware. 0: The DCM is in Transmit state 1: The DCM is in Receive state Bits 3:0 = DCMCSR[3:0] Clock counter value. (Read only) These bits are set/cleared by hard- ware and read by software. The value of the 4-bit sample clock counter (inte- ger range 0 to 15). The clock counter value is load- ed in the DCMCSR register when a DALI change of phase signal is detected (edge trigger). Refer to Figure 44. 0 0 0 0 DCME RTA RTS FTS ITE ITF EF RTF CK3 CK2 CK1 CK0

Table 16. Register Map and Reset Values

11.5 SERIAL PERIPHERAL INTERFACE (SPI)

11.5.1 Introduction

which devices may be either masters or slaves.

11.5.2 Main Features

initiate the next transmission sequence.

11.5.3 General Description

ard I/O ports on the master Device. Figure 45. Serial Peripheral Interface Block Diagram

11.5.3.1 Functional Description

slave (most significant bit first). the master device via the SCK pin). simplex communication is possible). must be programmed with the same timing mode. Figure 46. Single Master/ Single Slave Application

11.5.3.2 Slave Select Management

shift register (see Section 11.5.5.3). Figure 47. Generic SS Timing Diagram Figure 48. Hardware/Software Slave Select Management

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.5.3.3 Master Mode Operation

In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). To operate the SPI in master mode, perform the following steps in order (if the SPICSR register is not written first, the SPICR register setting (MSTR bit ) may be not taken into account): 1. Write to the SPICR register: – Select the clock frequency by configuring the SPR[2:0] bits. – Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 49 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: – Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: – Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high. The transmit sequence begins when software writes a byte in the SPIDR register.

11.5.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most sig- nificant bit first. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register. Note: While the SPIF bit is se t, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read.

11.5.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the fol- lowing actions: – Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 49). Note: The slave must have the same CPOL and CPHA settings as the master. – Manage the SS pin as described in Section 11.5.3.2 and Figure 47. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions.

11.5.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most sig- nificant bit first. The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICS R register while the SPIF bit is set. 2. A write or a read to the SPIDR register. Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 11.5.5.2).

11.5.4 Clock Phase and Clock Polarity

master and the slave device. Figure 49. Data Clock Timing Diagram Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

11.5.5 Error Flags

11.5.5.1 Master Mode Fault (MODF)

quest is generated if the SPIE bit is set.

1. A read access to the SPICSR register while the
2. A write to the SPICR register.

inal state during or after this clearing sequence. the MODF bit clearing sequence. slave mode with the MODF bit set.

11.5.5.2 Overrun Condition (OVR)

generated if the SPIE bit is set.

11.5.5.3 Write Collision Error (WCOL)

and the software write will be unsuccessful. is set (the WCOL bit is a status flag only). Figure 50. Clearing the WCOL bit (Write Collision Flag) Software Sequence

11.5.5.4 Single Master and Multimaster

the four SS pins of the slave devices. that time, thus disabling the slave devices. through the serial peripheral interface system. Figure 51. Single Master / Multiple Slave Configuration

SERIAL PERIPHERAL INTERFACE (Cont’d)

11.5.6 Low Power Modes

11.5.6.1 Using the SPI to wake-up the Device

In slave configuration, the SPI is able to wake-up the Device from HALT mode through a SPIF inter- rupt. The data received is subsequently read from the SPIDR register when the software is running (interrupt vector fetch). If multiple data transfers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to per- form an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake-up the Device from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the Device enters Halt mode. So if Slave se- lection is configured as external (see Section 11.5.3.2), make sure the master drives a low level on the SS pin when the slave enters Halt mode.

11.5.7 Interrupts

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SPI. SPI interrupt events cause the Device to exit from WAIT mode. HALT SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ation resumes when the Device is woken up by an interrupt with “exit from HALT mode” capability. The data received is subsequently read from the SPIDR register when the soft- ware is running (interrupt vector fetching). If several data are received before the wake- up event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the Device. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Trans- fer Event SPIF SPIE Yes Yes Master Mode Fault Event MODF Yes No Overrun Error OVR Yes No

11.5.8 Register Description

Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. Bit 6 = SPE Serial Peripheral Output Enable. Bit 5 = SPR2 Divider Enable. Note: This bit has no effect in slave mode. tions of the MISO and MOSI pins are reversed. Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. CPHA settings as the master. Bits 1:0 = SPR[1:0] Serial Clock Frequency. Note: These 2 bits have no effect in slave mode. Table 17. SPI Master mode SCK Frequency

SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the Device and an exter- nal device has been completed. Note: While the SPIF bit is se t, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read. Bit 6 = WCOL Write Collision status (Read only). This bit is set by hardware when a write to the SPIDR register is done during a transmit se- quence. It is cleared by a software sequence (see Figure 50). 0: No write collision occurred 1: A write collision has been detected Bit 5 = OVR SPI Overrun error (Read only). This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 11.5.5.2). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Bit 4 = MODF Mode Fault flag (Read only). This bit is set by hardware when the SS pin is pulled low in master mode (see Section 11.5.5.1 Master Mode Fault (MODF)). An SPI interrupt can be generated if SPIE=1 in the SPICR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bit 3 = Reserved, must be kept cleared. Bit 2 = SOD SPI Output Disable. This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled Bit 1 = SSM SS Management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section 11.5.3.2 Slave Select Management. 0: Hardware management (SS managed by exter- nal pin) 1: Software management (internal SS signal con- trolled by SSI bit. External SS pin free for gener- al-purpose I/O) Bit 0 = SSI SS Internal Mode. This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the SS slave select signal when the SSM bit is set. 0 : Slave selected 1 : Slave deselected DATA I/O REGISTER (SPIDR) Read/Write Reset Value: Undefined The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will init iate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value lo- cated in the buffer and not the content of the shift register (see Figure 45). SPIF WCOL OVR MODF - SOD SSM SSI D7 D6 D5 D4 D3 D2 D1 D0

Table 18. SPI Register Map and Reset Values

11.6.1 Introduction

levels from up to 7 different sources. through a Control/Status Register.

11.6.2 Main Features

The block diagram is shown in Figure 52.

11.6.3 Functional Description

11.6.3.1 Analog Power Supply

loaded or badly decoupled power supply lines. Figure 52. ADC Block Diagram

10-BIT A/D CONVERTER (ADC) (Cont’d)

11.6.3.2 Input Voltage Amplifier

The input voltage can be amplified by a factor of 8 by enabling the AMPSEL bit in the ADCDRL regis- ter. When the amplifier is enabled, the input range is 0V to VDD/8. For example, if VDD = 5V, then the ADC can con- vert voltages in the range 0V to 430mV with an ideal resolution of 0.6mV (equivalent to 13-bit res- olution with reference to a V SS to VDD range). For more details, refer to the Electrical character- istics section. Note: The amplifier is switched on by the ADON bit in the ADCCSR register, so no additional start- up time is required when the amplifier is selected by the AMPSEL bit.

11.6.3.3 Digital A/D Conversion Result

The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (V AIN) is greater than V DDA (high-level voltage reference) then the conversion result is FFh in the A DCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (low- level voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and AD- CDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section. R AIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time.

11.6.3.4 A/D Conversion

The analog input ports must be configured as in- put, no pull-up, no interrupt. Refer to the «I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the ADCCSR register: – Select the CS[2:0] bits to assign the analog channel to convert. ADC Conversion mode In the ADCCSR register: Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. When a conversion is complete: – The EOC bit is set by hardware. – The result is in the ADCDR registers. A read to the ADCDRH resets the EOC bit. To read the 10 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRL 3. Read ADCDRH. This clears EOC automati- cally. To read only 8 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRH. This clears EOC automati- cally.

11.6.4 Low Power Modes

Note: The A/D converter may be disabled by re- setting the ADON bit. This feature allows reduced power consumption when no conversion is need- ed and between single shot conversions.

11.6.5 Interrupts

None. Mode Description WAIT No effect on A/D Converter HALT A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilization time t STAB (see Electrical Characteristics) before accurate conversions can be performed.

10-BIT A/D CONVERTER (ADC) (Cont’d)

11.6.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by soft- ware reading the ADCDRH register. 0: Conversion is not complete 1: Conversion complete Bit 6 = SPEED ADC clock selection This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit de- scription. Bit 5 = ADON A/D Converter on This bit is set and cleared by software. 0: A/D converter and amplifier are switched off 1: A/D converter and amplifier are switched on Bit 4:3 = Reserved. Must be kept cleared. Bit 2:0 = CH[2:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. *The number of channels is device dependent. Refer to the device pinout description. DATA REGISTER HIGH (ADCDRH) Read Only Reset Value: xxxx xxxx (xxh) Bit 7:0 = D[9:2] MSB of Analog Converted Value AMP CONTROL/DATA REGISTER LOW (AD- CDRL) Read/Write Reset Value: 0000 00xx (0xh) Bit 7:5 = Reserved. Forced by hardware to 0. Bit 4 = AMPCAL Amplifier Calibration Bit This bit is set and cleared by software. User is sug- gested to use this bit to calibrate the ADC when amplifier is ON. Setting this bit internally connects amplifier input to 0v. Hence, corresponding ADC output can be used in software to eliminate ampli- fier-offset error. 0: Calibration off 1: Calibration on. (The input voltage of the amp is set to 0V) Note: It is advised to use this bit to calibrate the ADC when the amplifier is ON. Setting this bit in- ternally connects the amplifier input to 0v. Hence, the corresponding ADC output can be used in soft- ware to eliminate an amplifier-offset error. Bit 3 = SLOW Slow mode This bit is set and cleared by software. It is used together with the SPEED bit to configure the ADC clock speed as shown on the table below. EOC SPEED ADON 0 CH3 CH2 CH1 CH0 Channel Pin* CH2 CH1 CH0 AIN0 0 0 0 AIN1 0 0 1 AIN2 0 1 0 AIN3 0 1 1 AIN4 1 0 0 AIN5 1 0 1 AIN6 1 1 0 D9 D8 D7 D6 D5 D4 D3 D2

000 AMP

This bit is set and cleared by software. be less than or equal to 2 MHz. Table 19. ADC Register Map and Reset Values

12 INSTRUCTION SET

12.1 ST7 ADDRESSING MODES

Table 20. ST7 Addressing Mode Overview

ST7 ADDRESSING MODES (Cont’d)

12.1.1 Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation.

12.1.2 Immediate

Immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value.

12.1.3 Direct

In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub- modes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF address- ing space. Direct (long) The address is a word, thus allowing 64 Kbyte ad- dressing space, but requires 2 bytes after the op- code.

12.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte ad- dressing space and requires 2 bytes after the op- code.

12.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (point- er). The pointer address follows the opcode. The indi- rect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations

12.1.6 Indirect Indexed (Short, Long)

er address follows the opcode. and requires 1 byte after the opcode. and requires 1 byte after the opcode. Table 21. Instructions Supporting Direct,

12.1.7 Relative Mode (Direct, Indirect)

register value by adding an 8-bit signed offset to it. The offset follows the opcode.

12.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available op- codes for an 8-bit CPU (256 opcodes), three differ- ent prebyte opcodes are defined. These prebytes modify the meaning of the instruction they pre- cede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruc- tion using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

12.2.1 Illegal Opcode Reset

In order to provide enhanced robustness to the de- vice against unexpected behaviour, a system of il- legal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, com- bined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. Note: A valid prebyte associated with a valid op- code forming an unauthorized combination does not generate a reset. Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF

INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine retu rn Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >

INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2's compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z

13 ELECTRICAL CHARACTERISTICS

13.1 PARAMETER CONDITIONS

13.1.1 Minimum and Maximum values

times the standard deviation (mean±3Σ).

13.1.2 Typical values

guidelines and are not tested.

13.1.3 Typical curves

given only as design guidelines and are not tested.

13.1.4 Loading capacitor

measurement are shown in Figure 53. Figure 53. Pin loading conditions

13.1.5 Pin input voltage

vice is described in Figure 54. Figure 54. Pin input voltage

13.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

13.2.1 Voltage Characteristics

13.2.2 Current Characteristics

13.2.3 Thermal Characteristics

Notes: 1. Directly connecting the I/O pins to VDD or VSS could damage the device if an unexpected change of the I/O configura- tion occurs (for example, due to a co rrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if V IN maximum is respected. If V IN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected 3. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. No negative current injection allowed on PB0 and PB1 pins. 6. When several inputs are submitted to a current injection, the maximum ΣI INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi- mum current injection on four I/O port pins of the device. Symbol Ratings Maximum value Unit VDD - VSS Supply voltage 7.0 V VIN Input voltage on any pin 1) & 2) VSS-0.3 to VDD+0.3 VESD(HBM) Electrostatic discharge voltage (Human Body Model) see section 13.7.3 on page 113 V Symbol Ratings Maximum value Unit IVDD Total current into VDD power lines (source) 3) 100 mA IVSS Total current out of VSS ground lines (sink) 3) 100 IIO Output current sunk by any standard I/O and control pin 25 Output current sunk by any high sink I/O pin 50 Output current source by any I/Os and control pin - 25 IINJ(PIN) 2) & 4) Injected current on RESET pin ± 5 Injected current on OSC1 and OSC2 pins ± 5 Injected current on PB0 and PB1 pins 5) +5 Injected current on any other pin 6) ± 5 ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 6) ± 20 Symbol Ratings Value Unit TSTG Storage temperature range -65 to +150 °C TJ Maximum junction temperature (see Table 22, “THERMAL CHARACTERISTICS,” on page 128)

13.3 OPERATING CONDITIONS

13.3.1 General Operating Conditions: Suffix 6 Devices

TA = -40 to +85°C unless otherwise specified. Figure 55. fCLKIN Maximum Operating Frequency Versus VDD Supply Voltage

13.3.2 Operating Conditions with Low Voltage Detector (LVD)

TA = -40 to 85°C, unless otherwise specified Note: 1. Not tested in production. 2. Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU.

13.3.3 Auxiliary Voltage Detector (AVD) Thresholds

TA = -40 to 85°C, unless otherwise specified Note: 1. Not tested in production.

13.3.4 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte). Symbol Parameter Conditions Min Typ Max Unit VIT+(LVD) Reset release threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.00 3.40 1) 2.65 1) 4.25 3.60 2.90 4.50 3.80 3.15 V V IT-(LVD) Reset generation threshold (VDD fall) High Threshold Med. Threshold Low Threshold 3.80 3.20 2.40 4.05 3.40 2.70 4.30 3.65 1) 2.901) Vhys LVD voltage threshold hysteresis V IT+(LVD)-VIT-(LVD) 200 mV VtPOR VDD rise time rate 2) 20 20000 µs/V tg(VDD) Filtered glitch delay on VDD Not detected by the LVD 150 ns IDD(LVD) LVD/AVD current consumption 220 µA Symbol Parameter Conditions Min Typ Max Unit VIT+(AVD) 1=>0 AVDF flag toggle threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.401) 3.901) 3.201) 4.70 4.10 3.40 5.00 4.30 3.60 V VIT-(AVD) 0=>1 AVDF flag toggle threshold (VDD fall) High Threshold Med. Threshold Low Threshold 4.30 3.70 2.90 4.60 3.90 3.20 4.90 4.101) 3.401) Vhys AVD voltage threshold hysteresis V IT+(AVD)-VIT-(AVD) 150 mV ∆VIT- Voltage drop between AVD flag set and LVD reset activation VDD fall 0.45 V Symbol Parameter Conditions Min Typ Max Unit VDD(RC) Internal RC Oscillator operating voltage 2.4 5.5 VVDD(x4PLL) x4 PLL operating voltage 2.4 3.3 VDD(x8PLL) x8 PLL operating voltage 3.3 5.5 tSTARTUP PLL Startup time 60 PLL input clock (fPLL) cycles

OPERATING CONDITIONS (Cont’d) The RC oscillator and PLL characteristics are temperature-dependent and are grouped in four tables. Notes: 1. Data based on characterization results, not tested in production 2. RCCR0 is a factory-calibrated setting for 1000kHz with ±0.2 accuracy @ TA =25°C, VDD=5V. See “INTERNAL RC OS- CILLATOR ADJUSTMENT” on page 23 3. Guaranteed by design. 4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy. 5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 11 on page 24. Symbol Parameter Conditions Min Typ Max Unit fRC Internal RC oscillator fre- quency RCCR = FF (reset value), TA=25°C,VDD=5V 760 kHzRCCR = RCCR02 ),TA=25°C,VDD=5V 1000 ACCRC Accuracy of Internal RC oscillator with RCCR=RCCR0 TA=25°C,VDD=4.5 to 5.5V -1 +1% TA=-40 to +85°C,VDD=5V -5 +2 % TA=0 to +85°C,VDD=4.5 to 5.5V -2 1) +21) % IDD(RC) RC oscillator current con- sumption TA=25°C,VDD=5V 970 1) µA tsu(RC) RC oscillator setup time T A=25°C,VDD=5V 10 2) µs fPLL x8 PLL input clock 1 1) MHz tLOCK PLL Lock time5) 2m s tSTAB PLL Stabilization time5) 4m s ACCPLL x8 PLL Accuracy fRC = 1MHz@TA=25°C,VDD=4.5 to 5.5V 0.1 4) % fRC = 1MHz@TA=-40 to +85°C,VDD=5V 0.1 4) % tw(JIT) PLL jitter period f RC = 1MHz 8 3) kHz JITPLL PLL jitter (∆fCPU/fCPU)1 3) % IDD(PLL) PLL current consumption T A=25°C 600 1) µA

OPERATING CONDITIONS (Cont’d) Notes: 1. Data based on characterization results, not tested in production 2. RCCR1 is a factory-calibrated setting for 700MHz with ±0.2 accuracy @ TA =25°C, VDD=3V. See “INTERNAL RC OS- CILLATOR ADJUSTMENT” on page 23. 3. Guaranteed by design. 4. Averaged over a 4ms period. After the LOCKED bit is set, a period of t STAB is required to reach ACCPLL accuracy 5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 11 on page 24. Symbol Parameter Conditions Min Typ Max Unit fRC Internal RC oscillator fre- quency RCCR = FF (reset value), TA=25°C, VDD= 3.0V 560 kHzRCCR=RCCR12) ,TA=25°C,VDD= 3V 700 ACCRC Accuracy of Internal RC oscillator when calibrated with RCCR=RCCR11)2) TA=25°C,VDD=3V -2 +2 % TA=25°C,VDD=2.7 to 3.3V -25 +25 % TA=-40 to +85°C,VDD=3V -15 15 % IDD(RC) RC oscillator current con- sumption TA=25°C,VDD=3V 700 1) µA tsu(RC) RC oscillator setup time T A=25°C,VDD=3V 10 2) µs fPLL x4 PLL input clock 0.7 1) MHz tLOCK PLL Lock time5) 2m s tSTAB PLL Stabilization time5) 4m s ACCPLL x4 PLL Accuracy fRC = 1MHz@TA=25°C,VDD=2.7 to 3.3V 0.1 4) % fRC = 1MHz@TA=40 to +85°C,VDD= 3V 0.1 4) % tw(JIT) PLL jitter period f RC = 1MHz 8 3) kHz JITPLL PLL jitter (∆fCPU/fCPU)1 3) % IDD(PLL) PLL current consumption T A=25°C 190 1) µA

13.4 SUPPLY CURRENT CHARACTERISTICS

13.4.1 Supply Current

1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals

in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)

driven by external square wave, LVD disabled.

1. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in i nput mode with a static value at V DD or

VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. SLOW-WAIT mode selected with f CPU based on f OSC divided by 32. All I/O pins in input mode with a static value at

VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,

tested in production at VDD max and fCPU max.

1. All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at V DD max. and fCPU
2. This consumption refers to the Halt period only and not the associated run period which is software dependent.

Figure 63. Typical IDD in RUN vs. fCPU Figure 64. Typical IDD in SLOW vs. fCPU

Figure 65. Typical IDD in WAIT vs. fCPU Figure 66. Typical IDD in SLOW-WAIT vs. fCPU Figure 67. Typical IDD in AWUFH mode Figure 68. Typical IDD vs. Temperature

13.4.2 On-chip peripherals

1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer running in PWM
2. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica-

tion (data sent equal to 55h).

1. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions with am-

13.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA.

13.5.1 General Timings

Notes: 1. Guaranteed by Design. Not tested in production. 2. Data based on typical application software. 3. Time measured between interrupt event and interrupt vector fetch. Dtc(INST) is the number of tCPU cycles needed to fin- ish the current instruction execution.

13.5.2 Auto Wakeup from Halt Oscillator (AWU)

Symbol Parameter 1) Conditions Min Typ 2) Max Unit tc(INST) Instruction cycle time f CPU=8MHz 23 1 2 t CPU 250 375 1500 ns tv(IT) Interrupt reaction time 3) tv(IT) = ∆tc(INST) + 10 fCPU=8MHz 10 22 t CPU 1.25 2.75 µs Symbol Parameter Conditions Min Typ Max Unit fAWU AWU Oscillator Frequency 50 125 250 kHz tRCSRT AWU Oscillator startup time 50 µs

13.6 MEMORY CHARACTERISTICS

TA = -40°C to 85°C, unless otherwise specified

13.6.1 RAM and Hardware Registers

13.6.2 FLASH Program Memory

13.6.3 EEPROM Data Memory

Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg- isters (only in HALT mode). Guaranteed by construction, not tested in production. 2. Up to 32 bytes can be programmed at a time. 3. The data retention time increases when the TA decreases. 4. Data based on reliability test results and monitored in production. 5. Data based on characterization results, not tested in production. 6. Guaranteed by Design. Not tested in production. 7. Design target value pending full product characterization. Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode 1) HALT mode (or RESET) 1.6 V Symbol Parameter Conditions Min Typ Max Unit VDD Operating voltage for Flash write/erase 2.4 5.5 V tprog Programming time for 1~32 bytes 2) TA=−40 to +85°C 5 10 ms Programming time for 1.5 kBytes TA=+25°C 0.24 0.48 s tRET Data retention 4) TA=+55°C3) 20 years NRW Write erase cycles TA=+25°C 10K 7) cycles IDD Supply current Read / Write / Erase modes fCPU = 8MHz, VDD = 5.5V 2.66) mA No Read/No Write Mode 100 µA Power down mode / HALT 0 0.1 µA Symbol Parameter Conditions Min Typ Max Unit VDD Operating voltage for EEPROM write/erase 2.4 5.5 V tprog Programming time for 1~32 bytes TA=−40 to +85°C 5 10 ms tret Data retention 4) TA=+55°C 3) 20 years NRW Write erase cycles TA=+25°C 300K 7) cycles

13.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba- sis during product characterization.

13.7.1 Functional EMS (Electro Magnetic

Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ■ ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. This test conforms with the IEC 1000-4-2 standard. ■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4- 4 standard. A device reset allows normal operations to be re- sumed. The test results are given in the table be- low based on the EMS levels and classes defined in application note AN1709.

13.7.1.1 Designing hardened software to avoid

EMC characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the manage- ment of runaway conditions such as: – Corrupted program counter – Unexpected reset – Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the RE- SET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be ap- plied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note AN1015).

13.7.2 Electro Magnetic Interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/ 3 which specifies the board and the loading of each pin. Notes: 1. Data based on characterization results, not tested in production. Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD=5V, TA=+25°C, fOSC=8MHz conforms to IEC 1000-4-2 3B VFFTB Fast transient voltage burst limits to be applied through 100pF on VDD and VDD pins to induce a func- tional disturbance VDD=5V, TA=+25°C, fOSC=8MHz conforms to IEC 1000-4-4 3B Symbol Parameter Conditions Monitored Frequency Band Max vs. [fOSC/fCPU] Unit 8/4MHz 16/8MHz SEMI Peak level VDD=5V, TA=+25°C, SO20 package, conforming to SAE J 1752/3 0.1MHz to 30MHz 9 17 dBµV30MHz to 130MHz 31 36 130MHz to 1GHz 25 27 SAE EMI Level 3.5 4 -

EMC CHARACTERISTICS (Cont’d)

13.7.3 Absolute Maximum Ratings (Electrical

Sensitivity) Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer to the application note AN1181.

13.7.3.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22- A114A/A115A standard. Absolute Maximum Ratings Notes: 1. Data based on characterization results, not tested in production.

13.7.3.2 Static and Dynamic Latch-Up

■ LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. ■ DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1 000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181. Electrical Sensitivities Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standar d. B Class strictly covers all the JEDEC criteria (international standard). Symbol Ratings Conditions Maximum value 1) Unit VESD(HBM) Electro-static discharge voltage (Human Body Model) TA=+25°C 4000 V Symbol Parameter Conditions Class 1) LU Static latch-up class T A=+25°C A DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A

13.8 I/O PORT PIN CHARACTERISTICS

13.8.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

1. Data based on characterization results, not tested in production.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

characteristics, not tested in production.

1. The R PU pull-up equivalent resistor is based on a resistive transistor (corresponding I PU current characteristics de-
2. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

Figure 69. Two typical Applications with unused I/O Pin Figure 70. Typical IPU vs. VDD with VIN=VSS (external pull-up of 10k mandatory in This is to avoid entering ICC mode unexpectedly during a reset. noisy environment).

13.8.2 Output Driving Current

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

1. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of

IIO (I/O ports and control pins) must not exceed IVDD.

1. Not tested in production, based on characterization results.

Figure 71. Typical VOL at VDD=2.4V (standard) Figure 72. Typical V OL at VDD=2.7V (standard)

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

TA = -40°C to 85°C, unless otherwise specified Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistiv e transistor. Specified for voltages on RESET pin between VILmax and VDD 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage V SS - 0.3 0.3xVDD VVIH Input high level voltage 0.7xV DD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis 1) 2V VOL Output low level voltage 2) VDD=5V IIO=+5mA TA≤85°C TA≥85°C 0.5 1.0

1.2 VIIO=+2mA TA≤85°C

TA≥85°C 0.2 0.4 0.5 RON Pull-up equivalent resistor 3) 1) VDD=5V 20 40 80 kΩVDD=3V. 40 70 120 tw(RSTL)out Generated reset pulse duration Internal reset sources 30 µs th(RSTL)in External reset pulse hold time 4) 20 µs tg(RSTL)in Filtered glitch duration 200 ns

13.10 COMMUNICATION INTERFACE CHARACTERISTICS

13.10.1 SPI - Serial Peripheral Interface

fOSC, and TA unless otherwise specified. Figure 88. SPI Slave Timing Diagram with CPHA=0 3)

1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified. Figure 91. Typical Application with ADC

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data

based on characterization results, not tested in production.

1. The stabilization time of the AD converter is masked by the fi

rst tLOAD. The first conversion after the enable is then always valid.

1) Data based on characterization results over the whole temperature range, monitored in production. performed on any analog input. current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins. Figure 92. ADC Accuracy Characteristics with amplifier disabled between the actual and the ideal transfer curves. transition and the first ideal one. transition and the last actual one. between actual steps and the ideal one.

Figure 93. ADC Accuracy Characteristics with amplifier enabled to 2 MHz. (if fCPU=8MHz. then SPEED=0, SLOW=1). between the actual and the ideal transfer curves. transition and the first ideal one. transition and the last actual one. between actual steps and the ideal one.

ADC CHARACTERISTICS (Cont’d) Notes: 1) Data based on characterization results over the whole temperature range, not tested in production. 2) For precise conversion results it is recommended to calibrate the amplifier at the following two points: – offset at V INmin = 0V – gain at full scale (for example V IN=430mV) 3) Monotonicity guaranteed if VIN increases or decreases in steps of min. 5mV. 4) Please refer to the Application Note AN1830 for details of TE% vs Vin. 5) Refer to the offset variation in temperature below Amplifier output offset variation The offset is quite sensitive to temperature varia- tions. In order to ensure a good reliability in meas- urements, the offset must be recalibrated periodi- cally i.e. during power on or whenever the device is reset depending on the customer application and during temperature variation. The table below gives the typical offset variation over temperature: Symbol Parameter Conditions Min Typ Max Unit VDD(AMP) Amplifier operating voltage 3.6 5.5 V VIN Amplifier input voltage4) VDD=3.6V 0 350 mVVDD=5V 0 500 VOFFSET Amplifier output offset voltage5) VDD=5V 200 mV VSTEP Step size for monotonicity3) VDD=3.6V 3.5 mVVDD=5V 4.89 Linearity Output Voltage Response Linear Gain factor Amplified Analog input Gain 2) 8 Vmax Output Linearity Max Voltage VINmax = 430mV, VDD=5V 3.65 3.94 V Vmin Output Linearity Min Voltage 200 mV Typical Offset Variation (LSB) UNIT -45 -20 +25 +90 °C -12 -7 - +13 LSB

14 PACKAGE CHARACTERISTICS

14.1 PACKAGE MECHANICAL DATA

Figure 94. 20-Pin Plastic Small Outline Package, 300-mil Width

Table 22. THERMAL CHARACTERISTICS

1. The power dissipation is obtained from the formula P D=PINT+PPORT where PINT is the chip internal power (I DDxVDD)

and PPORT is the port power dissipation determined by the user.

1. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.

14.2 SOLDERING AND GLUEABILITY INFORMATION

Recommended soldering information given only as design guidelines. Figure 95. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) Figure 96. Recommended Reflow Soldering Oven Profile (MID JEDEC)

15 DEVICE CONFIGURATION

Each device is available for production in user pro- grammable versions (FLASH)as well as in factory coded versions (FASTROM). ST7FDALI devices are FLASH versions. ST7PDALI devices are Factory Advanced Service Technique ROM (FASTROM) versions: they are factory programmed FLASH devices. ST7FDALI devices are shipped to customers with a default program memory content (FFh), while FASTROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the customer us- ing the Option Bytes while the FASTROM devices are factory configured.

15.1 OPTION BYTES

The two option bytes allow the hardware configu- ration of the microcontroller to be selected. The option bytes can be accessed only in pro- gramming mode (for example using a standard ST7 programming tool). OPTION BYTE 0 OPT7 = Reserved, must always be 1. OPT6:4 = OSCRANGE[2:0] Oscillator range When the internal RC osc illator is not selected (Option OSC=1), these option bits select the range of the resonator oscillator current source or the ex- ternal clock source. Note: When the internal RC oscillator is selected, the OSCRANGE option bits must be kept at their default value in order to select the 256 clock cycle delay (see Section 7.5). OPT3:2 = SEC[1:0] Sector 0 size definition These option bits indicate the size of sector 0 ac- cording to the following table. OPT1 = FMP_R Read-out protection Readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first and the device can be reprogrammed. Refer to the ST7 Flash Programming Reference Manual and section 4.5 on page 14 for more de- tails 0: Read-out protection off 1: Read-out protection on OPT0 = FMP_W FLASH write protection This option indicates if the FLASH program mem- ory is write protected. Warning: When this option is selected, the pro- gram memory (and the option bit itself) can never be erased or programmed again. 0: Write protection off 1: Write protection on OSCRANGE 210 Typ. frequency range with Resonator LP 1~2MHz 0 0 0 MP 2~4MHz 0 0 1 MS 4~8MHz 0 1 0 HS 8~16MHz 0 1 1 VLP 32.768kHz 1 0 0 External Clock source: CLKIN on OSC1 1 0 1 on PB4 1 1 1 Reserved 1 1 0 Sector 0 Size SEC1 SEC0 0.5k 00 1k 01 2k 10 4k 11 OPTION BYTE 0 OPTION BYTE 1 Res. OSCRANGE 2:0 SEC1 SEC0 FMP R FMP W PLL x4x8 PLL OFF PLL32 OFF OSC LVD1 LVD0 WDG SW WDG HALT Default Value 1111110011 1 01111

OPT7 = PLLx4x8 PLL Factor selection. OPT5 = PLL32OFF 32MHz PLL disable. lected threshold as shown in Table 23. Table 23. LVD Threshold Configuration This option bit selects the watchdog type. Table 24. List of valid option combinations

15.2 DEVICE ORDERING INFORMATIONAND TRANSFER OF CUSTOMER CODE

tents and the list of the selected options (if any). Table 25. Supported part numbers

ST7DALI FASTROM MICROCONTROLLER OPTION LIST (Last update: November 2004) *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. Device Type/Memory Size/Package (check only one option): Warning: Addresses 1000h, 1001h, FFDEh and FFDFh are reserved areas for ST to program RCCR0 and RCCR1 (see section 7.1 on page 23). Conditioning (check only one option)): Special Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ " Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: DIP20/S020 (8 char. max) : _ _ _ _ _ _ _ _ Watchdog Selection: [ ] Software Ac tivation [ ] Hard ware Activation Watchdog Reset on Halt: [ ] Reset [ ] No Reset LVD Reset [ ] Disabled [ ] Enabled [ ] Highest threshold [ ] Medium threshold [ ] Lowest threshold Sector 0 size: [ ] 0.5K [ ] 1K [ ] 2K [ ] 4K Readout Protection: [ ] Disabled [ ] Enabled FLASH write Protection: [ ] Disabled [ ] Enabled Clock Source Selection: [ ] Resonator: [ ] VLP: Very Low power resonator (32 to 100 kHz) [ ] LP: Low power resonator (1 to 2 MHz) [ ] MP: Medium power resonator (2 to 4 MHz) [ ] MS: Medium speed resonator (4 to 8 MHz) [ ] HS: High speed resonator (8 to 16 MHz) [ ] External Clock: [ ] On OSC1 [ ] On PB4 [ ] Internal RC Oscillator PLL [ ] Disabled [ ] PLLx4 [ ] PLLx8 PLL32 [ ] Disabled [ ] Enabled Important note: Not all configurations are available. See Table 24 on page 131 for authorized option byte combinations. Please download the latest version of this option list from: http://www.st.com/mcu > downloads > ST7 microcontrollers > Option list SO20: | [ ] ST7PDALIF2M6 | [ ] Tape & Reel [ ] Tube

15.3 DEVELOPMENT TOOLS

ers, evaluation tools, emulators and programmers. interchange of TEBs (Target Emulation Board). Debugging kit from Softec Microsystems.

15 STxF-INDART/USB can be ordered with the

socket board via ST7 ICC connector. many third-party development tools. Table 26. STMicroelectronics Development Tools Note 1: Add suffix /EU, /UK, /US for the power supply of your region.

15.4 ST7 APPLICATION NOTES

IDENTIFICATION DESCRIPTION APPLICATION EXAMPLES AN1658 SERIAL NUMBERING IMPLEMENTATION AN1720 MANAGING THE READ-OUT PROTECTION IN FLASH MICROCONTROLLERS AN1755 A HIGH RESOLUTION/PRECISION THERMOMETER USING ST7 AND NE555 AN1756 CHOOSING A DALI IMPLEMENTATION STRATEGY WITH ST7DALI EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 I²C COMMUNICATION BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOÏD) AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER AN1046 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS AN1048 ST7 SOFTWARE LCD DRIVER AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERALS REGISTERS AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1105 ST7 PCAN PERIPHERAL DRIVER AN1129 PWM MANAGEMENT FOR BLDC MOTOR DRIVES USING THE ST72141 AN1130 AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS WITH THE ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X AN1445 EMULATED 16 BIT SLAVE SPI AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER AN1602 16-BIT TIMING OPERATIONS USING ST7262 OR ST7263B ST7 USB MCUS AN1633 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION IN ST7 NON-USB APPLICATIONS AN1712 GENERATING A HIGH RESOLUTION SINEWAVE USING ST7 PWMART AN1713 SMBUS SLAVE DRIVER FOR ST7 I2C PERIPHERALS AN1753 SOFTWARE UART USING 12-BIT ART GENERAL PURPOSE AN1476 LOW COST POWER SUPPLY FOR HOME APPLIANCES AN1526 ST7FLITE0 QUICK REFERENCE NOTE

AN1709 EMC DESIGN FOR ST MICROCONTROLLERS AN1752 ST72324 QUICK REFERENCE NOTE PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING AN1103 IMPROVED B-EMF DETECTION FOR LOW SPEED, LOW VOLTAGE WITH ST72141 AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876 AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS PRODUCT MIGRATION AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324 AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 AN1604 HOW TO USE ST7MDT1-TRAIN WITH ST72F264 PRODUCT OPTIMIZATION AN 982 USING ST7 WITH CERAMIC RENATOR AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY AN1181 ELECTROSTATIC DISCHARGE SENSITIVE MEASUREMENT AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY AN1530 ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCILLA- TOR AN1605 USING AN ACTIVE RC TO WAKEUP THE ST7LITE0 FROM POWER SAVING MODE AN1636 UNDERSTANDING AND MINIMIZING ADC CONVERSION ERRORS AN1828 PIR (PASSIVE INFRARED) DETECTOR USING THE ST7FLITE05/09/SUPERLITE AN1971 ST7LITE0 MICROCONTROLLED BALLAST PROGRAMMING AND TOOLS AN 978 ST7 VISUAL DEVELOP SOFTWARE KEY DEBUGGING FEATURES AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 AN1179 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO- GRAMMING) AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY IDENTIFICATION DESCRIPTION

AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS AN1576 IN-APPLICATION PROGRAMMING (IAP) DRIVERS FOR ST7 HDFLASH OR XFLASH MCUS AN1577 DEVICE FIRMWARE UPGRADE (DFU) IMPLEMENTATION FOR ST7 USB APPLICATIONS AN1601 SOFTWARE IMPLEMENTATION FOR ST7DALI-EVAL AN1603 USING THE ST7 USB DEVICE FIRMWARE UPGRADE DEVELOPMENT KIT (DFU-DK) AN1635 ST7 CUSTOMER ROM CODE RELEASE INFORMATION AN1754 DATA LOGGING PROGRAM FOR TESTING ST7 APPLICATIONS VIA ICC AN1796 FIELD UPDATES FOR FLASH BASED ST7 APPLICATIONS USING A PC COMM PORT AN1900 HARDWARE IMPLEMENTATION FOR ST7DALI-EVAL AN1904 ST7MC THREE-PHASE AC INDUCTION MOTOR CONTROL SOFTWARE LIBRARY SYSTEM OPTIMIZATION AN1711 SOFTWARE TECHNIQUES FOR COMPENSATING ST7 ADC ERRORS AN1827 IMPLEMENTATION OF SIGMA-DELTA ADC WITH ST7FLITE05/09 IDENTIFICATION DESCRIPTION

16 IMPORTANT NOTES

16.1 EXECUTION OF BTJX INSTRUCTION

When testing the address $FF with the "BTJT" or "BTJF" instructions, the CPU may perform an in- correct operation when the relative jump is nega- tive and performs an address page change. To avoid this issue, including when using a C com- piler, it is recommended to never use address $00FF as a variable (using the linker parameter for example).

16.2 ADC CONVERSION SPURIOUS RESULTS

Spurious conversions occur with a rate lower than 50 per million. Such conversions happen when the measured voltage is just between 2 consecutive digital values. Workaround A software filter should be implemented to remove erratic conversion results whenever they may cause unwanted consequences.

16.3 A/ D CONVERTER ACCURACY FOR FIRST

When the ADC is enabled after being powered down (for example when waking up from HALT, ACTIVE-HALT or setting the ADON bit in the AD- CCSR register), the first conversion (8-bit or 10- bit) accuracy does not meet the accuracy specified in the datasheet. Workaround In order to have the accuracy specified in the da- tasheet, the first conversion after a ADC switch-on has to be ignored.

16.4 NEGATIVE INJECTION IMPACT ON ADC

Injecting a negative current on an analog input pins significantly reduces the accuracy of the AD Converter. Whenever necessary, the negative in- jection should be prevented by the addition of a Schottky diode between the concerned I/Os and ground. Injecting a negative current on digital input pins degrades ADC accuracy especially if performed on a pin close to ADC channel in use.

16.5 CLEARING ACTIVE INTERRUPTS

When an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the CC register may be corrupted. Concurrent interrupt context The symptom does not occur when the interrupts are handled normally, i.e. when: - The interrupt request is cleared (flag reset or in- terrupt mask) within its own interrupt routine - The interrupt request is cleared (flag reset or in- terrupt mask) within any interrupt routine - The interrupt request is cleared (flag reset or in- terrupt mask) in any part of the code while this in- terrupt is disabled If these conditions are not met, the symptom can be avoided by implementing the following se- quence: Perform SIM and RIM operation before and after resetting an active interrupt request Ex: SIM reset flag or interrupt mask RIM

16.6 USING PB4 AS EXTERNAL INTERRUPT

PB4 cannot be used as an external interrupt in HALT mode because the port pin PB4 is not active in this mode.

17 REVISION HISTORY

Table 27. Revision History

19-Nov-2004 2.0 Revision number incremented from 1.3 to 2.0 due to Internal Document Management System change Added FASTROM devices Modified Caution to pin n°12 (SO20) or pin n°7 (DIP20) and added caution to PB0 and PB1 in Table 1 on page 7 Changed Caution in section 4.4 on page 13 Changed 1st sentence in section 4.5.1 on page 14 Replaced CRSR register by SICSR register in section 7.6.3 on page 32 Added note in section 7.6.1 on page 29 Changed “Output Compare Mode” on page 57 and note 1 in section 11.2.6 on page 60 Replaced FFh by FFFh in the description of OVF bit in section 11.2.6 on page 60 Replaced ICAP1 pin by LTIC Pin in section 11.3.3.3 on page 66 Changed “An interrupt is generated if SPIE = 1 in the SPICSR register” to “An interrupt is gen- erated if SPIE = 1 in the SPICR register” in description of OVR and MODF bits in section 11.5.8 on page 87 Removed references to “-40°C to +125°C” temperature range in section 13 on page 100 Changed section 13.3 on page 102 Changed note 2 in section 13.2.1 on page 101 Added one row in section 13.2.2 on page 101 (PB0 and PB1) Added note 5 in section 13.4.1 on page 108 Added VDD row in section 13.6.3 on page 111 Changed section 13.7 on page 112 Added caution to Figure 69 on page 114 Added VIL min value and VIH max value in section 13.8.1 on page 114 and in section 13.9.1 on page 119 Modified “Asynchronous RESET Pin” on page 119 (Figure 86 and Figure 87) Updated ADC accuracy table values on page 124 Changed values in ADC Characteristics table on page 126 Added “NEGATIVE INJECTION IMPACT ON ADC ACCURACY” on page 138 Changed Table 24, “List of valid option combinations,” on page 131: PLLx4x8 selection when PLL offAdded “ST7DALI FASTROM MICROCONTROLLER OPTION LIST (Last update: No- vember 2004)” on page 133 Updated Figure 65. Typical IDD in WAIT vs. fCPU with correct data Added data for Fcpu @ 1MHz into Section 13.4.1 Supply Current table. Reset delay in section 11.1.3 on page 51 changed to 30µs Altered note 1 for section 13.2.3 on page 101 removing references to RESET Removed sentence relating to an effective change only after overflow for CK[1:0], page 60 MOD00 replaced by 0Ex in Figure 36 on page 57 Added Note 2 related to Exit from Active Halt, section 11.2.5 on page 59 Added illegal opcode detection to page 1, section 7.6 on page 29, section 12 on page 94 Clarification of Flash read-out protection, section 4.5.1 on page 14 Added note 4 and description relating to Total Percentage in Error and Amplifier Output Offset Variation to the ADC Characteristics subsection and table, page 126 Added note 5 and description relating to Offset Variation in Temperature to ADC Characteris- tics subsection and table, page 126 FPLL value of 1MHz quoted as Typical instead of a Minimum in section 13.3.4.1 on page 104 Updated FSCK in section 13.10.1 on page 121 to FCPU/4 and FCPU/2 Corrected FCPU in SLOW and SLOW WAIT modes in section 13.4.1 on page 108 Max values updated for ADC Accuracy, page 124 Notes indicating that PB4 cannot be used as an external interrupt in HALT mode, section 16.6 on page 138 and Section 8.3 PERIPHERAL INTERRUPTS Changed section 11.5.2 on page 79 Changed section 11.5.3.3 on page 82 Removed “optional” referring to VDD in Figure 4 on page 13 Changed FMP_R option bit description in section 15.1 on page 130 Added “CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE” on page 138 Changed “DEVELOPMENT TOOLS” on page 134 Changed Figure 41 on page 70: fCPU instead of 8MHz fCPU Date Revision Description of Changes

Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publicati on are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia – Belgium - Brazil - Canada - China – Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America