ST7590 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 24
Technical content
Datasheet sections
- 1 Device description
- 2 Pin connection
- 3 Maximum ratings
- 3.1 Absolute maximum ratings
- 3.2 Thermal data
- 3.3 Electrical characteristics
- 4 Analog front end (AFE)
- 4.1 Reception path
- 4.2 Transmission path
- 4.3 Power amplifier
- 4.4 Thermal shutdown and temperature control
- 4.5 Zero-crossing detector
- 4.6 One time programmable (OTP) memory array
- 4.7 Power management
- 4.8 Clock management
- 5 Application information
- 6 Package mechanical data
- 7 Revision history
Features
■ Fully integrated narrow-band power line networking system-on-chip ■ High performing DSP engine with embedded turn-key firmware for Orthogonal frequency division multiplexing (OFDM) modulation, featuring: – 96 sub-carriers in CENELEC A band – BDPSK, QDPSK, 8DPSK programmable modulations – Programmable bit rate up to 128 kbps – Convolutional coding and Viterbi decoding – Signal to noise ratio and channel quality estimation – Full PRIME compliant PHY ■ On chip peripherals: – Host controller UART/SPI interface – I2C/SPI external data memory interface – High speed SRAM controller for optional external SRAM program code execution – Watchdog timer ■ On chip 128 bit AES encryption HW block ■ Fully integrated analog front end: – ADC and DAC – High sensitivity receiver – High linearity transmitter with intelligent gain control ■ Fully integrated power line driver – Up to 1 Arms, 14 Vpp single ended – Configurable active filtering topology – Ultra low distortion – Embedded temperature sensor – Current control ■ 3.3 V or 5 V I/O digital I/O supply ■ Integrated 5 V and 1.8 V linear regulators for AFE and digital core supply ■ 8 V to 18 V line driver power supply ■ Suitable for applications compliant with EN50065 and FCC part 15 specifications ■ -40 °C to +85 °C temperature range ■ QFN48 7x7 (ST7590) and TQFP 100 14x14 (ST7590T) exposed pad package options Application PRIME compliant smart metering and smart grid applications.
Description
ST7590 is the first complete Narrowband OFDM power line communication system-on-chip made using a multi-power technology with state of the art VLSI CMOS lithography. The ST7590 is based on dual core architecture to assure outstanding communication performance with a very high level of flexibility and programmability for either open standard or fully customized implementations. QFN-48 (7 x 7 mm) 41&0
1 Device description
ST7590 is available in two different package options: TQFP100 and QFN48. 32 LLC Layer from an external Serial NV memory connected through SPI interface. memories to run the protocol. communication system-on-chip ideal for PRIME compliant applications. chip when secure communication is requested. regulatory standards compliance. Figure 1. ST7590 block diagram
10 GPIO
3 Timers 2 Interrupts
2 Pin connection
Figure 2. TQFP100 pin connection Figure 3. QFN48 (a) pin connection ST7590 will run the code present in the embedded ROM only.
Table 1. Pin description
Table 1. Pin description (continued)
- Active Pull up (only in input mode for bi-directional pins)
3 Maximum ratings
3.1 Absolute maximum ratings
3.2 Thermal data
Table 2. Absolute maximum ratings Table 3. Thermal characteristics (1)
- Mounted on a 2s2p PCB, with a dissipating surfac e, connected through vias, on the bottom side of the
3.3 Electrical characteristics
TA = -40 to +85 °C, TJ < 125 °C, VCC = 18 V unless otherwise specified. Table 4. Electrical characteristics
Table 4. Electrical characteristics (continued)
- This parameter does not include the tolerance of external components
- Referred to IC start up, uploading code from external NVM and its execution from external RAM may require some second.
Figure 4. Power amplifier test circuit
4 Analog front end (AFE)
4.1 Reception path
(analog to digital converter). Figure 5. Reception path block diagram Table 5. PGA gain table
4.2 Transmission path
the desired transmission level. Figure 6. Transmission path block diagram steps of 3dB (typical). The maximum level corresponds to the TX_OUT full range.
4.3 Power amplifier
the amplifier driving even very low impedance points of the network. network to increase the linearity of the output signal.
4.4 Thermal shutdown and temperature control
must get below 125 °C before the ST7590 power amplifier comes back to operation. zones, as indicated in Table 6. Table 6. Temperature zones
1 T < T_TH 1
4 T > T_TH 3
4.5 Zero-crossing detector
4.6 One time programmable (OTP) memory array
4.7 Power management
- VCC (8 to 18 V) as the main power supply;
- VDDIO (3.3 or 5 V) for the I/O and digital sections. Two internal linear regulators provide the remaining required voltages:
- 5 V regulator (used by the analog front end blocks), generated from the VCC voltage and connected to the VCCA pin;
- 1.8 V regulator (required for the DSP and microcontroller cores, the digital blocks, the PLL and the oscillator), generated from the VDDIO voltage and connected to the VDD_REG_1V8 pin. All the supply voltages must be properly filtered, to their respective ground, using external capacitors close to each supply pin (see Figure 7). Note: The internal regulators connected to VD D_REG_1V8 and VCCA are not designed to supply external circuitry; their output is externally accessible for filtering purpose only.
Table 7. OTP memory array
0 Reserved – hardware trimming
Figure 7. Power supply internal scheme
4.8 Clock management
drive a crystal having a load capacitance of 16 pF with no additional components.
5 Application information
Figure 8. TQFP100 128 Kb external memory application example Figure 9. QFN48 application example
6 Package mechanical data
specifications, grade definitions and product status are available at: www.st.com. Table 8. TQFP 100 package mechanical data
Figure 10. TQFP 100 package outline
Table 9. QFN-48 (7 x 7 mm) package mechanical data
Figure 11. QFN-48 (7 x 7 mm) package outline
7 Revision history
Table 10. Document revision history