FSK, PSK multi-mode power line networking system-on-chip
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 33
Technical content
Datasheet sections
- 1 Device overview
- 2 Pin connection
- 3 Maximum ratings
- 3.1 Absolute maximum ratings
- 3.2 Thermal data
- 4 Electrical characteristics
- 5 Analog front-end (AFE)
- 5.1 Reception path
- 5.2 Transmission path
- 5.3 Power amplifier
- 5.4 Current and voltage control
- 5.5 Thermal shutdown and temperature control
- 5.6 Zero crossing comparator
- 6 Power management
- 7 Clock management
- 8 Functional overview
- 9 Physical layer
- 9.1 PSK modulations
- 9.1.1 PSK modes
- 9.1.2 PSK physical frame
Features
Fully integrated narrow-band power line networking system-on-chip High-performing PHY processor with embedded turnkey firmware featuring: – B-FSK modulation up to 9.6 kbps – B-PSK, Q-PSK, 8-PSK modulations up to 28.8 kbps – Dual channel operation mode – Convolutional error correction coding – Signal-to-noise ratio estimation – B-PSK with PNA mode against impulsive noise Protocol engine embedding turnkey communication protocol – Framing service – Error detection – Sniffer functionality Host controller UART interface up to 57.6 kbps AES-128 based authentication and confidentiality services Fully integrated analog front-end: – ADC and DAC – Digital transmissi on level control – PGA with automatic gain control – High sensitivity receiver Fully integrated single-ended power amplifier for line driving – Up to 1 A RMS, 14 V p-p output – Configurable active filtering topology – Very high linearity – Embedded temperature sensor – Current control feature 8 to 18 V power amplifier supply 3.3 V or 5 V digital I/O supply Zero crossing detection Suitable for EN50065, FCC part 15 and ARIB compliant applications Communication carrier frequency programmable up to 250 kHz VFQFPN48 7x7x1.0 48L exposed pad package -40 °C to +105 °C temperature range
Applications
Smart metering applications Street lighting control Command and control networking
Description
The ST7580 is a flexible power line networking system-on-chip combining a high performing PHY processor core and a protocol controller with a fully integrated analog front-end (AFE) and line driver for a scalable future-proof, cost effective, single chip, narrow-band power line communication solution. 9)4)31[[/ SLWFK Table 1. Device summary
1 Device overview
flexibility for either open standards or customized implementations. when secure communication is requested. current makes the ST7580 a unique system-on-chip for power line communication. Line coupling network design is also simplified, leading to a very low cost BOM. stringent application requirements and regulatory standards compliance. Figure 1. Block diagram
2 Pin connection
Figure 2. Pinout top view
Table 2. Pin description 1 TXD Digital output High-Z Disabled UART data out.
2 RXD Digital input High-Z Disabled UART data in
4 TRSTN Digital input Input Enabled System JTAG interface reset (active low)
5 TMS Digital input Input Enabled System JTAG interface mode select
6 GND Power - - Digital ground
7 TCK Digital input High-Z Disabled System JTAG interface clock.
8 TDO Digital output High-Z Disabled System JTAG interface data out
9 TDI Digital input Input Enabled System JTAG interface data in
10 RESETN Digital input Input Disabled System reset (active low)
12 XIN Analog - - Crystal oscillator input / external clock input
13 XOUT Analog - -
14 GND Power - - Digital ground
15 VSSA Power - - Analog ground
17 VCCA Power - - 5 V analog supply / internal regulator output. Externally accessible for filtering purposes only.
18 ZC_IN Analog input - - Zero crossing input
19 RX_IN Analog input - - Reception analog input
20 TX_OUT Analog output - - Transmission analog output
21 PA_IN+ Analog input - - Power amplifier
22 PA_IN- Analog input - - Power amplifier
23 CL Analog input - - Current limit sense input
24 VCC Power - - Power supply
25 VSS Power - - Power ground
26 PA_OUT Analog output - - Power amplifier output
27 VDD_REG_1V8 Power - - 1.8 V digital supply / internal regulator output.
29 NC - - - Not used, leave floating
30 NC - - - Not used, leave floating
31 RESERVED0 Power - - Pull-up to VDDIO.
32 NC - - - Not used, leave floating
33 GND Power - - Digital ground
35 VSSA Power - - Analog ground
36 CL_SEL Digital output High-Z Disabled Current limit resistor selection output
37 PL_RX_ON Digital output High-Z Disabled Reception in progress output
38 T_REQ Digital input High-Z Disabled UART communication control line
39 BR1 Digital input High-Z Disabled UART baud rate selection (sampled after each reset
41 PL_TX_ON Digital output High-Z Disabled Transmission in progress output
42 RESERVED1 - - - Pull up to VDDIO
43 RESERVED2 - - - Pull up to VDDIO
44 RESERVED3 - - - Pull up to VDDIO
45 GND Power - - Digital ground
47 RESERVED4 - - - Connect to VDDIO
48 RESERVED5 - - - Pull up to VDDIO
Table 2. Pin description (continued) Table 3. UART baud rate selection
3 Maximum ratings
3.1 Absolute maximum ratings
3.2 Thermal data
Table 4. Absolute maximum ratings Table 5. Thermal characteristics
- Mounted on a 2-side + vias PCB with a ground dissipating area on the bottom side.
- Same conditions as in note 1, with ma ximum transmission duration limited to 100 s.
4 Electrical characteristics
TA = -40 to +105 °C, TJ < 125 °C, VCC = 18 V, unless otherwise specified. Table 6. Electrical characteristics
50 Hz 100 dB
Table 6. Electrical characteristics (continued)
- Referred to Tamb = -40 °C.
- This parameter does not include the tolerance of external components.
5 Analog front-end (AFE)
5.1 Reception path
Figure 5. Reception path block diagram attenuate the input signal according to the input voltage range for the ADC. Table 7. PGA gain table
5.2 Transmission path
the desired transmission level. Figure 6. Transmission path block diagram the TX_OUT full range, down to -31 dB (typ.).
5.3 Power amplifier
the amplifier to drive even very low impedance points of the network. network to increase the linearity of the output signal.
5.4 Current and voltage control
current and making it flow through a resistor RCL connected between the CL pin and VSS. a time until V(CL) goes below the CL_TH threshold. Figure 7. PA_OUT current sense circuit have different crest factor values, different RCL values are required for the two modulations. CL_TH and CL_RATIO parameters, are indicated in Table 8. Table 8. CL resistor typical values
modulation is selected, CL_SEL is in high impedance state.
5.5 Thermal shutdown an d temperature control
go below T_TH3 before the ST7580 power amplifier comes back into operation. zones, as indicated in Table 9. Table 9. Temperature zones
5.6 Zero crossing comparator
synchronous to the mains voltage.
1 T < T_TH 1
4 T > T_TH 3
6 Power management
Figure 8 shows the power supply structure for the ST7580. The ST7580 operates from two external supply voltages: VCC (8 to 18 V) for the power amplifier and the analog section VDDIO (3.3 or 5 V) for interface lines and digital blocks. Two internal linear regulators provide the remaining required voltages: 5 V analog front-end supply: generated from the VCC voltage and connected to the VCCA pin 1.8 V digital core supply: generated from the VDDIO voltage and connected to VDD_REG_1V8 (direct regulator output) and VDD pins. The VDD_PLL pin, supplying the internal clock PLL, must be externally connected to VDD through a ferrite bead for noise filtering purposes. All supply voltages must be properly filtered to their respective ground, using external capacitors close to each supply pin, in accordance with the supply scheme depicted in Figure 8. Note that the internal regulators connected to VDD_REG_1V8 and to VCCA are not designed to supply external circuitry; their outputs are externally accessible for filtering purposes only. External connections between all VDD pins are not required.
Figure 8. Power supply internal scheme and external connections ground, VSSA is the analog ground, while GND pins refer to digital ground. Connection between VSSA and GND is provided through a ferrite bead.
Figure 9. ST7580 ground pins and recommended external connections
7 Clock management
The main clock source is an 8 MHz crystal connected to the internal oscillator through the XIN and XOUT pins. Both XIN and XOUT pins have a 32 pF integrated capacitor, in order to drive a crystal having a load capacitance of 16 pF with no additional components. Alternatively, an 8 MHz external clock can be directly supplied to the XIN pin, leaving XOUT floating. A PLL internally connected to the output of the oscillator generates the fCLK_PHY, required by the PHY processor block engine. fCLK_PHY is then divided by two to obtain fCLK_PROTOCOL, required by the protocol controller.
8 Functional overview
The ST7580 provides a complete physical layer (PHY) to the external host and some data link layer (DL) services for power line communication. It is mainly developed for smart metering applications in CENELEC A band, but suitable also for other command and control applications and remote load management in CENELEC B and D band. A UART host interface is available for communication with an external host, exporting all the functions and services required to configure and control the device and its protocol stack. The embedded PHY layer, hosted in the PHY processor, implements two different modulation schemes: a B-FSK modulation up to 9.6 kbps and a multi-mode PSK modulation with channel quality estimation, dual channel receiving mode, and convolutional coding, delivering a throughput up to 28.8 kbps. The embedded DL layer hosted in the protocol controller offers framing and error correction services.
Figure 10. Functional overview
9 Physical layer
Signal to noise ratio (SNR) estimation.
9.1 PSK modulations
recognize the PSK modulation kind used by the transmitter without further settings.
9.1.1 PSK modes
B-PSK coded with peak noise avoidance (PNA) algorithm. robustness through error correction. ZC_IN pin must be connected to a zero crossing detection circuit. Table 10 summarizes all the available PSK modulations and their bit rate. Table 10. PSK modes description
9.1.2 PSK physical frame
Figure 11 shows the physical frame for PSK modulations. Figure 11. PSK physical frame structure (length in bytes) physical layer also provides SNR estimation on the received unique word. its first byte, which is always present.
9.2 FSK modulations
9.2.1 FSK options
Table 11. FSK modes description
Figure 12. Frequency deviation summarizes the frequency deviation for all symbol rate and deviation factors. Table 12. Frequency deviation possible values
9.2.2 FSK physical frame
Figure 13 shows the physical frame for FSK modulations. Figure 13. FSK physical frame structure (length in bytes) length and values are programmable. its first byte, which is always present.
9.2.3 FSK settings
settings at a time, both for transmitting and receiving.
9.3 Channel and modu lation selection
Maximum frequency difference (f1 - f2): 38.461 kHz. signal around either the high channel or the low channel. Any modulation type can be used. The reception can be configured in single channel mode or in dual channel mode. carrier with a lower frequency value). detects a valid frame on a channel, it stops listening to the other channel.
- Any of the PSK modulations (specified by the mode field in PSK physical frame,
- FSK modulation, using the current FSK settings.
maximum FSK symbol rate is limited to 2400 baud. Table 13. ST7580 allowed settings combination for reception
10 Data link layer
10.1 Data link frame
Figure 14. Data link frame structure (length in bytes) (length and payload, or payload only) can be chosen by the external host.
10.2 Error detection and sniffer mode
computes the CRC field and builds the frames for transmitting frames. about frames received with wrong CRC also.
10.3 Security services
is used for both transmitting and receiving frames.
specifications, grade definitions and product status are available at: www.st.com. generated by the operation of the two linear regulators and the power amplifier. Figure 15. VFQFPN48 (7 x 7 x 1.0 mm) package outline
Table 14. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data
Table 15. Document revision history 26-Jan-2012 1 Initial release. Minor modifications throughout document.