ST7570 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 26
Technical content
Datasheet sections
- 1 Device overview
- 2 Pin connection
- 2.1 Pin description
- 3 Maximum ratings
- 3.1 Absolute maximum ratings
- 3.2 Thermal data
- 4 Electrical characteristics
- 5 Analog front end (AFE)
- 5.1 Reception path
- 5.2 Transmission path
- 5.3 Power amplifier
- 5.4 Current and voltage control
- 5.5 Thermal shutdown and temperature control
- 5.6 Zero-crossing PLL and delay compensation
- 6 Power management
- 7 Clock management
- 8 Functional overview
- 8.1 References
- 9 Physical layer
- 9.1 S-FSK principles
- 9.2 Bit timing
- 9.3 Frame structure at physical level
- 9.4 Frame timing and time-slot synchronization
- 10 Package mechanical data
- 11 Revision history
Features
■ Fully integrated narrow-band power line networking system-on-chip ■ High performing PHY processor with embedded turn-key firmware for spread frequency shift keying (S-FSK) modulation: – Programmable bit rate up to 2.4 Kbps (@
50 Hz)
– 1 Hz step programmable carriers up to 148.5 kHz – Signal to noise ratio estimation – Received signal strength indication ■ Protocol engine embedding: – IEC61334-5-1 PHY and MAC layers – Alarm management – Repeater Call procedure – Intelligent search initiator process ■ On chip peripherals: – Host controller UART interface ■ Fully integrated analog front end: – ADC and DAC – PGA with automatic gain control for high receiving sensitivity – High linearity modulated signal generation ■ Fully integrated single-ended power amplifier for line driving – Up to 1 A rms, 14 V p-p output – Configurable Active filtering topology – Very high linearity – Embedded temperature sensor – Current control feature ■ 8 to 18 V power amplifier supply ■ 3.3 V or 5 V digital I/O supply ■ Integrated 5 V and 1.8 V linear regulators for AFE and digital core supply ■ Mains zero crossing synchronization ■ Suitable for EN50065 and FCC part 15 compliant applications ■ VFQFPN48 package with exposed pad ■ -40 °C to +85 °C temperature range
Applications
■ Smart metering applications ■ Street lighting control ■ Command and control networking
Description
The ST7570 is a powerful power line networking system-on-chip. It combines a high-performance PHY processor core and a protocol controller core with a fully integrated analog front end (AFE) and line driver. The ST7570 features allow the most cost- effective, single-chip power line communication solution based on IEC61334-5-1 S-FSK standard. Table 1. Device summary
1 Device overview
flexibility and programmability. requirements and regulatory standards compliance. Figure 1. Block diagram
2 Pin connection
Figure 2. Pin out top view
2.1 Pin description
Table 2. Pin description
1 TXD Digital output High Z Disabled UART data out
2 RXD Digital input High Z Disabled UART data in
4 TRSTN Digital input Input Enabled System JTAG interface reset (active low)
5 TMS Digital input Input Enabled System JTAG interface mode select
6 GND Power - - Digital ground
7 TCK Digital input High Z Disabled System JTAG interface clock.
8 TDO Digital output High Z Disabled System JTAG interface data out
9 TDI Digital input Input Enabled System JTAG interface data in
10 RESETN Digital input Input Disabled System reset (active low)
11 VDD Power - -
12 XIN Analog - - Crystal oscillator input / external clock input
13 XOUT Analog - -
14 GND Power - - Digital ground
15 VSSA Power - - Analog ground
16 VDD_PLL Power - - 1.8 V PLL supply voltage.
17 VCCA Power - - 5 V analog supply / internal regulator output
18 ZC_IN_A Analog input - - Analog zero-crossing input
19 RX_IN Analog input - - Reception analog input
20 TX_OUT Analog output - - Transmission analog output
21 PA_IN+ Analog input - - Power amplifier
22 PA_IN- Analog input - - Power amplifier
23 CL Analog input - - Current limit sense input
24 VCC Power - - Power supply
25 VSS Power - - Power ground
26 PA_OUT Analog output - - Power amplifier output
29 NC - - - Not used, leave floating
30 NC - - - Not used, leave floating
31 RESERVED6 - - - Pull up to VDDIO
32 NC - - - Not used, leave floating
33 GND Power - - Digital ground
35 VSSA Power - - Analog ground
36 PRESLOT
- Transmission or Reception in progress (TXRXP).
If not used, this pin can be left floating. 37 ZC_IN_D Digital input High Z Disabled Digital zero-crossing input.
38 T_REQ Digital input High Z Disabled UART communication control line
39 BR1 Digital input High Z Disabled UART baud rate selection
41 RESERVED0 - - - Connect to GND
42 RESERVED1 - - - Pull up to VDDIO
43 RESERVED2 - - - Pull up to VDDIO
44 RESERVED3 - - - Pull up to VDDIO
45 GND Power - - Digital ground
46 VDD Power - -
47 RESERVED4 - - - Connect to VDDIO
48 RESERVED5 - - - Pull up to VDDIO
Table 2. Pin description (continued)
Table 3. UART baud rate selection
3 Maximum ratings
3.1 Absolute maximum ratings
3.2 Thermal data
Figure 3. Absolute maximum ratings
- Mounted on a 2-side + vias PCB with a ground dissipating area on the bottom side.
- Same conditions as in Note 1, with maximum transmission duration limited to 100 s.
4 Electrical characteristics
TA = -40 to +85°C, TJ < 125°C, VCC = 18 V unless otherwise specified. Table 5. Electrical characteristics
50 Hz 100 dB
50 Hz,
Table 5. Electrical characteristics (continued)
Figure 4. Power amplifier test circuit
- This parameter does not include t he tolerance of external components
5 Analog front end (AFE)
5.1 Reception path
Figure 5. reception path block diagram attenuate the input signal according to the input voltage range for the ADC.
5.2 Transmission path
Table 6. PGA gain table
Figure 6. Transmission path block diagram to the TX_OUT full range, down to -31 dB (typ.).
5.3 Power amplifier
the amplifier driving even very low impedance points of the network. network to increase the linearity of the output signal.
5.4 Current and voltage control
current and making it flow through a resistor RCL connected between the CL pin and VSS. time until V(CL) goes below the CL_TH threshold. The current sense circuit is depicted in Figure 6. Figure 7. PA_OUT current sense circuit value shall be calculated according to the transmitted signal waveform. and CL_RATIO parameters, is indicated in Table 7. Table 7. CL resistor typical values
5.5 Thermal shutdown and temperature control
get below T_TH3 before the ST7570 power amplifier comes back to operation. four zones, as indicated in Table 8. Table 8. Temperature zones
5.6 Zero-crossing PLL and delay compensation
- Analog input (ZC_IN_A): it requires a bipolar analog input signal which is internally squared through a Schmidt Trigger comparator with symmetrical thresholds;
- Digital input (ZC_IN_D): it requires a 50% duty-cycle square-wave digital signal (with two levels). The desired input can be selected by accessing a dedicated management information base (MIB) object. The ST7570 embeds a phase-locked loop (PLL) to generate the internal reference based on the external zero-crossing. In case of delay due to external zero crossing coupling circuits (i.e. based on optocouplers) or to improve interoperability, it is possible to introduce delay compensation through a dedicated MIB object.
Figure 8. Zero crossing detection
6 Power management
- VCC (8 to 18 V) for the power amplifier and the analog section;
- VDDIO (3.3 or 5 V) for interface lines and digital blocks. Two internal linear regulators provide the remaining required voltages:
- 5 V analog front end supply: generated from the VCC voltage and connected to the VCCA pin;
- 1.8 V digital core supply: generated from the VDDIO voltage and connected to VDD_REG_1V8 (direct regulator output) and VDD pins. The VDD_PLL pin, supplying the internal clock PLL, must be externally connected to VDD. All supply voltages must be properly filtered to their respective ground, using external capacitors close to each supply pin, in accordance to the supply scheme depicted in Figure 9. Note that the internal regulators connected to VDD_REG_1V8 and to VCCA are not designed to supply external circuitry; their outputs are externally accessible for filtering purpose only.
Figure 9. Power supply internal scheme
7 Clock management
The main clock source is an 8 MHz crystal connected to the internal oscillator through XIN and XOUT pins. Both XIN and XOUT pins have a 32 pF integrated capacitor, in order to drive a crystal having a load capacitance of 16 pF with no additional components. Alternatively, an 8 MHz external clock can be directly supplied to XIN pin, leaving XOUT floating. A PLL internally connected to the output of the oscillator generates the fCLK_PHY, required by the PHY processor block. fCLK_PHY is then scaled down by two to obtain fCLK_PC, required by the protocol controller.
8 Functional overview
The ST7570 embeds complete physical (PHY) and a medium access control (MAC) protocol layers and services compliant with the open standard IEC61334-5-1, mainly developed for smart metering applications, but suitable also for other command and control applications and remote load management in CENELEC B and D bands. A local port (UART) is available for communication with an external host, exporting all the functions and services required to configure and control the device and its protocol stack. Below a list of the protocol layers and functions embedded in the ST7570 (Figure 10):
- Physical layer: implemented in the PHY processor and exporting all the primitive functions listed in the international standard document IEC61334-5-1, plus additional services for configuration, alarm management, signal and noise amplitude estimation, phase detection, statistical information;
- MAC layer: implemented on the protocol controller and exporting all the primitive functions listed in the international standard document IEC61334-5-1, Repeater Call and Intelligent search initiator process together with additional services.
- Management information base (MIB): an information database with all the data required for proper configuration of the system (at both PHY and MAC layer);
- Host interface: all the services of the PHY , MAC and MIB are exported to an external host through the local UART port.
Figure 10. Functional overview
8.1 References
- ST7570 user manual, www.st.com/powerline
- International standard CEI-IEC-61334-5-1
9 Physical layer
9.1 S-FSK principles
higher robustness against narrow-band interferers typical of a spread-spectrum approach. Figure 11. S-FSK waveform (time domain) that a narrow-band interferer could corrupt both carriers at the same time. f0 and f1 can be set at any value in CENELEC bands A, B, D. Figure 12. S-FSK waveform (frequency domain)
9.2 Bit timing
Figure 13. Bit timing
9.3 Frame structure at physical level
- 2 byte preamble (PRE) (AAAAh);
- 2 byte start subframe delimiter (SSD) (54C7h);
- 38 byte physical service data unit (P_sdu);
- 3 byte for pause or alarm; The bytes are sent from the most significant byte (MSB) to the least significant byte (LSB). Bits within the byte are packed with the same order (msb to lsb).
Figure 14. Physical frame format
9.4 Frame timing and time-slot synchronization
the same “slot synchronization”.
- 15 mains cycles, at the 1200 bps operating speed (at 50 Hz);
- 7.5 mains cycles, at the 2400 bps operating speed (at 50 Hz). The slot synchronization is first achieved by the master (i.e. ST7570 modem in 'Client' mode) setting the time-slot starting at the mains zero-crossing instant. The frames transmitted by the master will enable the slot synchronization of all other slave nodes (i.e. ST7570 working in 'Server' mode): the reception of the sequence composed by PRE and SSD will allow all the 'Server' nodes aligning their time-slots to the Client's time-slot. !-V 3UHDPEOH 35( 6WDUW6XEIUDPH 'HOLPLWHU 66' 3BVGX 3DXVH$ODUP E\\WHV E\\WHV E\\WHV ELW 3+<)UDPH
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. generated by the operation of the two linear regulators and the power amplifier. A mechanical drawing of the VFQFPN48 package is included in Figure 15. Table 9. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data
Figure 15. VFQFPN48 (7 x 7 x 1.0 mm) package outline
Table 10. Document revision history 27-May-2010 1 Initial release. Updated pinout in Table 2, Electrical values in Table 5.