FSK power line transceiver
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 44
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin settings
- 2.1 Pin connection
- 2.2 Pin description
- 3 Electrical data
- 3.1 Maximum ratings
- 3.2 Thermal data
- 3.3 Recommended operating conditions
- 4 Electrical characteristics
- 5 Crystal resonator and external clock
- 6 Functional description
- 6.1 Carrier frequencies
- 6.2 Baud rates
- 6.3 Mark and space frequencies
- 6.4 ST7540 Mains access
- 6.5 Host processor interface
- 6.5.1 Communication between Host and ST7540
- 6.5.2 Control register access
- 6.6 Receiving mode
- 6.7 Transmission mode
- 6.8 Control register
FSK power line transceiver General features ■ Half-duplex frequency shift keying (FSK) transceiver ■ Integrated power line driver with programmable voltage and current control ■ Programmable mains access: – Synchronous – Asynchronous ■ Single supply voltage (from 7.5V up to 13.5V) ■ Very low power consumption (Iq = 5mA) ■ Integrates 5V voltage regulator (up to 50mA) with short circuit protection ■ Integrated 3.3V voltage regulator (up to 50mA) with short circuit protection ■ 3.3V or 5V digital supply ■ 8 Programmable transmission frequencies ■ Programmable baud rate up to 4800BPS ■ Receiving sensitivity up to 250µVRMS ■ Suitable for applications in accordance with EN
50065 Cenelec specification
■ Carrier or preamble detection ■ Band in use detection ■ Programmable control register ■ Watchdog timer ■ 8 or 16 Bit header recognition ■ ST7537 and ST7538 compatible ■ UART/SPI host interface
Description
The ST7540 is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and two linear regulators for 5V and 3.3V. The device operation is controlled by means of an internal register, programmable through the synchronous serial interface. Additional functions as watchdog, clock output, output voltage and current control, preamble detection, time-out and band in use are included. Realized in Multipower BCD5 technology that allows to integrate DMOS, Bipolar and CMOS structures in the same chip. HTSSOP28 Exposed Pad Order codes Part number Package Packaging ST7540 HTSSOP28 (Exposed Pad) Tube ST7540TR HTSSOP28 (Exposed Pad) Tape and reel
1 Block diagram
Figure 1. Block diagram
2 Pin settings
2.1 Pin connection
Figure 2. Pin connection (top view)
2.2 Pin description
Table 1. Pin description
1 CD_PD Digital/Output
Carrier, preamble or frame header detect output.
3 GND Supply Digital ground
4 RxD Digital/Output RX data output.
5 RxTx Digital/Input
Rx or Tx mode selection input. with internal pull-down TX data input.
7 BU/THERM Digital/Output
Band in use/Thermal Shutdown event detection output.
8 CLR/T Digital/Output Synchronous mains access clock or
10 MCLK Digital/Output Master clock output
11 RSTO Digital/Output Power ON or watchdog reset output
12 UART/SPI Digital/Input
13 WD Digital/Input
cleared on the falling edges.
14 PA_IN- Analog/Input Power line amplifier inverting input
15 PA_OUT Power/Output Power line amplifier output
17 VCC Supply Power supply voltage
18 PA_IN+ Analog/Input Power line amplifier not inverting input
19 TX_OUT Analog/Output Small signal analog transmit output
20 SVSS Supply Analog signal ground
21 X1 Analog/Output Crystal oscillator output
22 X2 Analog/Input Crystal oscillator input - or external clock input
23 VSENSE
24 CL(2) Analog/Input
capacitance is present on this pin.
25 RX_IN Analog/Input Receiving analog input
26 VDC Power 5V voltage regulator output
27 TEST1 Digital/Input
with internal pull-down Test input. Must be connected to GND. Table 1. Pin description (continued)
3 Electrical data
3.1 Maximum ratings
3.2 Thermal data
Table 2. Absolute maximum ratings
- This current is intended as not repetitive pulse current
Table 3. Thermal data
- Mounted on Multilayer PCB with a dissi pating surface on the bottom side of the PCB
- It is the same condition of the point above, without any heatsinking surface on the board.
3.3 Recommended operating conditions
Table 4. Recommended operating conditions
4 Electrical characteristics
Table 5. Electrical characteristics
Table 5. Electrical characteristics (continued)
Figure 3. PLI configuration for PA_OUT distortions measurement
- Not tested, guaranteed by design
5 Crystal resonator and external clock
Figure 4. External clock waveform Figure 5. Crystal Resonator
6 Functional description
6.1 Carrier frequencies
the normal working Mode to realize a multi frequency communication. filters are accordingly tuned.
6.2 Baud rates
ST7540 is a multi Baud rate device: four Baud Rate are available (See Table 8). Table 6. Channels List Table 7. ST7540 mark and space tones frequency distance Vs. baud rate and deviation
- Deviation = ∆F / (Baud Rate)
- Deviation 0.5 not allowed
6.3 Mark and space frequencies
∆F is the Frequency Deviation. is the Baudrate itself (∆F= Baudrate). The minimal Frequency Deviation is 600Hz. Table 8. ST7540 synthesized frequencies
6.4 ST7540 Mains access
- Synchronous access
- Asynchronous access The choice between the two types of access can be performed by means of Control Register bit 14(see Table 12) and affects the ST7540 data flow in Transmission Mode as in Reception Mode (for how to set the communication Mode, see Section 6.5). In data transmission mode:
- Synchronous Mains access: on clock signal provided by ST7540 (CLR/T line) rising edge, data transmission line (TxD line) value is read and sent to the FSK Modulator. ST7540 manages the Transmission timing according to the BaudRate Selected.
- Asynchronous Mains access: data transmission line (TxD line) value enters directly to the FSK Modulator. The Host Controller manages the Transmission timing (CLR/T line should be neglected). In data reception mode:
- Synchronous Mains access: on clock signal recovered by a PLL from ST7540 (CLR/T line) rising edge, value on FSK Demodulator is read and put to the data reception line (RxD line). ST7540 recovers the bit timing timing according to the BaudRate Selected.
- Asynchronous Mains access: Value on FSK Demodulator is sent directly to the data reception line (RxD line). The Host Controller recovers the communication timing (CLR/T line should be neglected). 600 132.5 600 1 75684 76335 1 132161 132813 1200 0.5 75684 76335 1200 0.5 132161 132813 1 75358 76660 1 131836 133138 2400 0.5 75358 76660 2400 0.5 131836 133138 1 74870 77148 1 131348 133626 4800 0.5 74870 77148 4800 0.5 131348 133626 1 73568 78451 1 130046 134928
6.5 Host processor interface
ST7540 exchanges data with the host processor through a serial interface. using RxD, TxD and CLR/T lines.
- Data Reception
- Data Transmission
- Control Register Read
- Control Register Write REG_DATA and RxTx lines are level sensitive inputs. ST7540 features two type of Host Communication Interfaces:
- SPI
- UART The selection can be done through the UART/SPI pin. If UART/SPI pin is forced to “0” SPI interface is selected while if UART/SPI pin is forced to “1” UART interface is selected. The type of interface affects the Data Reception by setting the idle state of RxD line. When ST7540 is in Receiving mode (REG_DATA=”0” and RxTx =“1”) and no data are available on mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the RxD line is forced to “0” when UART/SPI pin is forced to ”0” or it is forced to “1” when UART/SPI pin is forced to ”1”. The UART interface allows to connect an UART compatible device while SPI interface allows to connect an SPI compatible device. The allowed combinations of Host Interface/ST7540 Mains Access are:
Table 9. Data and Control register access bits configuration Table 10. Host interface / ST7540 mains access combinations
Figure 6. Synchronous and Asynchronous ST7540/Host Controller interfaces in Asynchronous mode, in this case REG_DATA pin must be tied to GND.
6.5.1 Communication bet ween Host and ST7540
=“1” ST7540 receives data from mains, if RxTx=”0” ST7540 transmits data over the mains).
- Asynchronous mode: In Asynchronous Mode, data are exchanged without any data Clock reference. The host controller has to recover the clock reference in receiving Mode and control the Bit time in transmission mode. If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7540 enters in an Idle State. After Tcc time the modem starts providing received data on RxD line. If RxTx line is set to “0” & REG_DATA=”0” (Data Transmission), ST7540 enters in an Idle State and transmission circuitry is switched on. After Tcc time the modem starts transmitting data present on TxD line. RxD CLR/T REG_DATA RxTx ST7540Host Controller TxD UART/Asynchronous Data Interface RxD CLR/T REG_DATA RxTx ST7540Host Controller TxD SPI/Synchronous Data Interface D03IN1415
6.5.2 Control register access
less than 24 bits are transferred to ST7540 the Control Register writing is aborted. are transferred, only the first 24 Control Register bits (from 23 to 0) are written. With REG_DATA = 1 and RxTx = 1, the content of the Control Register is sent on RxD port. Figure 9. Data reception Figure 10. data reception ➨ control register write ➨ data reception timing diagram
Figure 11. Data transmission ➨ control register read ➨ data reception timing diagram Figure 12. Data transmission ➨ control register write ➨ data reception timing diagram
6.6 Receiving mode
The receive section is active when RxTx Pin =”1” and REG_DATA=0. or space frequencies are detected on RX_IN Pin.
- Receiving Sensitivity Level Selection It is possible to select the ST7540 Receiving Sensitivity Level by Control Register (see Table 12) or setting to ‘1’ the TxD pin during reception phase (this condition overcomes the control register setting the sensitivity equal to BU threshold). Increasing the device sensitivity allows to improve the communication reliability when the ST7540 sensitivity is the limiting factor.
- Synchronization Recovery System (PLL) ST7540 embeds a Clock Recovery System to feature a Synchronous data exchange with the Host Controller. The clock recovery system is realized by means of a second order PLL. In Synchronous mode, data on the data line (RxD) are stable on CLR/T line rising edge (CLR/T Falling edge synchronized to RxD line transitions ± LOCK-IN Range). The PLL Lock-in and Lock-out Range is ±π/2. When the PLL is in the unlock condition RxD line is forced to “0” or “1” according to the UART/SPI pin level and CLR/T is forced to “0” only if the Detection Method “Preamble Detection With Conditioning” is selected.When PLL is in unlock condition it is sensitive to RxD Rising and Falling Edges. The maximum number of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the CLR/T Jitter. ST7540 PLL is forced in the un-lock condition, when more than 32 equal symbols are received.Due to the fact that the PLL, in lock-in condition, is sensitive only to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL into the un-lock condition.
Figure 13. ST7540 PLL lock-in range
- Carrier/Preamble Detection The Carrier/Preamble Block is a digital Frequency detector Circuit. It can be used to manage the MAINS access and to detect an incoming signal. Two are the possible setting: – Carrier Detection – Preamble Detection CLR/T RxD D03IN1417 LOCK-IN RANGE
ST7540 Functional description
- Carrier Detection The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier when it detects on the RX_IN Input a signal with an harmonic component close to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity Mode). When the device sensitivity is set by the TxD line (Sensitivity level equal to BU threshold) the CD_PD signal is conditioned to the BU signal. The CD_PD line is forced to a logic level low when a Carrier is detected.
- Preamble Detection The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier modulated at the Programmed Baud Rate for at least 4 Consecutive Symbols (“1010” or “0101” are the symbols sequences detected). CD_PD line is forced low till a Carrier signal is detected and PLL is in the lock-in range. To reinforce the effectiveness of the information given by CD_PD Block, a digital filtering is applied on Carrier or Preamble notification signal (see Section 6.8: Control register). The Detection Time Bits in the Control Register define the filter performance. Increasing the Detection Time reduced the false notifications caused by noise on main line. The Digital filter adds a delay to CD_PD notification equal to the programmed Detection Time. When the carrier frequency disappears, CD_PD line is held low for a period equal to the detection time and then forced high. During this time, some spurious data caused by noise can be demodulated and sent over RxD line.
- Header Recognition In Control Register Extended Mode (Control Register bit 21=”1”, see Table 12) the CD_PD line can be used to recognize if an header has been sent during the transmission. With Header Recognition function enable (Control Register bit 18=”1”, see Table 12), CD_PD line is forced low when a Frame Header is detected. If Frame Length Count function is enabled, CD_PD is held low and a number of 16 bit word equal to the Frame Length selected is sent to the host controller. In this case, CLR/T is forced to “0” and RxD is forced to “0” or “1” (according the UART/SPI pin level) when Header has not been detected or after the Frame Length has been reached. If Frame Length Count function is disabled, an header recognition is signaled by forcing CD_PD low for one period of CLR/T line. In this case, CLR/T and RxD signal are always present, even if no header has been recognized.
Figure 14. CD_PD Timing during RX Figure 15. Receiving path block diagram
6.7 Transmission mode
(TxD) enter synchronously or asynchronously to the FSK modulator.
- Synchronous Mains access: on CLR/T rising edge, TxD Line Value is read and sent to the FSK Modulator. ST7540 manages the Transmission timing according to the BaudRate Selected
- Asynchronous Mains access: TxD data enter directly to the FSK Modulator.The Host Controller manages the Transmission timing In both conditions no Protocol Bits are added by ST7540. The FSK frequencies are synthesized in the FSK modulator from a 16 MHz crystal oscillator by direct digital synthesis technique. The frequencies Table in different Configuration is reported in Table 8. The frequencies precision is same as external crystal one’s. TDCD TCD CD_PD RX_IN D03IN1418 TDCD TCD RxD (UART/SPI="1") demodulation active on RxD pin RxD (UART/SPI="0") noise demodulated noise demodulated /MT76/MT111/MT119/MT32/MT80/MT97/MT115/MT115 /MT66 /MT97/MT110/MT100/MT32/MT80/MT97/MT115/MT115 /MT80/MT82/MT69/MT45/MT70/MT73/MT76/MT84/MT69/MT82/MT73/MT70/MT32/MT70/MT73/MT76/MT84/MT69/MT82/MT70/MT83/MT75 /MT32/MT68/MT69/MT77/MT79/MT68/MT85/MT76/MT65/MT84/MT79/MT82 /MT68/MT73/MT71/MT73/MT84/MT65/MT76 /MT70/MT73/MT76/MT84/MT69/MT82 /MT77/MT73/MT88/MT69/MT82 /MT67/MT65/MT82/MT82/MT73/MT69/MT82/MT47 /MT80/MT82/MT69/MT65/MT77/MT66/MT76/MT69 /MT68/MT69/MT84/MT69/MT67/MT84/MT73/MT79/MT78 /MT65/MT71/MT67 /MT71/MT65/MT73/MT78 /MT67/MT79/MT78/MT84/MT82/MT79/MT76 /MT76/MT79/MT67/MT65/MT76 /MT79/MT83/MT67 /MT50/MT53 /MT66/MT105/MT116/MT32/MT50/MT51 /MT66/MT105/MT116/MT115/MT32/MT48/MT32/MT45/MT50 /MT66/MT105/MT116/MT115/MT32/MT51/MT45/MT52/MT32/MT38/MT49/MT52 /MT66/MT105/MT116/MT115/MT32/MT48/MT45/MT50 /MT82/MT88/MT95/MT73/MT78 /MT66/MT105/MT116/MT115/MT32/MT57/MT45/MT49/MT48/MT66/MT105/MT116/MT115/MT32/MT49/MT50/MT45/MT49/MT51/MT32/MT38/MT32/MT50/MT50 /MT67/MT97/MT114/MT114/MT105/MT101/MT114/MT32/MT68/MT101/MT116/MT101/MT99/MT116/MT105/MT111/MT110 /MT52 /MT82/MT120/MT68 /MT56 /MT67/MT76/MT82/MT47/MT84 /MT49 /MT67/MT68/MT95/MT80/MT68 /MT55 /MT66/MT85/MT47/MT84/MT72/MT69/MT82/MT77 /MT80/MT76/MT76 /MT66/MT105/MT116/MT115/MT32/MT51/MT45/MT52 /MT76/MT111/MT119/MT32/MT80/MT97/MT115/MT115 /MT66/MT65/MT78/MT68 /MT73/MT78 /MT85/MT83/MT69 /MT66/MT105/MT116/MT115/MT32/MT51/MT45/MT52/MT32/MT38/MT32/MT50/MT50 /MT66/MT97/MT110/MT100/MT32/MT80/MT97/MT115/MT115 /MT67/MT72/MT65/MT78/MT78/MT69/MT76 /MT70/MT73/MT76/MT84/MT69/MT82 /MT66/MT97/MT110/MT100/MT32/MT80/MT97/MT115/MT115 /MT68/MT48/MT51/MT73/MT78/MT49/MT52/MT49/MT57 /MT72/MT69/MT65/MT68/MT69/MT82 /MT82/MT69/MT67/MT79/MT71/MT78/MT46 /MT66/MT105/MT116/MT115/MT32/MT49/MT56/MT45/MT50/MT49/MT32/MT38 /MT50/MT52/MT45/MT52/MT55
at the end of the on-going half FSK sinewave cycle. Figure 16. Transmitting path block diagram
- Automatic Level Control (ALC) The Automatic Level Control Block (ALC) is a variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time. The ALC gain range is 0dB to 30 dB and the gain change is clocked at 5KHz. Each step increases or reduces the voltage of 1dB (Typ). Two are the control loops acting to define the ALC gain: – A Voltage Control loop – A Current Control Loop The Voltage control loop acts to keep the Peak-to-Peak Voltage constant on Vsense. The gain adjustment is related to the result of a peak detection between the Voltage waveform on Vsense and two internal Voltage references. It is possible to protect the Voltage Control Loop against noise by freezing the output level (see Section 7.5: Output voltage level freeze). – If Vsense < Vsense TH - VsenseHYST The next gain level is increased by 1 step –I f V s e n s eTH - VsenseHYST < Vsense < VsenseTH + VsenseHYST No Gain Change – If Vsense > Vsense TH + VsenseHYST The next gain level is decreased by 1 step /MT84/MT82/MT65/MT78/MT83/MT77/MT73/MT83/MT83/MT73/MT79/MT78 /MT70/MT73/MT76/MT84/MT69/MT82 /MT70/MT83/MT75 /MT77/MT79/MT68/MT85/MT76/MT65/MT84/MT79/MT82/MT68/MT45/MT84/MT89/MT80/MT69 /MT70/MT76/MT73/MT80 /MT70/MT76/MT79/MT80 /MT68/MT65/MT67 /MT49/MT52 /MT49/MT53 /MT56 /MT54 /MT49/MT57 /MT84/MT73/MT77/MT69/MT82/MT84/MT72/MT69/MT82/MT77/MT65/MT76 /MT83/MT69/MT78/MT83/MT79/MT82 /MT86/MT79/MT76/MT84/MT65/MT71/MT69 /MT76/MT79/MT79/MT80 /MT67/MT85/MT82/MT82/MT69/MT78/MT84 /MT76/MT79/MT79/MT80 /MT67/MT76/MT82/MT47/MT84/MT32/MT71/MT69/MT78/MT69/MT82/MT65/MT84/MT79/MT82 /MT50/MT52 /MT50/MT51 /MT86/MT115/MT101/MT110/MT115/MT101 /MT67/MT76 /MT80/MT65/MT95/MT73/MT78/MT45 /MT80/MT65/MT95/MT79/MT85/MT84 /MT84/MT88/MT95/MT79/MT85/MT84/MT67/MT76/MT82/MT47/MT84 /MT84/MT120/MT68 /MT66/MT105/MT116/MT32/MT49/MT52 /MT66/MT105/MT116/MT115/MT32/MT48/MT45/MT53/MT66/MT105/MT116/MT115/MT32/MT48/MT45/MT50 /MT66/MT105/MT116/MT115/MT32/MT55/MT45/MT56 /MT66/MT97/MT110/MT100/MT32/MT80/MT97/MT115/MT115 /MT80/MT65 /MT65/MT76/MT67 /MT68/MT48/MT51/MT73/MT78/MT49/MT52/MT50/MT48 /MT49/MT56 /MT80/MT65/MT95/MT73/MT78/MT43 /MT43 /MT45 /MT55 /MT66/MT85/MT47/MT84/MT72/MT69/MT82/MT77 /MT66/MT105/MT116/MT115/MT32/MT49/MT55/MT32/MT38/MT32/MT50/MT49
capacitor effect has been neglected. Figure 18. Typical output current vs RCL
- Integrated Power Line Interface (PLI) The Power Amplifier (PA) is a CMOS AB Class Power Amplifier. The PA requires, to ensure a proper operation, a regulated and well filtered Supply Voltage. Vcc Voltage and PA_OUT Voltage must fulfil the following formulas to work without clipping phenomena:
Table 11. VOUT Vs. R1 & R2 resistors value
select an appropriate active filtering topology to filter the signal present on TX_OUT pin. TX_OUT output has a current capability much lower than PA_OUT. Figure 19. PA_OUT and V
Functional description ST7540
6.8 Control register
The ST7540 is a multi-channel and multifunction transceiver. An internal 24 or 48 Bits (in Extended mode) Control Register allows to manage all the programmable parameters (Table 12). The programmable functions are:
- Channel Frequency
- Baud Rate
- Deviation
- Watchdog
- Transmission Timeout
- Frequency Detection Time
- Detection Method
- Mains Interfacing Mode
- Output Clock
- Sensitivity Mode
- Input Pre-Filter In addition to these functions the Extended mode provides 24 additional bits and others functions:
- Output Level Freeze
- Frame Header Recognizes (one 16 bits header of or two 8 bits headers) with support to Frame Length Bit count
Table 12. Control register functions
60 KHz
66 KHz
72 KHz
76 KHz
82.05 KHz
86 KHz
110 KHz
132.5 KHz
6 Watchdog
1 Enabled
11 Reserved Do not force a different value 0
configuration is not allowed.
1 Asynchronous
16 MHz
8 MHz
4 MHz
1 Disabled
19 Frame Length
20 Header
21 Extended
22 Sensitivity
1 Normal
23 Input Filter Disabled
7 Auxiliary analog and digital functions
7.1 Band in use
Sensitivity (83.5 dBµV Typ.) and with a different BandPass filter Selectivity (40dB/Dec). BU/THERM line is forced High when a signal in band is detected.
7.2 Time out
disabled for at least 125 ms. To Unlock the Time Out condition RxTx should be forced High. During the time out period only register access or reception mode are enabled. before starting a new data transmission. Time Out time is programmable using Control Register bits 7 and 8 (Table 12). Figure 22. Time-out timing and unlock sequence
7.3 Reset & watchdog
Figure 23. Reset and Watchdog Timing
7.4 Output clock
the Control Register to be a ratio of the crystal oscillator frequency (Fosc, Fosc/2 Fosc/4). cycle. The oscillator can be disabled using Control Register bits 15 and 16 (Table 12).
7.5 Output voltage level freeze
Register (Control Register bit 21=”1”).
7.6 Extended control register
enabled using Control Register bit 21(Table 12).
Auxiliary analog and digital functions ST7540
7.7 Under voltage lock out
The UVLO function turns off the device if the VCC voltage falls under 4V. Hysteresis is 340mV typically.
7.8 Thermal shutdown
The ST7540 is provided of a thermal protection which turn off the PLI when the junction temperature exceeds 170°C ±10% . Hysteresis is around 30°C. When shutdown threshold is overcome, PLI interface is switched OFF . Thermal Shutdown event is notified to the HOST controller using BU/THERM line. When BU/THERM line is High, ST7540 junction temperature exceed the shutdown threshold (Not Latched). This function is enabled only in Transmission mode (in Receiving mode the BU/THERM pin is used for Band in Use signaling, see Band in Use function Section 7.1: Band in use). 7.9 5V Voltage regulator ST7540 has an embedded 5V linear regulator externally available (on pin VDC) to supply the application circuitry. The 5V linear regulator has a very low quiescent current (50µA) and a current capability of 50mA. The regulator is protected against short circuitry events. 7.10 3.3V Voltage regulator The VDD pin can act either as 3.3V Voltage Output or as Input Digital Supply. When the VDD pin is externally forced to 5V all the Digital I/Os operate at 5V, otherwise all the Digital I/Os are internally supplied at 3.3V. The V DD pin can also source 3.3V voltage to supply external components. The 3.3V linear regulator has a very low quiescent current (50µA) and a current capability of 50mA. The regulator is protected against short circuitry events.
7.11 Power-up procedure
To ensure ST7540 proper power-Up sequence, VCC and VDD Supply has to fulfil the following rules: 1. V CC rising slope must not exceed 100V/ms. 2. When V DD is below 5V/3.3V: VCC-VDD < 1.2V. When VDD supply is connected to VDC (5V Digital Supply) the above mentioned relation can be ignored if VDC load < 50mA and if the filtering capacitor on VDC < 100uF . If VDD is not forced to 5V, the Digital I/Os are internally supplied at 3.3 V and if VDD load < 50mA and the filtering capacitor on VDD < 100uF the second relation can be ignored .
Figure 24. Power-up sequence
Figure 25. Application schematic ex ample with coupling transformer.
5 Lines
8 Mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Table 13. HTSSOP28 Mechanical data Figure 26. Package dimensions
9 Revision history
Table 14. Revision history 15-Mar-2006 1 Initial release.