ST722311R6T7S

ST72311R STMICROELECTRONICS | Alldatasheet

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Rev. 2.1 February 2000 1/164 ST72311R, ST72511R, ST72512R, ST72532R 8-BIT MCU WITH NESTED INTERRUPTS, EEPROM, ADC, 16-BIT TIMERS, 8-BIT PWM ART, SPI, SCI, CAN INTERFACES DATASHEET n Memories – 16K to 60K bytes Program memory (ROM,OTP and EPROM) with read-out protection – 256 bytes E2PROM Data memory (only on ST72532R4) – 1024 to 2048 bytes RAM n Clock, Reset and Supply Management – Enhanced reset system – Low voltage supply supervisor – Clock sources: crystal/ceramic resonator os- cillator or external clock – Beep and Clock-out capability – 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow n Interrupt Management – Nested interrupt controller – 13 interrupt vectors plus TRAP and RESET – 15 external interrupt lines (on 4 vectors) – TLI dedicated top level interrupt pin n 48 I/O Ports – 48 multifunctional bidirectional I/O lines – 32 alternate function lines – 12 high sink outputs n 5 Timers – Configurable watchdog timer – Real time clock timer – One 8-bit auto-reload timer with 4 independ- ent PWM output channels, 2 input captures, output compares and external clock with event detector (except on ST725x2R4) – Two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input on one tim- er, PWM and Pulse generator modes n 3 Communications Interfaces – SPI synchronous serial interface – SCI asynchronous serial interface – CAN interface (except on ST72311Rx) n 1 Analog peripheral – 8-bit ADC with 8 input channels n Instruction Set – 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation n Development Tools – Full hardware/software development package Device Summary Note 1. See Section 12.3.1 on page 133 for more information on VDD versus fOSC . TQFP64 14 x 14 Features ST72511R9 ST72511R7 ST72511R6 ST72311R9 ST72311R7 ST72311R6 ST72512R4 ST72532R4 Program memory - bytes 60K 48K 32K 60K 48K 32K 16K 16K RAM (stack) - bytes 2048 (256) 1536 (256) 1024 (256) 2048 (256) 1536 (256) 1024 (256) 1024 (256) 1024 (256) EEPROM - bytes - - - --- -2 5 6 Peripherals watchdog, two 16-bit timers, 8-bit PWM ART, SPI, SCI, CAN, ADC watchdog, two 16-bit timers, 8-bit PWM ART, SPI, SCI, ADC watchdog, two 16-bit timers, SPI, SCI, CAN, ADC Operating Supply 3.0V to 5.5V 3.0 to 5.5V 1) CPU Frequency 2 to 8 MHz (with 4 to 16 MHz oscillator) 2 to 4 MHz 1) Operating Temperature -40 °C to +85°C (-40°C to +105/125°C optional)

ST72311R, ST72511R, ST72512R, ST72532R

ST72311R, ST72511R, ST72512R, ST72532R

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

plications but without CAN interface. is in idle or standby state. Figure 1. Device Block Diagram

1.2 PIN DESCRIPTION

Figure 2. 64-Pin TQFP Package Pinout

Refer to Section 8 ”I/O PORTS” on page 38 for more details on the software configuration of the I/O ports. Table 1. Device Pin Description

1 PE4 (HS) I/O C T HS X X X X Port E4

2 PE5 (HS) I/O C T HS X X X X Port E5

3 PE6 (HS) I/O C T HS X X X X Port E6

4 PE7 (HS) I/O C T HS X X X X Port E7

5 PB0/PWM3 I/O C T X ei2 X X Port B0 PWM Output 3

6 PB1/PWM2 I/O C T X ei2 X X Port B1 PWM Output 2

7 PB2/PWM1 I/O C T X ei2 X X Port B2 PWM Output 1

8 PB3/PWM0 I/O C T X ei2 X X Port B3 PWM Output 0

9 PB4/ARTCLK I/O C T X ei3 X X Port B4 PWM-ART External Clock

10 PB5 I/O C T X ei3 X X Port B5

11 PB6 I/O C T X ei3 X X Port B6

12 PB7 I/O C T X ei3 X X Port B7

13 PD0/AIN0 I/O C T X X X X X Port D0 ADC Analog Input 0

14 PD1/AIN1 I/O C T X X X X X Port D1 ADC Analog Input 1

15 PD2/AIN2 I/O C T X X X X X Port D2 ADC Analog Input 2

16 PD3/AIN3 I/O C T X X X X X Port D3 ADC Analog Input 3

17 PD4/AIN4 I/O C T X X X X X Port D4 ADC Analog Input 4

18 PD5/AIN5 I/O C T X X X X X Port D5 ADC Analog Input 5

19 PD6/AIN6 I/O C T X X X X X Port D6 ADC Analog Input 6

20 PD7/AIN7 I/O C T X X X X X Port D7 ADC Analog Input 7

21 V DDA S Analog Power Supply Voltage

22 V SSA S Analog Ground Voltage

23 V DD_3 S Digital Main Supply Voltage

ST72311R, ST72511R, ST72512R, ST72532R

24 V SS_3 S Digital Ground Voltage

25 PF0/MCO I/O C T X ei1 X X Port F0 Main clock output (f OSC /2)

26 PF1/BEEP I/O C T X ei1 X X Port F1 Beep signal output

27 PF2 I/O C T X ei1 X X Port F2

28 PF3/OCMP2_A I/O C T X X X X Port F3 Timer A Output Compare 2

29 PF4/OCMP1_A I/O C T X X X X Port F4 Timer A Output Compare 1

30 PF5/ICAP2_A I/O C T X X X X Port F5 Timer A Input Capture 2

31 PF6 (HS)/ICAP1_A I/O C T HS X X X X Port F6 Timer A Input Capture 1

32 PF7 (HS)/EXTCLK_A I/O C T HS X X X X Port F7 Timer A External Clock Source

33 V DD_0 S Digital Main Supply Voltage

34 V SS_0 S Digital Ground Voltage

35 PC0/OCMP2_B I/O C T X X X X Port C0 Timer B Output Compare 2

36 PC1/OCMP1_B I/O C T X X X X Port C1 Timer B Output Compare 1

37 PC2 (HS)/ICAP2_B I/O C T HS X X X X Port C2 Timer B Input Capture 2

38 PC3 (HS)/ICAP1_B I/O C T HS X X X X Port C3 Timer B Input Capture 1

39 PC4/MISO I/O C T X X X X Port C4 SPI Master In / Slave Out Data

40 PC5/MOSI I/O C T X X X X Port C5 SPI Master Out / Slave In Data

41 PC6/SCK I/O C T X X X X Port C6 SPI Serial Clock

42 PC7/SS I/O C T X X X X Port C7 SPI Slave Select (active low)

43 PA0 I/O C T X ei0 X X Port A0

44 PA1 I/O C T X ei0 X X Port A1

45 PA2 I/O C T X ei0 X X Port A2

46 PA3 I/O C T X ei0 X X Port A3

47 V DD_1 S Digital Main Supply Voltage

48 V SS_1 S Digital Ground Voltage

49 PA4 (HS) I/O C T HS X X X X Port A4

50 PA5 (HS) I/O C T HS X X X X Port A5

51 PA6 (HS) I/O C T HS X T Port A6

52 PA7 (HS) I/O C T HS X T Port A7

53 V PP I

Must be tied low in user mode. In programming mode when available, this pin acts as the pro- gramming voltage input V PP .

54 RESET I/O C X X Top priority non maskable interrupt (active low)

55 NC Not Connected

56 NMI I C

T X Non maskable interrupt input pin

57 V SS_3 S Digital Ground Voltage

58 OSC2 3) I/O External clock mode input pull-up or crystal/ce-

ramic resonator oscillator inverter output

59 OSC1 3) I External clock input or crystal/ceramic resona-

tor oscillator inverter input

60 V DD_3 S Digital Main Supply Voltage

Pin n° Pin Name Type Level Port Main function (after reset) Alternate function TQFP64 Input Output Input Output float wpu int ana OD PP

ST72311R, ST72511R, ST72512R, ST72532R Notes: 1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V DD are not implemented). See Section 8 ”I/O PORTS” on page 38 and Section 12.8 ”I/O PORT PIN CHAR- ACTERISTICS” on page 145 for more details. 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscillator see Section 1.2 ”PIN DESCRIPTION” on page 7 and Section 12.5 ”CLOCK AND TIMING CHARACTER- ISTICS” on page 138 for more details.

61 PE0/TDO I/O C T X X X X Port E0 SCI Transmit Data Out

62 PE1/RDI I/O C T X X X X Port E1 SCI Receive Data In

63 PE2/CANTX I/O C T X Port E2 CAN Transmit Data Output

64 PE3/CANRX I/O C T X X X X Port E3 CAN Receive Data Input

Pin n° Pin Name Type Level Port Main function (after reset) Alternate function TQFP64 Input Output Input Output float wpu int ana OD PP

1.3 REGISTER & MEMORY MAP

Figure 3. Memory Map

1024 Bytes RAM

2048 Bytes RAM

1536 Bytes RAM

16 KBytes

48 KBytes

32 KBytes

60 KBytes

Table 2. Hardware Register Map

ST72311R, ST72511R, ST72512R, ST72532R 002Ah 002Bh WATCHDOG WDGCR WDGSR Watchdog Control Register Watchdog Status Register 7Fh 000x 000x R/W R/W 002Ch EEPROM EECSR Data EEPROM Control/Status Register 00h R/W 002Dh to 0030h Reserved Area (4 Bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh TIMER A TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0040h MISCR2 Miscellaneous Register 2 00h R/W 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh TIMER B TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h SCI SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register C0h xxh 00xx xxxx xxh 00h 00h 00h Read Only R/W R/W R/W R/W R/W R/W Address Block Register Label Register Name Reset Status Remarks

ST72311R, ST72511R, ST72512R, ST72532R Legend : x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 0058h 0059h Reserved Area (2 Bytes) 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 006Fh CAN CANISR CANICR CANCSR CANBRPR CANBTR CANPSR CAN Interrupt Status Register CAN Interrupt Control Register CAN Control / Status Register CAN Baud Rate Prescaler Register CAN Bit Timing Register CAN Page Selection Register First address to Last address of CAN page X 00h 00h 00h 00h 23h 00h R/W R/W R/W R/W R/W R/W See CAN

Description

PWM AR Timer Duty Cycle Register 3 PWM AR Timer Duty Cycle Register 2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register 00h 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W 007Ah to 007Fh Reserved Area (6 Bytes) Address Block Register Label Register Name Reset Status Remarks

ST72311R, ST72511R, ST72512R, ST72532R

2 EPROM PROGRAM MEMORY

The program memory of the OTP and EPROM de- vices can be programmed with EPROM program- ming tools available from STMicroelectronics EPROM Erasure EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo cur- rent. It is recommended that the EPROM devices be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional fail- ure. Extended exposure to room level fluorescent lighting may also cause erasure. An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting con- ditions. Covering the window also reduces I DD in power-saving modes due to photo-diode leakage currents.

3 DATA EEPROM

3.1 INTRODUCTION

basic access protocol described in this chapter.

3.2 MAIN FEATURES

Figure 4. EEPROM Block Diagram

3.3 MEMORY ACCESS

put on the data bus in less than 1 CPU clock cycle. set by software (the PGM bit remains cleared). Significant Bits of the address can change. It is not possible to read the latched data. This note is ilustrated by the Figure 6. Figure 5. Data EEPROM Programming Flowchart

3.4 POWER SAVING MODES

function in progress, and data may be corrupted.

3.5 ACCESS ERROR HANDLING

data on the bus will not be latched. Figure 6. Data EEPROM Programming Cycle

3.6 REGISTER DESCRIPTION

Bit 7:3 = Reserved, forced by hardware to 0. only be cleared by software if PGM bit is cleared. Table 3. DATA EEPROM Register Map and Reset Values

00000 I E L A T P G M

4 CENTRAL PROCESSING UNIT

4.1 INTRODUCTION

4.2 MAIN FEATURES

4.3 CPU REGISTERS

(Program Counter High which is the MSB). Figure 7. CPU Registers

ST72311R, ST72511R, ST72512R, ST72532R CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions. These bits can be individually tested and/or con- trolled by specific instructions. Arithmetic management bits Bit 4 =H Half carry. This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: An half carry has occurred. This bit is tested using the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines. Bit 2 =N Negative. This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the re- sult 7 thbit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- tions. Bit 1 =Z Zero. This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 =C Carry/borrow. This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. Interrupt management bits Bit 5,3 =I1, I0 Interrupt. The combination of the Iand I0 bits gives the cur- rent interrupt software priority. These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software pri- ority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details.

11 I 1 H I 0 NZ C

Interrupt Software Priority I1 I0 Level 0 (main) 1 0 Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable) 1 1

ways pointing to the next free location in the stack. popped from the stack (see Figure 8). mented and the context is pushed on the stack. and the context is popped from the stack. terrupt five locations in the stack area. Figure 8. Stack Manipulation Example

5 SUPPLY, RESET AND CLOCK MANAGEMENT

nents. An overview is shown in Figure 9. Figure 9. Clock, RESET, Option and Supply Management Overview

5.1 LOW VOLTAGE DETECTOR (LVD)

well as the power-down keeping the ST7 in reset. ning and sinks current on the supply (hysteresis). The LVD function is illustrated in Figure 10. Figure 10. Low Voltage Detector vs Reset

5.2 RESET SEQUENCE MANAGER (RSM)

5.2.1 Introduction

ways kept low during the delay phase. dresses FFFEh-FFFFh in the ST7 memory map. taken place from the Reset state. Figure 11. RESET Sequence Phases Figure 12. Reset Block Diagram

4096 CLOCK CYCLES

5.2.2 Asynchronous External RESET pin

output with integrated RON weak pull-up resistor. electrical characteristics section for more details. can enter reset state even in HALT mode.

5.2.3 Internal Low Voltage Detection RESET

VDD <V IT-(falling edge) as shown in Figure 13.

5.2.4 Internal Watchdog RESET

Watchdog counter overflow is shown in Figure 13. gy to be used to drive external devices. Figure 13. RESET Sequences

5.3 LOW CONSUMPTION OSCILLATOR

the OSC1 pin while the OSC2 pin is tied to ground. output distortion and start-up stabilization time. Table 4. ST7 Clock Sources

6 INTERRUPTS

6.1 INTRODUCTION

FFFFh) sorted by hardware priority order. ed) ST7 interrupt controller.

6.2 MASKING AND PROCESSING FLOW

the current instruction execution. of the serviced interrupt vector. “Interrupt Mapping” table for vector addresses). saved registers to be recovered from the stack. and the program in the previous level will resume. Table 5. Interrupt Software Priority Levels Figure 14. Interrupt Processing Flowchart LOAD I1:0 FROM INTERRUPT SW REG.

6.3 INTERRUPTS AND LOW POWER MODES

after the first one serviced.

6.4 CONCURRENT & NESTED MANAGEMENT

tifying the software of the failure. Figure 16. Concurrent interrupt management Figure 17. Nested interrupt management

ST72311R, ST72511R, ST72512R, ST72532R INTERRUPTS (Cont’d)

6.5 INTERRUPT REGISTER DESCRIPTION

CPU CC REGISTER INTERRUPT BITS Read/Write Reset Value: 111x 1010 (xAh) Bit 5, 3 =I1, I0Software Interrupt Priority These two bits indicate the current interrupt soft- ware priority. These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software pri- ority registers (ISPRx). They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and PUSH/POP in- structions (see “Interrupt Dedicated Instruction Set” table). *Note: TLI, TRAP and RESET events are non maskable sources and can interrupt a level 3 pro- gram. INTERRUPT SOFTWARE PRIORITY REGIS- TERS (ISPRX) Read/Write (bit 7:4 ofISPR3 are read only) Reset Values: 1111 1111 (FFh) These four registers contain the interrupt software priority of each interrupt vector. – Each interrupt vector (except RESET and TRAP) has corresponding bits in these registers where its own software priority is stored. This corre- spondance is shown in the following table. – Each I1_x and I0_x bit value in the ISPRx regis- ters has the same meaning as the I1 and I0 bits in the CC register. – Level 0 can not be written (I1_x=1, I0_x=0). In this case, the previously stored value is kept. (ex- ample: previous=CFh, write=64h, result=44h) The RESET, TRAP and TLI vectors have no soft- ware priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. *Note: Bits in the ISPRx registers which corre- spond to the TLI can be read and written but they are not significant in the interrupt process man- agement. Caution: If the I1_x and I0_x bits are modified while the interrupt x is executed the following be- haviour has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and the new software priority is higher than the previ- ous one, the interrupt x is re-entered. Otherwise, the software priority stays unchanged up to the next interrupt request (after the IRET of the inter- rupt x).

11 I1 H I0 NZC

Interrupt Software Priority Level I1 I0 Level 0 (main) Low High Level 1 0 1 Level 2 0 0 Level 3 (= interrupt disable*) 1 1 ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0 ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4 ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8 ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12 Vector address ISPRx bits FFFBh-FFFAh I1_0 and I0_0 bits* FFF9h-FFF8h I1_1 and I0_1 bits FFE1h-FFE0h I1_13 and I0_13 bits

Table 6. Dedicated Interrupt Instruction Set software priority up to the next IRET instruction or one of the previously mentioned instructions. be used in an interrupt routine. Table 7. Interrupt Mapping

0 TLI External Top Level Interrupt MISCR2 yes FFFAh-FFFBh

1 MCC/RTC Main Clock Controller Time Base Interrupt MCCSR FFF8h-FFF9h

6 CAN CAN Peripheral Interrupts CANISR FFEEh-FFEFh

7 SPI SPI Peripheral Interrupts SPISR no FFECh-FFEDh

8 TIMER A TIMER A Peripheral Interrupts TASR FFEAh-FFEBh

9 TIMER B TIMER B Peripheral Interrupts TBSR FFE8h-FFE9h

10 SCI SCI Peripheral Interrupts SCISR FFE6h-FFE7h

11 EEPROM EEPROM Interrupt EECSR FFE4h-FFE5h

12 Not Used FFE2h-FFE3h

13 PWM ART PWM ART Overflow Interrupt ARTCSR Yes FFE0h-FFE1h

Table 8. Nested Interrupts Register Map and Reset Values

7 POWER SAVING MODES

7.1 INTRODUCTION

Figure 18. Power Saving Mode Transitions

7.2 SLOW MODE

the available supply voltage. Figure 19. SLOW Mode Clock Transitions

7.3 WAIT MODE

sumption mode by stopping the CPU. or an Interrupt occurs, causing it to wake up. Figure 20. WAIT Mode Flow-chart

4096 CPU CLOCK CYCLE

7.4 ACTIVE-HALT AND HALT MODES

enable flag (OIE bit in MCCSR register).

7.4.1 ACTIVE-HALT MODE

as external or auxiliary oscillator). HALT mode is provided by the oscillator interrupt. is active does not generate a RESET. than a defined delay in this power saving mode. Figure 21. ACTIVE-HALT Timing Overview Figure 22. ACTIVE-HALT Mode Flow-chart

0 HALT mode

1 ACTIVE-HALT mode

7.4.2 HALT MODE

tails on the MCCSR register).

4096 CPU cycle delay is used to stabilize the os-

the reset vector which woke it up (see Figure 24). cluding the operation of the on-chip peripherals. Section 14.1 on page 158 for more details). Figure 23. HALT Timing Overview Figure 24. HALT Mode Flow-chart

ST72311R, ST72511R, ST72512R, ST72532R

8 I/O PORTS

8.1 INTRODUCTION

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

8.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre- sponding register bits in the DDR and OR regis- ters: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not pro- vide this register refer to the I/O Port Implementa- tion section). The generic I/O block diagram is shown in Figure 25

8.2.1 Input Modes

The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external inter- rupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Mis- cellaneous register. Each external interrupt vector is linked to a dedi- cated group of I/O port pins (see pinout description and interrupt section). If several input pins are se- lected simultaneously as interrupt source, these are logically ANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configura- tion, special care must be taken when changing the configuration (see Figure 26). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellane- ous register must be modified.

8.2.2 Output Modes

The output configuration is selected by setting the corresponding DDR register bit. In this case, writ- ing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR reg- ister returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:

8.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip periph- eral, the I/O pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. DR Push-pull Open-drain 0V SS Vss 1V DD Floating

Figure 25. I/O Port General Block Diagram Table 9. I/O Port Mode Options vice against positive stress.

Table 10. I/O Port Configurations

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

1. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

8.3 I/O PORT IMPLEMENTATION

such as spurious interrupt generation. Figure 26. Interrupt I/O Port State Transitions

the CC register is not active (RIM instruction). Table 11. Port Configuration

• Note: when the CANTX alternate function is selected the IO port operates in output push-pull mode.

cause the device to exit from WAIT mode. cause the device to exit from HALT mode.

ST72311R, ST72511R, ST72512R, ST72532R I/O PORTS (Cont’d)

8.5.1 Register Description

DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C, D, E or F. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 =D[7:0]Data register 8 bits. The DR register has a specific behaviour accord- ing to the selected input/output configuration. Writ- ing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B, C, D, E or F. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 =DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B, C, D, E or F. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 =O[7:0]Option register 8 bits. For specific I/O pins, this register is not implement- ed. In this case the DDR register is enough to se- lect the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: pull-up input with or without interrupt Output mode: 0: output open drain (with P-Buffer unactivated) 1: output push-pull D7 D6 D5 D4 D3 D2 D1 D0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 O7 O6 O5 O4 O3 O2 O1 O0

Table 12. I/O Port Register Map and Reset Values

9 MISCELLANEOUS REGISTERS

9.1 I/O PORT INTERRUPT SENSITIVITY

9.2 I/O PORT ALTERNATE FUNCTIONS

port function while the SPI is active. Figure 27. External Interrupt Sources vs MISCR

ST72311R, ST72511R, ST72512R, ST72532R MISCELLANEOUS REGISTERS (Cont’d)

9.3 MISCELLANEOUS REGISTERS

MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h) Bit 7:6 =IS1[1:0]ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: - ei2 (port B3..0) - ei3 (port B7..4) These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 5 =MCO Main clock out selection This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled (fOSC /2on I/O port) Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode. Bit 4:3 =IS2[1:0]ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts: - ei0 (port A3..0) - ei1 (port F2..0) These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bit 2:1 =CP[1:0]CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software Bit 0 =SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC /2 1: Slow mode. fCPU is given by CP1, CP0 See Section 7.2 ”SLOW MODE” on page 34 and Section 10.2 ”MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)” on page 52 for more details. IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS IS11 IS10 External Interrupt Sensitivity MISCR2.IPB=0 MISCR2.IPB=1

00 Falling edge &

& high level 0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Rising and falling edge IS11 IS10 External Interrupt Sensitivity 0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge IS21 IS20 External Interrupt Sensitivity MISCR2.IPA=0 MISCR2.IPA=1 & high level 0 1 Rising edge only Falling edge only 1 0 Falling edge only Rising edge only 1 1 Rising and falling edge IS21 IS20 External Interrupt Sensitivity 0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge f CPU in SLOW mode CP1 CP0 fOSC /4 0 0 fOSC /8 1 0 fOSC /1 6 0 1 fOSC /3 2 1 1

ST72311R, ST72511R, ST72512R, ST72532R MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read/Write Reset Value: 0000 0000 (00h) Bit 7 =IPA Interrupt polarity for port A This bit is used to invert the sensitivity of the port A [3:0] external interrupts. It is set and cleared by software. 0: No sensitivity inversion 1: Sensitivity inversion See Section 9.1 ”I/O PORT INTERRUPT SENSI- TIVITY” on page 45 and the description of the IS2x bits of the MISCR1 register for more details. Bit 6 =IPB Interrupt polarity for port B This bit is used to invert the sensitivity of the port B [3:0] external interrupts. It is set and cleared by software. 0: No sensitivity inversion 1: Sensitivity inversion See Section 9.1 ”I/O PORT INTERRUPT SENSI- TIVITY” on page 45 and the description of the IS1x bits of the MISCR1 register for more details. Bit 5:4 =BC[1:0] Beep control These 2 bits select the PF1 pin beep capability. The beep output signal is available in ACTIVE- HALT mode but has to be disabled to reduce the consumption. Bit 3 =TLIS TLI sensitivity This bit allows to toggle the TLI edge sensitivity. It can be set and cleared by software only when TLIE bit is cleared. 0: Falling edge 1: Rising edge Bit 2 =TLIE TLI enable This bit allows to enable or disable the TLI capabil- ity on the dedicated pin. It is set and cleared by software. 0: TLI disabled 1: TLI enabled Note: a parasitic interrupt can be generated when clearing the TLIE bit. Bit 1 =SSM SS mode selection This bit is set and cleared by software. 0: Normal mode - the level of the SPI SS signal is input from the external SS pin. 1: I/O mode (PC7), the level of the SPI SS signal is read from the SSI bit. Bit 0 =SSI SS internal mode This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description). It is set and cleared by software. IPA IPB BC1 BC0 TLIS TLIE SSM SSI BC1 BC0 Beep mode with f OSC =16MHz 0 0 Off 0 1 ~2-KHz Output Beep signal ~50% duty cycle 1 0 ~1-KHz 1 1 ~500-Hz

Table 13. Miscellaneous Register Map and Reset Values

10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

10.1.2 Main Features

10.1.3 Functional Description

programmed by the user in 64 increments. Figure 28. Watchdog Block Diagram

ST72311R, ST72511R, ST72512R, ST72532R WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 14 .Watchdog Timing (fCPU = 8 MHz)): – The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme- diate reset – The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 14.Watchdog Timing (f CPU = 8 MHz) Notes: Following a reset, the watchdog is disa- bled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software re- set (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset.

10.1.4 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the device-specific Option Byte descrip- tion.

10.1.5 Low Power Modes

10.1.6 Interrupts

None.

10.1.7 Register Description

CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh) Bit 7 =WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note:This bit is not used if the hardware watch- dog option is enabled by option byte. Bit 6:0 =T[6:0]7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). STATUS REGISTER (SR) Read/Write Reset Value*: 0000 0000 (00h) Bit 0 =WDOGF Watchdog flag. This bit is set by a watchdog reset and cleared by software or a power on/off reset. This bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: No Watchdog reset occurred 1: Watchdog reset occurred * Only by software and power on/off reset Note:This register is not used in versions without LVD Reset. CR Register initial value WDG timeout period (ms) Max FFh 98.304 Min C0h 1.536 Mode Description WAIT No effect on Watchdog. HALT Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated (WDGA bit is set). WDGA T6 T5 T4 T3 T2 T1 T0 - - - - - - - WDOGF

Table 15. Watchdog Timer Register Map and Reset Values

10.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)

10.2.1 Programmable CPU Clock Prescaler

10.2.2 Clock-out Capability

pends the clock during ACTIVE-HALT mode.

10.2.3 Real Time Clock Timer (RTC)

register: TB[1:0], OIE and OIF. Figure 29. Main Clock Controller (MCC/RTC) Block Diagram

10.2.4 Register Description

See “MISCELLANEOUS REGISTERS” Section. Bit 7:4 = Reserved, always read as 0. base. They are set and cleared by software. use this time base as a real time clock. This bit set and cleared by software. unintentionally clearing the OIF bit.

10.2.5 Low Power Modes

10.2.6 Interrupts

1. The MCC/RTC interrupt allows to exit from AC-

TIVE-HALT mode, not from HALT mode. Table 16. MCC/RTC Register Map and Reset Values

0000 T B 1 T B 0 O I E O I F

No effect on MCC/RTC peripheral. set), the registers are frozen. MCC/RTC counter and registers are frozen.

10.3 PWM AUTO-RELOAD TIMER (ART)

10.3.1 Introduction

Figure 30. PWM Auto-Reload Timer Block Diagram

10.3.2 Functional Description

ing edge of the clock signal. ARR register (the prescaler is not affected). the fCPU or an external input frequency fEXT . the prescaler and counter contents are frozen. (Timer Counter Enable) bits in the CSR register. whereupon counting will start from a known value. Direct access to the prescaler is not possible. ation when changing the duty cycle on the fly. Figure 31. Output compare control

counted before setting the OVF flag. an interrupt which wakes up the MCU. Figure 34. External Event Detector Example (3 counts)

ST72311R, ST72511R, ST72512R, ST72532R PWM AUTO-RELOAD TIMER (Cont’d)

10.3.3 Register Description

CONTROL / STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) Bit 7 =EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: CPU clock. 1: External clock. Bit 6:4 =CC[2:0] Counter Clock Control These bits are set and cleared by software. They determine the prescaler division ratio from fINPUT . Bit 3 =TCE Timer Counter Enable This bit is set and cleared by software. It puts the timer in the lowest power consumption mode. 0: Counter stopped (prescaler and counter frozen). 1: Counter running. Bit 2 =FCRL Force Counter Re-Load This bit is write-only and any attempt to read it will yield a logicalzero. When set, it causesthe contents of ARR register to be loaded into the counter, and the content of the prescaler register to be cleared in order to initialize the timer before starting to count. Bit 1 =OIE Overflow Interrupt Enable This bit is set and cleared by software. It allows to enable/disable the interrupt which is generated when the OVF bit is set. 0: Overflow Interrupt disable. 1: Overflow Interrupt enable. Bit 0 =OVF Overflow Flag This bit is set by hardware and cleared by software reading the CSR register. It indicates the transition of the counter from FFh to the ARR value. 0: New transition not yet reached 1: Transition reached COUNTER ACCESS REGISTER (CAR) Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 =CA[7:0] Counter Access Data These bits can be set and cleared either by hard- ware or by software. The CAR register is used to read or write the auto-reload counter “on the fly” (while it is counting). AUTO-RELOAD REGISTER (ARR) Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 =AR[7:0]Counter Auto-Reload Data These bits are set and cleared by software. They are used to hold the auto-reload value which is au- tomatically loaded in the counter when an overflow occurs. At the same time, the PWM output levels are changed according to the corresponding OPx bit in the PWMCR register. This register has two PWM management func- tions: – Adjusting the PWM frequency – Setting the PWM duty cycle resolution PWM Frequency vs. Resolution: EXCL CC2 CC1 CC0 TCE FCRL OIE OVF fCOUNTER With fINPUT =8 MHz CC2 CC1 CC0 fINPUT fINPUT /2 fINPUT /4 fINPUT /8 fINPUT /1 6 fINPUT /3 2 fINPUT /6 4 fINPUT / 128

8 MHz

4 MHz

2 MHz

1 MHz

500 KHz

250 KHz

125 KHz

62.5 KHz

CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 ARR value Resolution fPWM Min Max 0 8-bit ~0.244-KHz 31.25-KHz

ST72311R, ST72511R, ST72512R, ST72532R PWM AUTO-RELOAD TIMER (Cont’d) PWM CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h) Bit 7:4 =OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels inde- pendently acting on the corresponding I/O pin. 0: PWM output disabled. 1: PWM output enabled. Bit 3:0 =OP[3:0] PWM Output Polarity These bits are set and cleared by software. They independently select the polarity of the four PWM output signals. Note: When an OPx bit is modified, the PWMx out- put signal polarity is immediately reversed. DUTY CYCLE REGISTERS (DCRx) Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 =DC[7:0] Duty Cycle Data These bits are set and cleared by software. A DCRx register is associated with the OCRx reg- ister of each PWM channel to determine the sec- ond edge location of the PWM signal (the first edge location is common to all channels and given by the ARR register). These DCR registers allow the duty cycle to be set independently for each PWM channel. OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0 PWMx output level OPx Counter <= OCRx Counter > OCRx 10 0 01 1 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0

Table 17. PWM Auto-Reload Timer Register Map and Reset Values

ST72311R, ST72511R, ST72512R, ST72532R 10.4 16-BIT TIMER

10.4.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement of up to two input sig- nals (input capture) or generation of up to two out- put waveforms (output compareand PWM ). Pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequen- cies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).

10.4.2 Main Features

n Programmable prescaler: fCPU dividedby2, 4or 8. n Overflow status flag and maskable interrupt n External clock input (must be at least 4 times slower thanthe CPUclock speed) with the choice of active edge n Output compare functions with – 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt n Input capture functions with – 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt n Pulse width modulation mode (PWM) n One pulse mode n 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 35. *Note:Some timer pins may not available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be ‘1’.

10.4.3 Functional Description

10.4.3.1 Counter

The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): – Counter High Register (CHR) is the most sig- nificant byte (MS Byte). – Counter Low Register (CLR) is the least sig- nificant byte (LS Byte). Alternate Counter Register (ACR) – Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). – Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register, (SR), (see note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit tim- er). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 18 Clock Control Bits. The value in the counter register re- peats every 131.072, 262.144 or 524.288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be f CPU /2, fCPU /4, fCPU /8 or an external frequency.

Figure 35. Timer Block Diagram

ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER(Cont’d) 16-bit read sequence:(from either the Counter Register or the Alternate Counter Register). The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they re- turn the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, out- put compare, one pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: – The TOF bit of the SR register is set. – A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Notes:The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

10.4.3.2 External Clock

The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the exter- nal clock pin EXTCLK that will trigger the free run- ning counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the CPU clock frequency. is buffered Read At t0 Read Returns the buffered LS Byte value at t0At t0 +Δt Other instructions Beginning of the sequence Sequence completed LS Byte LS Byte MS Byte

ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER(Cont’d)

10.4.3.3 Input Capture

In this section, the index,i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter after a transition detected by the ICAP ipin (see figure 5). ICiR register is a read-only register. The active transition is software programmable through the IEDGibit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU /CC[1:0]). Procedure: To use the input capture function select the follow- ing in the CR2 register: – Select the timer clock (CC[1:0]) (see Table 18 Clock Control Bits). – Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as floating input). And select the following in the CR1 register: – Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as floating input). When an input capture occurs: – ICFibit is set. – The ICiR register contains the value of the free running counter on the active transition on the ICAP ipin (see Figure 40). – A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Other- wise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICF ibit) is done in two steps: 1. Reading the SR register while the ICFibit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One pulse Mode and PWM mode only the input capture 2 can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input cap- ture function. Moreover if one of the ICAP ipin is configured as an input and the second one as an output, an interrupt can be generated if the user toggle the output pin and if the ICIE bit is set. This can be avoided if the input capture func- tion iis disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with interrupt in order to measure event that go beyond the timer range (FFFFh). MS Byte LS Byte ICiR IC iHR IC iLR

ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER(Cont’d)

10.4.3.4 Output Compare

In this section, the index,i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Com- pare register and the free running counter, the out- put compare function: – Assigns pins with a programmable value if the OCIE bit is set – Sets a flag in the status register – Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC iR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/ CC[1:0]). Procedure: To use the output compare function, select the fol- lowing in the CR2 register: – Set the OCiE bit if an output is needed then the OCMP ipin is dedicated to the output comparei signal. – Select the timer clock (CC[1:0]) (see Table 18 Clock Control Bits). And select the following in the CR1 register: – Select the OLVLibit to applied to the OCMPipins after the match occurs. – Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: – OCF ibit is set. – The OCMP ipin takes OLVLibit value (OCMPi pin latch is forced low during reset). – A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). The OCiR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: Δt = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 de- pending on CC[1:0] bits, see Table 18 Clock Control Bits) If the timer clock is an external clock, the formula is: Where: Δt = Output compare period (in seconds) fEXT = External timer clock frequency (in hertz) Clearing the output compare interrupt request (i.e. clearing the OCFibit) is done by: 1. Reading the SR register while the OCFibit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to pre- vent the OCFibit from being set between the time it is read and the write to the OCiR register: – Write to the OCiHR register (further compares are inhibited). – Read the SR register (first step of the clearance of the OCFibit, which may be already set). – Write to the OCiLR register (enables the output compare function and clears the OCFibit). MS Byte LS Byte OC iRO C iHR OC iLR Δ OC iR= Δt* fCPU PRESC Δ OC iR= Δ t* fEXT

1. After a processor write cycle to the OCiHR reg-

until the OCiLR register is also written.

1. If the OCiE bit is not set, the OCMPipin is a

could be generated if the OCIE bit is set.

1. When the timer clock is fCPU /2, OCFi and

ter value plus 1 (see Figure 43 on page 68).

1. The output compare functions can be used both
2. The value in the 16-bit OC

waveform or establish a new elapsed timeout. Figure 41. Output Compare Block Diagram

16 BIT FREE RUNNING

ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER(Cont’d)

10.4.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The one pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use one pulse mode: 1. Load the OC1R register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded- icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 18 Clock Control Bits). Then, on a valid event on the ICAP1 pin, the coun- ter is initialized to FFFCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the val- ue FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the Input Capture interrupt request (i.e. clearing the ICF ibit) is done in two steps: 1. Reading the SR register while the ICFibit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the fol- lowing formula: Where: t = Pulse period (in seconds) f CPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depend- ing on the CC[1:0] bits, see Table 18 Clock Control Bits) If the timer clock is an external clock the formula is: Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin, (See Figure 44). Notes: 1. The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When one pulse mode is used OC1R is dedi- cated to this mode. Nevertheless OC2R and OCF2 can be used to indicate a period of time has been elapsed but cannot generate an out- put waveform because the level OLVL2 is dedi- cated to the one pulse mode. event occurs Counter = OC1R OCMP1 = OLVL1 When When on ICAP1 One pulse mode cycle OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set OC iR Value = t*fCPU PRESC OC iR= t* fEXT -5

ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER(Cont’d)

10.4.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The pulse width modulation mode uses the com- plete Output Compare 1 function plus the OC2R register, and so these functionality can not be used when the PWM mode is activated. Procedure To use pulse width modulation mode: 1. Load the OC2R register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corre- sponding to the period of the pulse if (OLVL1=0 and OLVL2=1) using the formula in the oppo- site column. 3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after a successful comparison with OC1R register. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat- ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 18 Clock Control Bits). If OLVL1=1 and OLVL2=0 the length of the posi- tive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OC iR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depend- ing on CC[1:0] bits, see Table 18 Clock Control Bits) If the timer clock is an external clock the formula is: Where: t = Signal or pulse period (in seconds) f EXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 45) Notes: 1. After a write instruction to the OC iHR register, the output compare function is inhibited until the OC iLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the coun- ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is discon- nected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse Mode (OPM) bits are both set, the PWM mode is the only active one. Counter OCMP1 = OLVL2 Counter = OC2R OCMP1 = OLVL1 When When = OC1R Pulse Width Modulation cycle Counter is reset to FFFCh ICF1 bit is set OC iR Value = t*fCPU PRESC OC iR= t* fEXT -5

ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER(Cont’d)

10.4.4 Low Power Modes

10.4.5 Interrupts

Note:The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap- ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). 2) See note 5 in Section 10.4.3.5 ”One Pulse Mode” on page 69 3) See note 4 in Section 10.4.3.6 ”Pulse Width Modulation Mode” on page 71 Mode Description WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. HALT 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAP ipin, the input capture detection circuitry is armed. Consequent- ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFibit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE Yes No Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 OCIE Yes No Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes No MODES AVAILABLE RESOURCES Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) Yes Yes Yes Yes One Pulse Mode No Not Recommended 1) No Partially 2) PWM Mode No Not Recommended 3) No No

ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER(Cont’d)

10.4.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) Bit 7 =ICIEInput Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 =OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 =TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 =FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 =FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no suc- cessful comparison. Bit 2 =OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg- ister and OCxE is set in the CR2 register. This val- ue is copied to the OCMP1 pin in One Pulse Mode and Pulse Width Modulation mode. Bit 1 =IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 =OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin when- ever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Output Compare 1 Pin Enable. free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Output Compare 2 Pin Enable. free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. 0: One Pulse Mode is not active. contents of the OC1R register. Table 18. Clock Control Bits on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER(Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. Bit 7 =ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 =OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) reg- ister. Bit 5 =TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR reg- ister, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 =ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 =OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter has matched the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) reg- ister. Bit 2-0 = Reserved, forced by hardware to 0. INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. ICF1 OCF1 TOF ICF2 OCF2 0 0 0 70 MSB LSB MSB LSB MSB LSB MSB LSB

ST72311R, ST72511R, ST72512R, ST72532R 16-BIT TIMER(Cont’d) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit. ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register. INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event). INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the In- put Capture 2 event). MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

Table 19. 16-Bit Timer Register Map and Reset Values

10.5 SERIAL PERIPHERAL INTERFACE (SPI)

10.5.1 Introduction

which devices may be either masters or slaves.

10.5.2 Main Features

n Maximum slave mode frequency = fCPU/2. n Master mode fault protection capability.

10.5.3 General description

must be programmed with the same timing mode. Figure 46. Serial Peripheral Interface Master/Slave

Figure 47. Serial Peripheral Interface Block Diagram

ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4 Functional Description

Figure 46 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer to the CR, SR and DR registers in Section 10.5.7for the bit definitions.

10.5.4.1 Master Configuration

In a master configuration, the serial clock is gener- ated on the SCK pin. Procedure – Select the SPR0 & SPR1 bits to define the se- rial clock baud rate (see CR register). – Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 49). – The SS pin must be connected to a high level signal during the complete byte transmit se- quence. – The MSTR and SPE bits must be set (they re- main set only if the SS pin is connected to a high level signal). In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is writ- ten the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A write or a read of the DR register. Note:While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.

ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4.2 Slave Configuration

In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – For correct data transfer, the slave device must be in the same timing mode as the mas- ter device (CPOL and CPHA bits). See Figure 49. – The SS pin must be connected to a low level signal during the complete byte transmit se- quence. – Clear the MSTR bit and set the SPE bit to as- sign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2. A write or a read of the DR register. Notes:While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 10.5.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 10.5.4.4).

10.5.4.3 Data Transfer Format

ed do not interfere with the SPI transfer. by software, using the CPOL and CPHA bits. master and the slave device. be driven by the master device. clock edge before the capture clock edge. the occurrence of the second clock transition. currence of the first clock transition. each byte transmitted (see Figure 48). Figure 48. CPHA / SS Timing Diagram

Figure 49. Data Clock Timing Diagram Note:This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

10.5.4.4 Write Collision Error

the software write will be unsuccessful. nal MISO pin of the slave device. (SCK) is in the process of transfer. is set (the WCOL bit is a status flag only). Figure 50. Clearing the WCOL bit (Write Collision Flag) Software Sequence

ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.4.5 Master Mode Fault

Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. – The SPE bit is reset. This blocks all output from the device and disables the SPI periph- eral. – The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes:To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing se- quence of the MODF bit. The SPE and MSTR bits may be restored to their original state during or af- ter this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine.

10.5.4.6 Overrun Condition

An overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripher- al.

10.5.4.7 Single Master and Multimaster Configurations

the four SS pins of the slave devices. that time, thus disabling the slave devices. through the serial peripheral interface system. Figure 51. Single Master Configuration

ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d)

10.5.5 Low Power Modes

10.5.6 Interrupts

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Transfer Event SPIF SPIE Yes No Master Mode Fault Event MODF Yes No

10.5.7 Register Description

Serial peripheral interrupt enable. This bit is set and cleared by software. Bit 6 =SPE Serial peripheral output enable. eral is not initially connected to the external pins. set the baud rate. Refer to Table 20. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. This bit is set and cleared by software. Bit 1:0 =SPR[1 :0]Serial peripheral rate. These 2 bits have no effect in slave mode. Table 20. Serial Peripheral Baud Rate

ST72311R, ST72511R, ST72512R, ST72532R SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) Bit 7 =SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a soft- ware sequence (an access to the SR register fol- lowed by a read or write to the DR register). 0: Data transfer is in progress or has been ap- proved by a clearing sequence. 1: Data transfer between the device and an exter- nal device has been completed. Note:While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 =WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 50). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 =MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 10.5.4.5 ”Master Mode Fault” on page 85). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An ac- cess to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused. DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/re- ception of another byte. Notes:During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A write to the the DR register returns the value lo- cated in the buffer and not the contents of the shift register (See Figure 47 ). SPIF WCOL - MODF - - - - D7 D6 D5 D4 D3 D2 D1 D0

Table 21. SPI Register Map and Reset Values

ST72311R, ST72511R, ST72512R, ST72532R

10.6 SERIAL COMMUNICATIONS INTERFACE (SCI)

10.6.1 Introduction

The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI of- fers a very wide range of baud rates using two baud rate generator systems.

10.6.2 Main Features

n Full duplex, asynchronous communications n NRZ standard format (Mark/Space) n Dual baud rate generator systems n Independently programmable transmit and receive baud rates up to 250K baud. n Programmable data word length (8 or 9 bits) n Receive buffer full, Transmit buffer empty and End of Transmission flags n Two receiver wake-up modes: – Address bit (MSB) – Idle line n Muting functionfor multiprocessor configurations n Separate enable bits for Transmitter and Receiver n Three error detection flags: – Overrun error – Noise error – Frame error n Five interrupt sources with flags: – Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected

10.6.3 General Description

The interface is externally connected to another device by two pins (see Figure 53): – TDO: Transmit Data Output. When the transmit- ter is disabled, the output pin returns to its I/O port configuration. When the transmitter is ena- bled and nothing is to be transmitted, the TDO pin is at high level. – RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. Through this pins, serial data is transmitted and re- ceived as frames comprising: – An Idle Line prior to transmission or reception – A start bit – A data word (8 or 9 bits) least significant bit first – A Stop bit indicating that the frame is complete. This interface usestwo typesofbaud rategenerator: – A conventional type for commonly-used baud rates, – An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies.

Figure 52. SCI Block Diagram

10.6.4 Functional Description

10.6.7for the definitions of each bit.

10.6.4.1 Serial Data Format

The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. tra “1” bit to acknowledge the start bit. Figure 53. Word length programming

ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.2 Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the CR1 reg- ister. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the DR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 52). Procedure – Select the M bit to define the word length. – Select the desired baud rate using the BRR and the ETPR registers. – Set the TE bit to assign the TDO pin to the alter- nate function and to send a idle frame as first transmission. – Access the SR register and write the data to send in the DR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SR register 2. A write to the DR register The TDRE bit is set by hardware and it indicates: – The TDR register is empty. – The data transfer is beginning. – The next data can be written in the DR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write in- struction to the DR register stores the data in the TDR register and which is copied in the shift regis- ter at the end of the current transmission. When no transmission is taking place, a write in- struction to the DR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: 1. An access to the SR register 2. A write to the DR register Note:The TDRE and TC bits are cleared by the same software sequence. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 53). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a trans- mission sends an idle frame after the current word. Note:Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the DR.

ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.3 Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 reg- ister. Character reception During a SCI reception, data shifts in least signifi- cant bit first through the RDI pin. In this mode, DR register consists in a buffer (RDR) between the in- ternal bus and the received shift register (see Fig- ure 52). Procedure – Select the M bit to define the word length. – Select the desired baud rate using the BRR and the ERPR registers. – Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: – The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. – An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. – The error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SR register 2. A read to the DR register. The RDRF bit must be cleared before the endof the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SPI han- dles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ILIE bit is set and the I bit is cleared in the CCR register. Overrun Error An overrun error occurs when a character is re- ceived when RDRF has not been reset. Data can not be transferred from the shift register to the TDR register as long as the RDRF bit is not cleared. When a overrun error occurs: – The OR bit is set. – The RDR content will not be lost. – The shift register will be overwritten. – An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SR register followed by a DR register read operation. Noise Error Oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. When noise is detected in a frame: – The NF is set at the rising edge of the RDRF bit. – Data is transferred from the Shift register to the DR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF bit is reset by a SR register read operation followed by a DR register read operation. Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the DR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SR register read operation followed by a DR register read operation.

Figure 54. SCI Baud Rate and Extended Prescaler Block Diagram

ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.4.4 Conventional Baud Rate Generation

The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: with: PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits) (see SCT0, SCT1 & SCT2 bits) (see SCR0,SCR1 & SCR2 bits) All this bits are in the BRR register. Example: If f CPU is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and receive baud rates are 19200 baud. Note: the baud rate registers MUST NOT be changed while the transmitter or the receiver is en- abled.

10.6.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional Baud Rate Genera- tor retains industry standard software compatibili- ty. The extended baud rate generator block diagram is described in the Figure 54. The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the ERPR or the ETPR register. Note: the extended prescaler is activated by set- ting the ETPR or ERPR register to a value other than zero. The baud rates are calculated as fol- lows: with: ETPR = 1,..,255 (see ETPR register) ERPR = 1,.. 255 (see ERPR register)

10.6.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. The non addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode: All the reception status bits can not be set. All the receive interrupt are inhibited. A muted receiver may be awakened by one of the following two ways: – by Idle Line detection if the WAKE bit is reset, – by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an ad- dress. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. Tx = (32 *PR)*TR fCPU Rx = (32*PR)*RR fCPU Tx = 16*ETPR fCPU Rx = 16*ERPR fCPU

ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.5 Low Power Modes

10.6.6 Interrupts

The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corre- sponding Enable Control Bit is set and the inter- rupt mask in the CC register is reset (RIM instruc- tion). Mode Description WAIT No effect on SCI. SCI interrupts cause the device to exit from Wait mode. HALT SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Transmit Data Register Empty TDRE TIE Yes No Transmission Complete TC TCIE Yes No Received Data Ready to be Read RDRF RIE Yes No Overrrun Error Detected OR Yes No Idle Line Detected IDLE ILIE Yes No

ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d)

10.6.7 Register Description

STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) Bit 7 =TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE =1 in the CR2 register. It is cleared by a software se- quence (an access to the SR register followed by a write to the DR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Note: data will not be transferred to the shift regis- ter as long as the TDRE bit is not reset. Bit 6 =TC Transmission complete. This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generated if TCIE=1 in the CR2 register. It is cleared by a software se- quence (an access to the SR register followed by a write to the DR register). 0: Transmission is not complete 1: Transmission is complete Bit 5 =RDRF Received data ready flag. This bit is set by hardware when the content of the RDR register has been transferred into the DR register. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by hardware when RE=0 or by a software sequence (an access to the SR register followed by a read to the DR register). 0: Data is not received 1: Received data is ready to be read Bit 4 =IDLE Idle line detect. This bit is set by hardware when a Idle Line is de- tected. An interrupt is generated if the ILIE=1 in the CR2 register. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Idle Line is detected 1: Idle Line is detected Note:The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line oc- curs). This bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. Bit 3 =OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the CR2 reg- ister. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Overrun error 1: Overrun error is detected Note:When this bit is set RDR register content will not be lost but the shift register will be overwritten. Bit 2 =NF Noise flag. This bit is set by hardware when noise is detected on a received frame. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR regis- ter). 0: No noise is detected 1: Noise is detected Note:This bit does not generate interrupt as it ap- pears at the same time as the RDRF bit which it- self generates an interrupt. Bit 1 =FE Framing error. This bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. It is cleared by hardware when RE=0 by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Framing error is detected 1: Framing error or break character is detected Note:This bit does not generate interrupt as it ap- pears at the same time as the RDRF bit which it- self generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Bit 0 = Unused. TDRE TC RDRF IDLE OR NF FE -

ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined Bit 7 =R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 =T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmit- ted word when M=1. Bit 4 =M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Bit 3 =WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle Line 1: Address Mark CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) Bit 7 =TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE=1 in the SR register. Bit 6 =TCIE Transmission complete interrupt ena- ble This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever TC=1 in the SR register Bit 5 =RIE Receiver interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SR register Bit 4 =ILIEIdle line interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SR register. Bit 3 =TE Transmitter enable. This bit enables the transmitter and assigns the TDO pin to the alternate function. It is set and cleared by software. 0: Transmitter is disabled, the TDO pin is back to the I/O port configuration. 1: Transmitter is enabled Note:during transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble after the current word. Bit 2 =RE Receiver enable. This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled, it resets the RDRF, IDLE, OR, NF and FE bits of the SR register. 1: Receiver is enabled and begins searching for a start bit. Bit 1 =RWU Receiver wake-up. This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in active mode 1: Receiver in mute mode Bit 0 =SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted Note:If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word. R8 T8 - M WAKE - - - TIE TCIE RIE ILIE TE RE RWU SBK

ST72311R, ST72511R, ST72512R, ST72532R SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift reg- ister (see Figure 52). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 52). BAUD RATE REGISTER (BRR) Read/Write Reset Value: 00xx xxxx (XXh) Bit 7:6=SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges: Bit 5:3 =SCT[2:0]SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al Baud Rate Generator mode. Note:this TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR is replaced by the ETPR dividing factor. Bit 2:0 =SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode. Note:this RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR is replaced by the ERPR dividing factor. DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 PR Prescaling factor SCP1 SCP0 10 0 30 1 41 0 13 1 1 TR dividing factor SCT2 SCT1 SCT0 1 000 2 001 4 010 8 011 1 6 100 3 2 101 6 4 110 128 1 1 1 RR dividing factor SCR2 SCR1 SCR0 1 000 2 001 4 010 8 011 1 6 100 3 2 101 6 4 110 128 1 1 1

sion factor for the receive circuit. sion factor for the transmit circuit. Table 22. SCI Register Map and Reset Values

10.7 CONTROLLER AREA NETWORK (CAN)

10.7.1 Introduction

frames which are recognized but never initiated. Figure 55. CAN Block Diagram

10 Bytes

4 Bytes

ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d)

10.7.2 Main Features

– Support of CAN specification 2.0A and 2.0B pas- sive – Three prioritized 10-byte Transmit/Receive mes- sage buffers – Two programmable global 12-bit message ac- ceptance filters – Programmable baud rates up to 1 MBit/s – Buffer flip-flopping capability in transmission – Maskable interrupts for transmit, receive (one per buffer), error and wake-up – Automatic low-power mode after 20 recessive bits or on demand (standby mode) – Interrupt-driven wake-up from standby mode upon reception of dominant pulse – Optional dominant pulse transmission on leaving standby mode – Automatic message queuing for transmission upon writing of data byte 7 – Programmable loop-back mode for self-test op- eration – Advanced error detection and diagnosis func- tions – Software-efficient buffer mapping at a unique ad- dress space – Scalable architecture.

10.7.3 Functional Description

10.7.3.1 Frame Formats

A summary of all the CAN frame formats is given in Figure 56 for reference. It covers only the stand- ard frame format since the extended one is only acknowledged. A message begins with a start bit called Start Of Frame (SOF). This bit is followed by the arbitration field which contains the 11-bit identifier (ID) and the Remote Transmission Request bit (RTR). The RTR bit indicates whether it is a data frame or a re- mote request frame. A remote request frame does not have any data byte. The control field contains the Identifier Extension bit (IDE), which indicates standard or extended format, a reserved bit (ro) and, in the last four bits, a count of the data bytes (DLC). The data field ranges from zero to eight bytes and is followed by the Cyclic Redundancy Check (CRC) used as a frame integrity check for detecting bit errors. The acknowledgement (ACK) field comprises the ACK slot and the ACK delimiter. The bit in the ACK slot is placed on the bus by the transmitter as a re- cessive bit (logical 1). It is overwritten as a domi- nant bit (logical 0) by those receivers which have at this time received the data correctly. In this way, the transmitting node can be assured that at least one receiver has correctly received its message. Note that messages are acknowledged by the re- ceivers regardless of the outcome of the accept- ance test. The end of the message is indicated by the End Of Frame (EOF). The intermission field defines the minimum number of bit periods separating con- secutive messages. If there is no subsequent bus access by any station, the bus remains idle.

10.7.3.2 Hardware Blocks

The CAN controller contains the following func- tional blocks (refer to Figure 55): – ST7 Interface: buffering of the ST7 internal bus and address decoding of the CAN registers. – TX/RX Buffers: three 10-byte buffers for trans- mission and reception of maximum length mes- sages. – ID Filters: two 12-bit compare and don’t care masks for message acceptance filtering. – PSR: page selection register (see memory map). – BRPR: clock divider for different data rates. – BTR: bit timing register. – ICR: interrupt control register. – ISR: interrupt status register. – CSR: general purpose control/status register. – TECR: transmit error counter register. – RECR: receive error counter register. – BTL: bit timing logic providing programmable bit sampling and bit clock generation for synchroni- zation of the controller. – BCDL: bit coding logic generating a NRZ-coded datastream with stuff bits. – SHREG: 8-bit shift register for serialization of data to be transmitted and parallelisation of re- ceived data. – CRC: 15-bit CRC calculator and checker. – EML: error detection and management logic. – CAN Core: CAN 2.0B passive protocol control- ler.

Figure 56. CAN Frames

3 Transmission

• 0 <= N <= 8
• SOF = Start Of Frame
• ID = Identifier
• RTR = Remote Transmission Request
• IDE = Identifier Extension Bit
• r0 = Reserved Bit
• DLC = Data Length Code
• CRC = Cyclic Redundancy Code
• Error flag: 6 dominant bits if node is error active else 6 recessive bits.
• Suspend transmission: applies to error passive nodes only.
• EOF = End of Frame
• ACK = Acknowledge bit Data Frame or Remote FrameAny Frame Inter-Frame Space or Error Frame End Of Frame or Error Delimiter or Overload Delimiter Ack Field End Of Frame RTR IDE EOF

10.7.3.3 Modes of Operation

by the RUN bit being read-back as 0. otherwise it enters RESYNC directly. dition to all other bus members. Figure 57. CAN Controller State Diagram

ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) – RESYNC . The resynchronization mode is used to find the correct entry point for starting trans- mission or reception after the node has gone asynchronous either by going into the STANDBY or bus-off states. Resynchronization is achieved when 128 se- quences of 11 recessive bits have been moni- tored unless the node is not bus-off and the FSYN bit in the CSR register is set in which case a single sequence of 11 recessive bits needs to be monitored. – IDLE. The CAN controller looks for one of the fol- lowing events: the RUN bit is reset, a Start Of Frame appears on the CAN bus or the DATA7 register of the currently active page is written to. – TRANSMISSION . Once the LOCK bit of a Buffer Control/Status Register (BCSRx) has been set and read back as such, a transmit job can be submitted by writing to the DATA7 register. The message with the highest priority will be transmit- ted as soon as the CAN bus becomes idle. Among those messages with a pending trans- mission request, the highest priority is given to Buffer 3 then 2 and 1. If the transmission fails due to a lost arbitration or to an error while the NRTX bit of the CSR register is reset, then a new trans- mission attempt is performed . This goes on until the transmission ends successfully or until the job is cancelled by unlocking the buffer, by set- ting the NRTX bit or if the node ever enters bus- off or if a higher priority message becomes pend- ing. The RDY bit in the BCSRx register, which was set since the job was submitted, gets reset. When a transmission is in progress, the BUSY bit in the BCSRx register is set. If it ends successful- ly then the TXIF bit in the Interrupt Status Regis- ter (ISR) is set, else the TEIF bit is set. An interrupt is generated in either case provided the TXIE and TEIE bits of the ICR register are set. The ETX bit in the same register is used to get an early transmit interrupt and to automatically un- lock the transmitting buffer upon successful com- pletion of its job. This enables the CPU to get a new transmit job pending by the end of the cur- rent transmission while always leaving two buff- ers available for reception. An uninterrupted stream of messages may be transmitted in this way at no overrun risk. Note 1:Setting the SRTE bit of the CSR register allows transmitted messages to be simultane- ously received when they pass the acceptance filtering. This is particularly useful for checking the integrity of the communication path. Note 2:When the ETX bit is reset, the buffer with the highest priority and with a pending transmis- sion request is always transmitted. When the ETX bit is set, once a buffer participates in the ar- bitration phase, it is sent until it wins the arbitra- tion even if another transmission is requested from a buffer with a higher priority. – RECEPTION . Once the CAN controller has syn- chronized itself onto the bus activity, it is ready for reception of new messages. Every incoming message gets its identifier compared to the ac- ceptance filters. If the bitwise comparison of the selected bits ends up with a match for at least one of the filters then that message is elected for reception and atarget buffer is searched for. This buffer will be the first one - order is 1 to 3 - that has the LOCK and RDY bits of its BCSRx regis- ter reset. – When no such buffer exists then an overrun interrupt is generated if the ORIE bit of the ICR register has been set. In this case the identifi- er of the last message is made available in the Last Identifier Register (LIDHR and LIDLR) at least until it gets overwritten by a new identifi- er picked-up from the bus. – When a buffer does exist, the accepted mes- sage gets written into it, the ACC bit in the BCSRx register gets the number of the match- ing filter, the RDY and RXIF bits get set and an interrupt is generated if the RXIE bit in the ISR register is set. Up to three messages can be automatically received without intervention from the CPU because each buffer has its own set of status bits, greatly reducing the reactiveness require- ments in the processing of the receive inter- rupts.

cation to determine the stability of the network. Register. Refer to Figure 58. Figure 58. CAN Error State Diagram

10.7.3.4 Bit Timing Logic

synchronizing on following edges. between 1 and 4 time quanta. that the sample point is delayed. RJW so that the transmit point is moved earlier. Figure 59. Bit Timing

ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d)

10.7.4 Register Description

The CAN registers are organized as 6 general pur- pose registers plus 5 pages of 16 registers span- ning the same address space and primarily used for message and filter storage. The page actually selected is defined by the content of the Page Se- lection Register. Refer to Figure 60.

10.7.4.1 General Purpose Registers

INTERRUPT STATUS REGISTER (ISR) Read/Write Reset Value: 00h Bit 7 =RXIF3 Receive Interrupt Flag for Buffer 3 − Read/Clear Set byhardware to signal that a new error-free mes- sage is available in buffer 3. Cleared by software to release buffer 3. Also cleared by resetting bit RDY of BCSR3. Bit 6 =RXIF2 Receive Interrupt Flag for Buffer 2 − Read/Clear Set by hardware to signal that a new error-free message is available in buffer 2. Cleared by software to release buffer 2. Also cleared by resetting bit RDY of BCSR2. Bit 5 =RXIF1 Receive Interrupt Flag for Buffer 1 − Read/Clear Set byhardware to signal that a new error-free mes- sage is available in buffer 1. Cleared by software to release buffer 1. Also cleared by resetting bit RDY of BCSR1. Bit 4 =TXIF Transmit Interrupt Flag − Read/Clear Set by hardware to signal that the highest priority message queued for transmission has been suc- cessfully transmitted (ETX = 0) or that it has passed successfully the arbitration (ETX = 1). Cleared by software. Bit 3 =SCIF Status Change Interrupt Flag − Read/Clear Set by hardware to signal the reception of a domi- nant bit while in standby or a change from error ac- tive to error passive and bus-off while in run. Also signals any receive error when ESCI = 1. Cleared by software. Bit 2 =ORIF Overrun Interrupt Flag − Read/Clear Set by hardware to signal that a message could not be stored because no receive buffer was available. Cleared by software. Bit 1 =TEIF Transmit Error Interrupt Flag − Read/Clear Set byhardware to signal that an erroroccurred dur- ing thetransmission of the highest prioritymessage queued for transmission. Cleared by software. Bit 0 =EPND Error Interrupt Pending − Read Only Set byhardware when at leastone of the three error interrupt flags SCIF, ORIF or TEIF is set. Reset by hardware when all error interrupt flags have been cleared. Caution; Interrupt flags are reset by writing a ”0” to the cor- responding bit position. The appropriate way con- sists in writing an immediate mask orthe one’s com- plement of the register content initially read by the interrupt handler. Bit manipulation instruction BRES should neverbe used due to its read-modify- write nature. RXIF3 RXIF2 RXIF1 TXIF SCIF ORIF TEIF EPND

ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) INTERRUPT CONTROL REGISTER (ICR) Read/Write Reset Value: 00h Bit 6 =ESCI Extended Status Change Interrupt − Read/Set/Clear Set by software to specify that SCIF is to be set on receive errors also. Cleared by software to set SCIF only on status changes and wake-up but not on all receive errors. Bit 5 =RXIE Receive Interrupt Enable − Read/Set/Clear Set by software to enable an interrupt request whenever a message has been received free of er- rors. Cleared by software to disable receive interrupt re- quests. Bit 4 = TXIE Transmit Interrupt Enable − Read/Set/Clear Set by software to enable an interrupt request whenever a message has been successfully trans- mitted. Cleared by software to disable transmit interrupt requests. Bit 3 =SCIE Status Change Interrupt Enable − Read/Set/Clear Set by software to enable an interrupt request whenever thenode’s status changes in run mode or whenever a dominant pulse is received in standby mode. Cleared by software to disable status change inter- rupt requests. Bit 2 =ORIE Overrun Interrupt Enable − Read/Set/Clear Set by software to enable an interrupt request whenever a message should be stored and no re- ceive buffer is avalaible. Cleared by software to disable overrun interrupt re- quests. Bit 1 =TEIE Transmit Error Interrupt Enable − Read/Set/Clear Set by software to enable an interrupt whenever an error has been detected during transmission of a message. Cleared by software to disable transmit error inter- rupts. Bit 0 =ETX Early Transmit Interrupt − Read/Set/Clear Set by software to request the transmit interrupt to occur as soon as the arbitration phase has been passed successfully. Cleared by software to request the transmit inter- rupt to occur at the completion of the transfer.

0 ESCI RXIE TXIE SCIE ORIE TEIE ETX

ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 00h Bit 6 =BOFF Bus-Off State − Read Only Set by hardware to indicate that the node is in bus- off state, i.e. the Transmit Error Counter exceeds 255. Reset by hardware to indicate that the node is in- volved in bus activities. Bit 5 =EPSV Error Passive State − Read Only Set by hardware to indicate that the node is error passive. Reset by hardware to indicate that the node is either error active (BOFF = 0) or bus-off. Bit 4 =SRTE Simultaneous Receive/Transmit En- able− Read/Set/Clear Set by software to enable simultaneous transmis- sion and reception of a message passing the ac- ceptance filtering. Allows to check the integrity of the communication path. Reset by software to discard all messages trans- mitted by the node. Allows remote and data frames to share the same identifier. Bit 3 =NRTX No Retransmission − Read/Set/Clear Set by software to disable the retransmission of un- successful messages. Cleared by software to enable retransmission of messages until success is met. Bit 2 =FSYN Fast Synchronization − Read/Set/Clear Set by software to enable a fast resynchronization when leaving standby mode, i.e. wait for only 11 re- cessive bits in a row. Cleared by software to enable the standard resyn- chronization when leaving standby mode, i.e. wait for 128 sequences of 11 recessive bits. Bit 1 =WKPS Wake-up Pulse − Read/Set/Clear Set bysoftware to generate a dominant pulse when leaving standby mode. Cleared by software for no dominant wake-up pulse. Bit 0 =RUN CAN Enable − Read/Set/Clear Set bysoftware to leave standby modeafter 128 se- quences of 11 recessive bits or just 11 recessive bits if FSYN is set. Cleared by software to request a switch to the standby or low-power mode as soon as any on-go- ing transfer is complete. Read-back as 1 in the meantime toenable proper signalling of thestandby state. The CPU clock may therefore be safely switched OFF whenever RUN is read as 0.

0 BOFF EPSV SRTE NRTX FSYN WKPS RUN

ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) BAUD RATE PRESCALER REGISTER (BRPR) Read/Write in Standby mode Reset Value: 00h RJW[1:0] determine the maximum number of time quanta by which a bit period may be shortened or lengthened to achieve resynchronization. tRJW =tCAN * (RJW + 1) BRP[5:0] determine the CAN system clock cycle time or time quanta which is used to build up the in- dividual bit timing. tCAN =tCPU * (BRP + 1) Where tCPU = time period of the CPU clock. The resulting baud rate can be computed bythe for- mula: Note: Writing to this register is allowed only in Standby mode to prevent any accidental CAN pro- tocol violation through programming errors. BIT TIMING REGISTER (BTR) Read/Write in Standby mode Reset Value: 23h BS2[2:0]determine the length of Bit Segment 2. tBS2 =tCAN * (BS2 + 1) BS1[3:0]determine the length of Bit Segment 1. tBS1 =tCAN * (BS1 + 1) Note: Writing to this register is allowed only in Standby mode to prevent any accidental CAN pro- tocol violation through programming errors. PAGE SELECTION REGISTER (PSR) Read/Write Reset Value: 00h PAGE[2:0] determine which buffer or filter page is mapped at addresses 0010h to 001Fh. RJW1 RJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 BR 1 tCPU BRP 1+()× BS 1 BS 23++()×

0 BS22 BS21 BS20 BS13 BS12 BS11 BS10

00000 PAGE

PAGE2 PAGE1 PAGE0 Page Title 0 0 0 Diagnosis 0 0 1 Buffer 1 0 1 0 Buffer 2 0 1 1 Buffer 3 1 0 0 Filters 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved

ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d)

10.7.4.2 Paged Registers

LAST IDENTIFIER HIGH REGISTER (LIDHR) Read/Write Reset Value: Undefined LID[10:3]are the most significant 8 bits of the last Identifier read on the CAN bus. LAST IDENTIFIER LOW REGISTER (LIDLR) Read/Write Reset Value: Undefined LID[2:0]are the least significant 3 bits of the last Identifier read on the CAN bus. LRTR is the last Remote Transmission Request bit read on the CAN bus. LDLC[3:0]is the last DataLength Code read on the CAN bus. TRANSMIT ERROR COUNTER REG. (TECR) Read Only Reset Value: 00h TEC[7:0]is the least significant byte of the 9-bit Transmit Error Counter implementing part of the fault confinement mechanism of the CAN protocol. In case of an error during transmission, this counter is incremented by 8. It is decremented by 1 after every successful transmission. When the counter value exceeds 127, the CAN controller enters the error passivestate. When avalue of 256 isreached, the CAN controller is disconnected from the bus. RECEIVE ERROR COUNTER REG. (RECR) Page: 00h — Read Only Reset Value: 00h REC[7:0]is the Receive Error Counter implement- ing part of the fault confinement mechanism of the CAN protocol. In case of an error during reception, this counter is incremented by 1 or by 8 depending on the error condition as defined by the CAN stand- ard. After every successful reception the counter is decremented by 1 or reset to 120 if its value was higher than 128. When the counter value exceeds 127, the CAN controller enters the error passive state. IDENTIFIER HIGH REGISTERS (IDHRx) Read/Write Reset Value: Undefined ID[10:3]are the most significant 8 bits of the 11-bit message identifier.The identifier acts as the mes- sage’s name, used for bus access arbitration and acceptance filtering. LID10 LID9 LID8 LID7 LID6 LID5 LID4 LID3 LID2 LID1 LID0 LRTR LDLC LDLC LDLC LDLC TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3

ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) IDENTIFIER LOW REGISTERS (IDLRx) Read/Write Reset Value: Undefined ID[2:0]are the least significant 3 bits of the 11-bit message identifier. RTR is the Remote Transmission Request bit. It is set to indicate a remote frame and reset to indicate a data frame. DLC[3:0] is the Data Length Code. It gives the number of bytes in the data field of the mes- sage.The valid range is 0 to 8. DATA REGISTERS (DATA0-7x) Read/Write Reset Value: Undefined DATA[7:0]is amessage databyte. Upto eight such bytes may be part of a message. Writing to byte DATA7 initiates a transmit request and should al- ways be done even when DATA7 is not part of the message. BUFFER CONTROL/STATUS REGs. (BCSRx) Read/Write Reset Value: 00h Bit 3 =ACC Acceptance Code − Read Only Set by hardware with the id of the highest priority filter which accepted the message stored in the buffer. ACC = 0: Match for Filter/Mask0. Possible match for Filter/Mask1. ACC = 1: No match for Filter/Mask0 and match for Filter/Mask1. Reset by hardware when either RDY or RXIF gets reset. Bit 2 =RDY Message Ready − Read/Clear Set by hardware to signal that a new error-free message is available (LOCK = 0) or that a trans- mission request is pending (LOCK = 1). Cleared by software when LOCK = 0 to release the buffer and to clear the corresponding RXIF bit in the Interrupt Status Register. Cleared by hardware when LOCK = 1 to indicate that the transmission request has been serviced or cancelled. Bit 1 =BUSY Busy Buffer − Read Only Set by hardware when the buffer is being filled (LOCK = 0) or emptied (LOCK = 1). Reset by hardware when the buffer is not ac- cessed by the CAN core for transmission nor re- ception purposes. Bit 0 =LOCK Lock Buffer − Read/Set/Clear Set by software to lock a buffer. No more message can be received into the buffer thus preserving its content and making it available for transmission. Cleared by software to make the buffer available for reception. Cancels any pending transmission request. Cleared by hardware once a message has been successfully transmitted provided the early trans- mit interrupt mode is on. Left untouched otherwise. Note that in order to prevent any message corrup- tion or loss of context, LOCK cannot be set nor re- set while BUSY is set. Trying to do so will result in LOCK not changing state. ID2 ID1 ID0 RTR DLC3 DLC2 DLC1 DLC0 DATA DATA DATA DATA DATA DATA DATA DATA 0 0 0 0 ACC RDY BUSY LOCK

ST72311R, ST72511R, ST72512R, ST72532R CONTROLLER AREA NETWORK (Cont’d) FILTER HIGH REGISTERS (FHRx) Read/Write Reset Value: Undefined FIL[11:3]are the most significant 8 bits of a 12-bit message filter. The acceptance filter is compared bit by bit with the identifier and the RTR bit of the incoming message. If there is a match for the set of bits specified by the acceptance mask then the message is stored in a receive buffer. FILTER LOW REGISTERS (FLRx) Read/Write Reset Value: Undefined FIL[3:0]are the least significant 4 bits of a 12-bit message filter. MASK HIGH REGISTERS (MHRx) Read/Write Reset Value: Undefined MSK[11:3] are the most significant 8 bits of a 12- bit message mask. The acceptance mask defines which bits of the acceptance filter should match the identifier and the RTR bit of the incoming mes- sage. MSK i= 0: don’t care. MSK i= 1: match required. MASK LOW REGISTERS (MLRx) Read/Write Reset Value: Undefined MSK[3:0]are the least significant 4 bits of a 12-bit message mask. FIL11 FIL10 FIL9 FIL8 FIL7 FIL6 FIL5 FlL4 FIL3 FIL2 FIL1 FIL0 0 0 0 0 MSK1 MSK1

0 MSK9 MSK8 MSK7 MSK6 MSK5 MSK4

MSK3 MSK2 MSK1 MSK0 0 0 0 0

Figure 60. CAN Register Map

Figure 61. Page Maps

Table 23. CAN Register Map and Reset Values

0 CANLIDHR

0 CANLIDLR

10.8.1 Introduction

levels from up to 16 different sources. through a Control/Status Register.

10.8.2 Main Features

The block diagram is shown in Figure 62.

10.8.3 Functional Description

10.8.3.1 Analog Power Supply

loaded or badly decoupled power supply lines. Figure 62. ADC Block Diagram CH2 CH1CH3COCO 0 ADON 0 CH0 ADCCSR

10.8.3.2 Digital A/D Conversion Result

and never increases if the analog input does not. scale) without overflow indication. version result in the DR register is 00h. the conversion is stored in the ADCDR register.

10.8.3.3 A/D Conversion Phases

analog to digital conversion accuracy. pin in case of single input channel measurement.

10.8.3.4 Software Procedure

tions and to Figure 63 for the timings. clock periods (1/fADC =2/fCPU ). sion of the selected channel. – The COCO bit is set by hardware. – No interrupt is generated. valid until the next conversion has ended. Figure 63. ADC Conversion Timings

10.8.4 Low Power Modes

and between single shot conversions.

10.8.5 Interrupts

curate conversions can be performed.

ST72311R, ST72511R, ST72512R, ST72532R 8-BIT A/D CONVERTER (ADC) (Cont’d)

10.8.6 Register Description

CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) Bit 7 =COCO Conversion Complete This bit is set by hardware. It is cleared by soft- ware reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register Bit 6 =Reserved. must always be cleared. Bit 5 =ADON A/D Converter On This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bit 4 =Reserved. must always be cleared. Bit 3:0 =CH[3:0]Channel Selection These bits are set and cleared by software. They select the analog input to convert. *Note: The number of pins AND the channel selec- tion varies according to the device. Refer to the de- vice pinout. DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h) Bit 7:0 =D[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Note: Reading this register reset the COCO flag. COCO 0 ADON 0 CH3 CH2 CH1 CH0 Channel Pin* CH3 CH2 CH1 CH0 AIN0 0 0 0 0 AIN1 0 0 0 1 AIN2 0 0 1 0 AIN3 0 0 1 1 AIN4 0 1 0 0 AIN5 0 1 0 1 AIN6 0 1 1 0 AIN7 0 1 1 1 AIN8 1 0 0 0 AIN9 1 0 0 1 AIN10 1 0 1 0 AIN11 1 0 1 1 AIN12 1 1 0 0 AIN13 1 1 0 1 AIN14 1 1 1 0 AIN15 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0

Table 24. ADC Register Map and Reset Values

11 INSTRUCTION SET

11.1 ST7 ADDRESSING MODES

Table 25. ST7 Addressing Mode Overview

ST72311R, ST72511R, ST72512R, ST72532R INSTRUCTION SET OVERVIEW (Cont’d)

11.1.1 Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation.

11.1.2 Immediate

Immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value.

11.1.3 Direct

In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub- modes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF address- ing space. Direct (long) The address is a word, thus allowing 64 Kbyte ad- dressing space, but requires 2 bytes after the op- code.

11.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte ad- dressing space and requires 2 bytes after the op- code.

11.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (point- er). The pointer address follows the opcode. The indi- rect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Pow- er Mode) HALT Halt Oscillator (Lowest Power Mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask (level 3) RIM Reset Interrupt Mask (level 0) SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations

11.1.6 Indirect Indexed (Short, Long)

er address follows the opcode. and requires 1 byte after the opcode. and requires 1 byte after the opcode. Table 26. Instructions Supporting Direct,

11.1.7 Relative mode (Direct, Indirect)

The offset is following the opcode.

ST72311R, ST72511R, ST72512R, ST72532R INSTRUCTION SET OVERVIEW (Cont’d)

11.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Using a pre-byte The instructions are described with one to four op- codes. In order to extend the number of available op- codes for an 8-bit CPU (256 opcodes), three differ- ent prebyte opcodes are defined. These prebytes modify the meaning of the instruction they pre- cede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the ef- fective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent ad- dressing mode by a Y one. PIX 92 Replace an instruction using di- rect, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed ad- dressing mode to an instruction using indirect X in- dexed addressing mode. PIY 91 Replace an instruction using X in- direct indexed addressing mode by a Y one. Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Code Condition Flag modification SIM RIM SCF RCF

ST72311R, ST72511R, ST72512R, ST72532R INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description Function/Example Dst Src I1 H I0 N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 10 IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C INC Increment inc X reg, M N Z JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if Port B INT pin = 1 (no Port B Interrupts) JRIL Jump if Port B INT pin = 0 (Port B interrupt) JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I1:0 = 11 I1:0 = 11 ? JRNM Jump if I1:0 <> 11 I1:0 <> 11 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >

ST72311R, ST72511R, ST72512R, ST72532R INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description Function/Example Dst Src I1 H I0 N Z C JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2’s compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M I1 H I0 N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I1:0 = 10 (level 0) 1 0 RLC Rotate left true C C <= A <= C reg, M N Z C RRC Rotate right true C C => A => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Substract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I1:0 = 11 (level 3) 1 1 SLA Shift left Arithmetic C <= A <= 0 reg, M N Z C SLL Shift left Logic C <= A <= 0 reg, M N Z C SRL Shift right Logic 0 => A => C reg, M 0 Z C SRA Shift right Arithmetic A7 => A => C reg, M N Z C SUB Substraction A = A - M A M N Z C SWAP SWAP nibbles A7-A4 <=> A3-A0 reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 1 WFI Wait for Interrupt 1 0 XOR Exclusive OR A = A XOR M A M N Z

12 ELECTRICAL CHARACTERISTICS

12.1 PARAMETER CONDITIONS

12.1.1 Minimum and Maximum values

times the standard deviation (mean±3Σ).

12.1.2 Typical values

guidelines and are not tested.

12.1.3 Typical curves

given only as design guidelines and are not tested.

12.1.4 Loading capacitor

measurement are shown in Figure 64. Figure 64. Pin loading conditions

12.1.5 Pin input voltage

vice is described in Figure 65. Figure 65. Pin input voltage

ST72311R, ST72511R, ST72512R, ST72532R

12.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

12.2.1 Voltage Characteristics

12.2.2 Current Characteristics

12.2.3 Thermal Characteristics

Notes: 1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for RESET, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN)specification. A positive injection is induced by VIN>V DD while a negative injection is induced by VIN<V SS . 3. All power (VDD ) and ground (VSS ) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effect on analog part, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. When several inputs are submitted to a current injection, the maximumΣI INJ(PIN)is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterisation withΣ IINJ(PIN)maxi- mum current injection on four I/O port pins of the device. 6. True open drain I/O port pins do not accept positive injection. Symbol Ratings Maximum value Unit V DD -V SS Supply voltage 6.5 V VDDA -V SSA Analog reference voltage (VDD ≥VDDA ) 6.5 |Δ VDDx | and |ΔVSSx | Variations between different digital power pins 50 mV |VSSA -V SSx | Variations between digital and analog ground pins 50 VIN Input voltage on VPP pin V SS -0.3 to 13 V Input voltage on any other pin1) & 2) VSS -0.3 to VDD +0.3 V ESD(HBM) Electro-static discharge voltage (Human Body Model)see Section 12.7.2 ”Absolute Electri- cal Sensitivity” on page 141VESD(MM) Electro-static discharge voltage (Machine Model) Symbol Ratings Maximum value Unit IVDD Total current into VDD power lines (source)3) 150 mA IVSS Total current out of VSS ground lines (sink)3) 150 IIO Output current sunk by any standard I/O and control pin 25 Output current sunk by any high sink I/O pin 50 Output current source by any I/Os and control pin - 25 I INJ(PIN) 2) & 4) Injected current on VPP pin ± 5 Injected current on RESET pin ± 5 Injected current on OSC1 and OSC2 pins ± 5 Injected current on any other pin5) & 6) ± 5 ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins)5) ± 20 Symbol Ratings Value Unit TSTG Storage temperature range -65 to +150 °C TJ Maximum junction temperature (see Section 13.2 ”THERMAL CHARACTERISTICS” on page 155 )

12.3 OPERATING CONDITIONS

12.3.1 General Operating Conditions

Figure 66. fOSC Maximum Operating Frequency Versus VDD Supply for devices without EEPROM2) Figure 67. fOSC Maximum Operating Frequency Versus VDD Supply for device with EEPROM2)

1. Guaranteed by construction. A/D operation is not guaranteed below 1MHz.
2. Operating conditions with TA=-40 to +125°C.

1 Suffix Version 0 70

6 Suffix Version -40 85

7 Suffix Version -40 105

3 Suffix Version -40 125

12.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating condition for VDD ,fOSC , and TA. Figure 68. LVD Threshold Versus VDD and fOSC for ROM devices2)

1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.

12.4 SUPPLY CURRENT CHARACTERISTICS

12.4.1 RUN and SLOW Modes

Figure 69. Typical I

1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals

switched off; clock input (OSC1) driven by external square wave, LVD disabled.

1. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or

V SS (no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled.

12.4.2 WAIT and SLOW WAIT Modes

Figure 71. Typical IDD in WAIT vs. fCPU Figure 72. Typical IDD in SLOW-WAIT vs. fCPU

1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals switched off; clock input (OSC1)

driven by external square wave, LVD disabled.

1. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at

V DD or VSS (no load), all peripherals switched off; clock input (OSC1) driven by external square wave, LVD disabled.

ST72311R, ST72511R, ST72512R, ST72532R SUPPLY CURRENT CHARACTERISTICS (Cont’d)

12.4.3 HALT and ACTIVE-HALT Modes

12.4.4 Supply and Clock Managers

The previous current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- vice consumption, the two current values must be added (except for HALT mode).

12.4.5 On-Chip Peripheral

Notes: 1. Typical data are based on TA=25°C. 2. All I/O pins in input mode with a static value at VDD or VSS (no load), LVD disabled. 3. Data based on design simulation and/or technology characteristics, not tested in production. All I/O pins in input mode with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. 4. Typical data are based on TA=25°C, VDD =5V. 5. Data based on characterization results, not tested in production. 6. Data based on characterization results done with the typical external components, not tested in production. 7. As the oscillator is based on a current source, the consumption does not depend on the voltage. 8. Data based on a differential I DD measurement between reset configuration (timer counter running at fCPU /4) and timer counter stopped (selecting external clock capability). Data valid for one timer. 9. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica- tion (data sent equal to 55h). 10. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. Symbol Parameter Conditions Typ 1) Max Unit IDD Supply current in HALT mode2) 3.0V≤V DD VDD ≤5.5V µA40°C ≤TA≤+125°C5 0 Supply current in ACTIVE-HALT mode3) 50 150 Symbol Parameter Conditions Typ 4) Max 5) Unit IDD(CK) Supply current of resonator oscillator6) & 7) 600 850 µA IDD(LVD) LVD supply current HALT mode 100 150 Symbol Parameter Conditions Typ Unit IDD(TIM) 16-bit Timer supply current8) fCPU =8MHz VDD =3.3V 50 µA VDD =5.0V 150 IDD(SPI) SPI supply current9) fCPU =8MHz VDD =3.3V 250 VDD =5.0V 350 IDD(ADC) ADC supply current when converting10) fADC =4MHz VDD =3.3V 800 VDD =5.0V 1100

12.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating condition for VDD ,fOSC , and TA.

12.5.1 General Timings

12.5.2 External Clock Source

Figure 73. Typical Application with an External Clock Source

12.5.3 Crystal and Ceramic Resonator Oscillators

1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch.Δtc(INST)is the number of tCPU cycles needed to finish

the current instruction execution.

1. Data based on design simulation and/or technology characteristics, not tested in production.
2. CL1 (resp.CL2) is load capacitance on OSC1 (resp. OSC2) pin.
3. RS is the equivalent serial resistance of the crystal or ceramic resonator.

ST72311R, ST72511R, ST72512R, ST72532R

12.6 MEMORY CHARACTERISTICS

Subject to general operating condition for VDD ,fOSC , and TA unless otherwise specified.

12.6.1 RAM and Hardware Registers

12.6.2 EEPROM Data Memory

12.6.3 EPROM Program Memory

Notes: 1. Minimum VDD supply voltage without losing data stored into RAM (in in HALT mode or under RESET) or into hardware registers (only in HALT mode). Guaranteed by construction, not tested in production. 2. The data retention time increase when the TA decreases. 3. Data based on reliability test results and monitored in production. 4. Data given only as guidelines. Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode1) HALT mode (or RESET) 1.6 V Symbol Parameter Conditions Min Typ Max Unit tprog Programming time (for 1 up to 16 bytes at a time) -40°C ≤TA≤+85°C1 0 ms tret Data retention3) TA=+55°C 2) 20 Years N RW Write erase cycles3) TA=+25°C 300 000 Cycles Symbol Parameter Conditions Min Typ Max Unit W ERASE UV lamp Lamp wavelength 2537Å 15 Watt.sec /cm2 terase Erase Time4) UV lamp is placed 1 inch from the device window without any interposed filters 15 20 min t ret Data retention3) TA =+55°C 2) 20 years

12.7 EMC CHARACTERISTICS

sis during product characterization.

12.7.1 Functional EMS

until a failure occurs (indicated by the LEDs). conforms with the IEC 1000-4-2 standard. Figure 74. EMC Recommended star network power supply connection

1. Data based on characterization results, not tested in production.
2. The suggested 10nF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC

dations are given in other sections (I/Os, RESET, OSCx pin characteristics).

12.7.2 Absolute Electrical Sensitivity

fer to the AN1181 ST7 application note.

12.7.2.1 Electro-Static Discharge (ESD)

conforms to the JESD22-A114A/A115A standard. See Figure 75 and the following test sequences. – S1 switches position from generator to R. prior to the delivery of the next pulse. – S1 switches position from generator to ST7. prior to the delivery of the next pulse. sures a slow discharge of the ST7. Figure 75. Typical Equivalent ESD Circuits

1. Data based on characterization results, not tested in production.

12.7.2.2 Static and Dynamic Latch-Up

on 10 parts to assess the latch-up performance. refer to the AN1181 ST7 application note. Figure 76. Simplified Diagram of the ESD Generator for DLU

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-

JEDEC criteria (international standard).

1. Schaffner NSG435 with a pointed test finger.

12.7.3 ESD Pin Protection Strategy

or heating within their structure. Figure 77. Positive Stress on a Standard Pad vs. VSS Figure 78. Negative Stress on a Standard Pad vs. VDD

12.8 I/O PORT PIN CHARACTERISTICS

12.8.1 General Characteristics

Subject to general operating condition for VDD ,fOSC , and TA unless otherwise specified. Figure 82. Two typical Applications with unused I/O Pin

1. Unless otherwise specified, typical data are based on TA=25°C and VDD =5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

characteristics, not tested in production.

1. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

12.8.2 Output Driving Current

Subject to general operating condition for VDD ,fOSC , and TA unless otherwise specified. Figure 83. Typical VOL at VDD =5V (standard) Figure 84. Typical VOL at VDD =5V (high-sink) Figure 85. Typical VDD -VOH at VDD =5V

1. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS .

1. The IIO current sourced must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of

IIO (I/O ports and control pins) must not exceed IVDD . True open drain I/O pins does not have VOH .

12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating condition for VDD ,fOSC , and TA unless otherwise specified. Figure 86. Typical Application with RESET pin5)

12.9.2 VPP Pin

Subject to general operating condition for VDD ,fOSC , and TA unless otherwise specified. Figure 87. Two typical Applications with VPP Pin7)

1. Unless otherwise specified, typical data are based on TA=25°C and VDD =5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results,
5. The reset network protects the device against parasitic resets, especially in a noisy environment.
6. Data based on design simulation and/or technology characteristics, not tested in production.
7. When the in-circuit programming mode is not required by the application VPP pin must be tied to VSS .

ST72311R, ST72511R, ST72512R, ST72532R

12.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating condition for VDD ,fO- SC , and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (outpu compare, input capture, external clock, PWM output...).

12.10.1 Watchdog Timer

12.10.2 8-Bit PWM-ART Auto-Reload Timer 12.10.3 16-Bit Timer Symbol Parameter Conditions Min Typ Max Unit tw(WDG) Watchdog time-out duration 12,288 786,432 t CPU fCPU =8MHz 1.54 98.3 ms Symbol Parameter Conditions Min Typ Max Unit tres(PWM) PWM resolution time 1t CPU fCPU =8MHz 125 ns fEXT ART external clock frequency 0 f CPU /2 MHz fPWM PWM repetition rate 0 f CPU /2 ResPWM PWM resolution 8 bit VOS PWM/DAC output step voltage V DD =5V, Res=8-bits 20 mV Symbol Parameter Conditions Min Typ Max Unit tw(ICAP)in Input capture pulse time 1 t CPU tres(PWM) PWM resolution time 2t CPU fCPU =8MHz 250 ns fEXT Timer external clock frequency 0 f CPU /4 MHz fPWM PWM repetition rate 0 f CPU /4 MHz ResPWM PWM resolution 16 bit

12.11 COMMUNICATIONS INTERFACE CHARACTERISTICS

12.11.1 SPI - Serial Peripheral Interface

SC , and TA unless otherwise specified. Figure 88. SPI Slave Timing Diagram with CPHA=03)

1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD .

ST72311R, ST72511R, ST72512R, ST72532R COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)

12.11.2 SCI - Serial Communications Interface

Subject to general operating condition for VDD ,fO- SC , and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI and TDO).

12.11.3 CAN - Controller Area Network Interface

Subject to general operating condition for V DD ,fO- SC , and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). Symbol Parameter Conditions Standard Baud Rate Unit fCPU Accuracy vs. Standard Prescaler fTx fRx Communication frequency 8MHz ~0.16% Conventional Mode TR (or RR)=64, PR=13 TR (or RR)=16, PR=13 TR (or RR)= 8, PR=13 TR (or RR)= 4, PR=13 TR (or RR)= 2, PR=13 TR (or RR)= 8, PR= 3 TR (or RR)= 1, PR=13 300 1200 2400 4800 9600 10400 19200 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 Hz Extended Mode ETPR (or ERPR) = 13 38400 ~38461.54 ~0.79% Extended Mode ETPR (or ERPR) = 35 14400 ~14285.71 Symbol Parameter Conditions Min Typ Max Unit t p(RX:TX) CAN controller propagation time 60 ns

Subject to general operating condition for VDD ,fOSC , and TA unless otherwise specified. Figure 91. Typical Application with ADC

1. Unless otherwise specified, typical data are based on TA=25°C and VDD -VSS =5V. They are given only as design guide-
2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS .
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ ). Data

based on characterization results, not tested in production.

1. The stabilization time of the AD converter is masked by the first tLOAD . The first conversion after the enable is then

Figure 92. ADC Accuracy Characteristics

1. Data based on characterization results over the whole temperature range, monitored in production.
2. ADC Accuracy vs. Negative Injection Current:

-a t5 VVDD supply, and worst case temperature.

1 LSBIDEAL

between the actual and the ideal transfer curves. transition and the first ideal one. transition and the last actual one. between actual steps and the ideal one.

13 PACKAGE CHARACTERISTICS

13.1 PACKAGE MECHANICAL DATA

Figure 93. 64-Pin Thin Quad Flat Package Figure 94. 64-Pin Epoxy Thin Quad Flat Package

ST72311R, ST72511R, ST72512R, ST72532R

13.2 THERMAL CHARACTERISTICS

Notes: 1. The power dissipation is obtained from the formula PD =P INT+P PORT where PINT is the chip internal power (IDD xVDD ) and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ =T A +P D x RthJA. Symbol Ratings Value Unit R thJA Package thermal resistance (junction to ambient) TQFP64 60 °C/W PD Power dissipation1) 500 mW TJmax Maximum junction temperature2) 150 °C

13.3 SOLDERING AND GLUEABILITY INFORMATION

Recommended soldering information given only as design guidelines. Figure 95. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) Figure 96. Recommended Reflow Soldering Oven Profile (MID JEDEC)

13.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL

board with an TQFP64 clamshell socket. Figure 97. TQFP64 Device And Emulator Probe Compatible Footprint Table 27. Suggested List of TQFP64 Socket Types

• SK: Plastic socket overall dimensions.

ST72311R, ST72511R, ST72512R, ST72532R

14 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro- grammable versions (OTP) as well as in factory coded versions (ROM). OTP devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code sup- plied by the customer. This implies that OTP de- vices have to be configured by the customer using the Option Bytes while the ROM devices are facto- ry-configured.

14.1 OPTION BYTES

The option byte allows the hardware configuration of the microcontroller to be selected. The option byte has no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 program- ming tool). The default content of the OTP is fixed to FFh. This means that all the options have “1” as their default value. In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list). USER OPTION BYTE Bit 7:6,4 =Reserved , must always be 1. Bit 5 =Reserved, must always be 0. Bit 3 =FMP Full memory protection This option bit allows the protection of the software contents against piracy (program or data). When the protection is activated, read-out of the EPROM or data EEPROM contents is prevented by hard- ware. 0: Read-out protection enabled 1: Read-out protection disabled Bit 2 =Reserved , must always be 1 Bit 1 =WDG HALT Watchdog and HALT mode This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active. 0: No Reset generation when entering Halt mode 1: Reset generation when entering Halt mode Bit 0 =WDG SW Hardware or software watchdog This option bit selects the watchdog type. 0: Hardware (watchdog always enabled) 1: Software (watchdog to be enabled by software) USER OPTION BYTE 7 0 FMP WDG HALT WDG SW Default Value 111 11111

14.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE

Figure 98. ROM Factory Coded Device Types Figure 99. OTP User Programmable Device Types

ST72311R, ST72511R, ST72512R, ST72532R TRANSFER OF CUSTOMER CODE (Cont’d) MICROCONTROLLER OPTION LIST STMicroelectronics references Device: [ ] ST72311R9 [ ] ST72511R9 [ ] ST72512R4 [ ] ST72311R7 [ ] ST72511R7 [ ] ST72532R4 [ ] ST72311R6 [ ] ST72511R6 Temperature Range: [ ] 0 °Ct o+7 0°C []-4 0 °Ct o+8 5°C Oscillator Source Selection: [ ] Quartz Crystal/Ceramic resonator [ ] External Clock Watchdog Selection: [ ] Software Activation [ ] Hardware Activation Watchdog Reset on Halt [ ] Disabled [ ] Enabled Readout Protection: [ ] Disabled [ ] Enabled LVD Reset [ ] Disabled [ ] Enabled: Comments : Supply Operating Range in the application:

14.3 DEVELOPMENT TOOLS

ers, emulators and gang programmers.

1. In Situ Programming (ISP) interface for FLASH devices.

Table 28. STMicroelectronics Development Tools

ST72311R, ST72511R, ST72512R, ST72532R

15 ST7 GENERIC APPLICATION NOTE

To get the updated information on that product please refer to STMicroelectronics web server. ß http://st7.st.com/ Identification Description PROGRAMMING AND TOOLS AN912 A simple guide to development tools AN985 Executing code in ST7 RAM AN986 Using the ST7 indirect addressing mode AN987 ST7 in-circuit programming AN988 Starting with ST7 assembly tool chain AN989 Starting with ST7 Hiware C AN1039 ST7 math utility routines AN1064 Writing optimized hiware C language for ST7 EXAMPLE DRIVERS AN969 ST7 SCI communication between the ST7 and a PC AN970 ST7 SPI communication between the ST7 and E PROM AN971 ST7 I C communication between the ST7 and E PROM AN972 ST7 software SPI master communication AN973 SCI software communication with a PC using ST72251 16-bit timer AN974 Real time clock with the ST7 timer output compare AN976 Driving a buzzer using the ST7 PWM function AN979 Driving an analog keyboard with the ST7 ADC AN980 ST7 keypad decoding techniques, implementing wake-up on keystroke AN1017 Using the ST7 USB microcontroller AN1041 Using ST7 PWM signal to generate analog output (sinusoid) AN1042 ST7 routine for I C slave mode management AN1044 Multiple interrupt sources management for ST7 MCUs AN1045 ST7 software implementation of I C bus master AN1047 Managing reception errors with the ST7 SCI peripheral AN1048 ST7 software LCD driver AN1048 ST7 timer PWM duty cycle switch for true 0% or 100% duty cycle PRODUCT OPTIMIZATION AN982 Using ceramic resonators with the ST7 AN1014 How to minimize the ST7 power consumption AN1070 ST7 checksum selfchecking capability PRODUCT EVALUATION AN910 ST7 and st9 performance benchmarking AN990 ST7 benefits versus industry standard APPLICATIONS EXAMPLES AN1086 ST7 / ST10U435 CAN-Do solutions for car multiplexing

ST72311R, ST72511R, ST72512R, ST72532R

16 SUMMARY OF CHANGES

Description of the changes between the current release of the specification and the previous one. Revision Main changes Date 2.1 - Section 8.4 ”LOW POWER MODES” on page 42 and Section 8.5 ”INTERRUPTS” on page 42 added in Section 8 ”I/O PORTS” on page 38. - Section 10.2.5 ”Low Power Modes” on page 53 and Section 10.2.6 ”Interrupts” on page 53 added in Section 10.2 ”MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)” on page 52. - ESD absolute maximum rating modified in Section 12.2 on page 132. - EMC characteristics corrected in Section 12.7 on page 140. Feb-00

ST72311R, ST72511R, ST72512R, ST72532R Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics  2000 STMicroelectronics - All Rights Reserved. Purchase of I 2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http:// www.st.com