ST72101_01 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 85
Technical content
8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM,
256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
■ User Program Memory (ROM/OTP/EPROM): 4 to 8K bytes ■ Data RAM: 256 bytes, including 64 bytes of stack ■ Master Reset and Power-On Reset ■ Run, Wait, Slow, Halt and RAM Retention modes ■ 22 multifunctional bidirectional I/O lines: – 22 programmable interrupt inputs – 8 high sink outputs – 6 analog alternate inputs – 10 to 14 alternate functions –E M I f i l t e r i n g ■ Programmable watchdog (WDG) ■ One or two 16-bit Timers, each featuring: – 2 Input Captures – 2 Output Compares – External Clock input (on Timer A only) – PWM and Pulse Generator modes ■ Synchronous Serial Peripheral Interface (SPI) ■ 8-bit Analog-to-Digital converter (6 channels) (ST72212 and ST72213 only) ■ 8-bit Data Manipulation ■ 63 Basic Instructions ■ 17 main Addressing Modes ■ 8 x 8 Unsigned Multiply Instruction ■ True Bit Manipulation ■ Complete Development Support on PC/DOS- WINDOWS TM Real-Time Emulator ■ Full Software Package on DOS/WINDOWS TM (C-Compiler, Cross-Assembler, Debugger) Device Summary SO28 PSDIP32 CSDIP32W (See ordering information at the end of datasheet) Features ST72101G1 ST72101G2 ST72213G1 ST72212G2 Program Memory- bytes 4K 8K 4K 8K RAM (stack) - bytes 256 (64) 16-bit Timers one one one two ADC no no yes yes Other Peripherals Watchdog, SPI Operating Supply 3 to 5.5 V CPU Frequency 8MHz max (16MHz oscillator) - 4MHz max o ver 85°C Temperature Range - 40°C to + 125°C Rev. 1.8 Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s) Table of Contents
Obsolete Product(s) - Obsolete Product(s) Table of Contents
1 GENERAL DESCRIPTION
1.1 INTRODUCTION
Captures and 2 Output Compares. Figure 1. ST72101, ST72213 and ST72212 Block Diagram
1.2 PIN DESCRIPTION
Figure 2. ST72212 Pinout (SO28) Figure 3. ST72213 Pinout (SO28) Figure 4. ST72101 Pinout (SO28) Figure 5. ST72212 Pinout (SDIP32) Figure 6. ST72213 Pinout (SDIP32) Figure 7. ST72101 Pinout (SDIP32)
Table 1. ST72212 Pin Configuration 1 1 RESET I/O Bidirectional. Active low. Top priority non maskable interrupt.
8 NC Not Connected
9 NC Not Connected
24 NC Not Connected
25 NC Not Connected
ming mode, this pin acts as the programming voltage input VPP.
Table 2. ST72213 Pin Configuration 1 1 RESET I/O Bidirectional. Active low. Top priority non maskable interrupt. of the miscellaneous register. gramming mode, this pin acts as the programming voltage input VPP.
Table 3. ST72101 Pin Configuration 1 1 RESET I/O Bidirectional. Active low. Top priority non maskable interrupt. mode, this pin acts as the programming voltage input VPP. Note 1: VPP on EPROM/OTP only.
1.3 EXTERNAL CONNECTIONS
ternal connections for the device. necessary power consumption on floating lines. ports as inputs with pull-up. Figure 8. Recommended External Connections
1.4 MEMORY MAP
Figure 9. Memory Map Table 4. Interrupt Vector Map
256 Bytes RAM
64 Bytes Stack or
Table 5. Hardware Register Memory Map
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 Notes: 1. ST72212 only, reserved area for other devices. 2. ST72212 and ST72213 only, reserved otherwise. 0041h 0042h 0043h 0044h-0045h 0046h-0047h 0048h-0049h 004Ah-004Bh 004Ch-004Dh 004Eh-004Fh Timer B TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Control Register2 Control Register1 Status Register Input Capture1 High Register Input Capture1 Low Register Output Compare1 High Register Output Compare1 Low Register Counter High Register Counter Low Register Alternate Counter High Register Alternate Counter Low Register Input Capture2 High Register Input Capture2 Low Register Output Compare2 High Register Output Compare2 Low Register 00h 00h 00h xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0050h to 006Fh Reserved Area (32 Bytes) 0070h 0071h ADC 2) ADCDR ADCCSR Data Register Control/Status Register 00h 00h Read Only R/W 0072h to 007Fh Reserved Area (14 Bytes) Address Block Name Register Label Register name Reset Status Remarks
2 CENTRAL PROCESSING UNIT
2.1 INTRODUCTION
2.2 MAIN FEATURES
2.3 CPU REGISTERS
temporary storage areas for data manipulation. (Program Counter High which is the MSB). Figure 10. CPU Registers
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions. These bits can be individually tested and/or con- trolled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET in- structions and is tested by the JRM and JRNM in- structions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- tions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. 111HIN Z C
ways pointing to the next free location in the stack. popped from the stack (see Figure 11). mented and the context is pushed on the stack. and the context is popped from the stack. terrupt five locations in the stack area. Figure 11. Stack Manipulation Example
3 CLOCKS, RESET, INTERRUPTS & POWER SAVING MODES
3.1 CLOCK SYSTEM
3.1.1 General Description
rived from the external oscillator frequency (fOSC ). ed capacitance and feedback resistance values. quency ranges are to be used. Table 6. Recommended Values for 16 MHz er limit, see crystal specification). Figure 12. External Clock Source Connections Figure 13. Crystal/Ceramic Resonator Figure 14. Clock Prescaler Block Diagram
3.2 RESET
3.2.1 Introduction
3.2.2 External Reset
3.2.3 Reset Operation
state, all I/Os take their reset value.
4096 CPU Clock cycle delay period is initiated in
nal connections shown in Figure 8.
3.2.4 Power-on Reset
tion (at approximately VDD = 2V). Figure 15. Reset Block Diagram
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213
4 INTERRUPTS
The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 1. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: – Normal processing is suspended at the end of the current instruction execution. – The PC, X, A and CC registers are saved onto the stack. – The I bit of the CC register is set to prevent addi- tional interrupts. – The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector address- es). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be inter- rupted because the I bit is set by hardware enter- ing in interrupt routine. In the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the Interrupt Map- ping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifi- cally mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT“ column in the Interrupt Mapping Ta- ble).
4.1 NON MASKABLE SOFTWARE INTERRUPT
This interrupt is entered when the TRAP instruc- tion is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 1.
4.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same inter- rupt vector, are configured as interrupts, their sig- nals are logically ANDed and inverted before en- tering the edge/level detection block. Caution: The type of sensitivity defined in the Mis- cellaneous or Interrupt register (if available) ap- plies to the ei source. In case of an ANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity.
4.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: – The I bit of the CC register is cleared. – The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status register or – Access to the status register while the flag is set followed by a read or write of an associated reg- ister. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed.
Figure 16. Interrupt Processing Flowchart
Table 7. Interrupt Mapping Note 1: Timer B is available on ST72212 only.
4.4 POWER SAVING MODES
4.4.1 Introduction
entered using the WFI and HALT instructions.
4.4.2 Slow Mode
clock frequency to available supply voltage.
4.4.3 Wait Mode
Register) is cleared, so as to enable all interrupts. All other registers and memory remain unchanged. terrupt or Reset Service Routine. an Interrupt occurs, causing it to wake up. Figure 17. WAIT Flow Chart
4096 CPU CLOCK
4.4.4 Halt Mode
ister is cleared so as to enable External Interrupts. If an interrupt occurs, the CPU becomes active. by fetching the reset vector if a reset wakes it up. Figure 18. HALT Flow Chart
4.5 MISCELLANEOUS REGISTER
terrupt requests and to output the internal clock. nal interrupt according to Table 8. Table 8. EI1 External Interrupt Polarity Options 0 - PC2 is a general purpose I/O port. nal interrupt according to Table 9. Table 9. EI0 External Interrupt Polarity Options Bit 1:2 = Unused, always read at 0. compatibility with future products. This bit is set and cleared by software.
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213
5 ON-CHIP PERIPHERALS
5.1 I/O PORTS
5.1.1 Introduction
The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – analog signal input (ADC) – alternate signal input/output for the on-chip pe- ripherals. – external interrupt generation An I/O port is composed of up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital out- put.
5.1.2 Functional Description
Each port is associated to 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and some of them to an optional register: – Option Register (OR) Each I/O pin may be programmed using the corre- sponding register bits in DDR and OR registers: bit X corresponding to pin X of the port. The same cor- respondence is used for the DR register. The following description takes into account the OR register, for specific ports which do not provide this register refer to the I/O Port Implementation Section 5.1.3. The generic I/O block diagram is shown on Figure 20.
5.1.2.1 Input Modes
The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. All the inputs are triggered by a Schmitt trigger. 2. When switching from input mode to output mode, the DR register should be written first to output the correct value as soon as the port is con- figured as an output. Interrupt function When an I/O is configured in Input with Interrupt, an event on this I/O can generate an external In- terrupt request to the CPU. The interrupt polarity is given independently according to the description mentioned in the Miscellaneous register or in the interrupt register (where available). Each pin can independently generate an Interrupt request. Each external interrupt vector is linked to a dedi- cated group of I/O port pins (see Interrupts sec- tion). If several input pins are configured as inputs to the same interrupt vector, their signals are logi- cally ANDed before entering the edge/level detec- tion block. For this reason if one of the interrupt pins is tied low, it masks the other ones.
5.1.2.2 Output Mode
The pin is configured in output mode by setting the corresponding DDR register bit. In this mode, writing “0” or “1” to the DR register applies this digital value to the I/O pin through the latch. Then reading the DR register returns the previously stored value. Note: In this mode, the interrupt function is disa- bled.
5.1.2.3 Digital Alternate Function
When an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. This alternate function takes priority over standard I/O programming. When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin has to be configured in input mode. In this case, the pin’s state is also digitally readable by addressing the DR register. Notes: 1. Input pull-up configuration can cause an unex- pected value at the input of the alternate peripher- al input. 2. When the on-chip peripheral uses a pin as input and output, this pin must be configured as an input (DDR = 0). Warning : The alternate function must not be acti- vated as long as the pin is configured as input with interrupt, in order to avoid generating spurious in- terrupts.
5.1.2.4 Analog Alternate Function
5.1.3 I/O Port Implementation
spurious interrupt generation. Figure 19. Recommended I/O State Transition Diagram
Figure 20. I/O Block Diagram Table 10. Port Mode Configuration – No OR Register on some ports (see register map). – ADC Switch on ports with analog alternate functions.
Table 11. Port Configuration
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 I/O PORTS (Cont’d)
5.1.4 Register Description
5.1.4.1 Data registers
Port A Data Register (PADR) Port B Data Register (PBDR) Port C Data Register (PCDR) Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 = D7-D0 Data Register 8 bits. The DR register has a specific behaviour accord- ing to the selected input/output configuration. Writ- ing the DR register is always taken in account even if the pin is configured as an input. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital val- ue applied to the I/O pin (pin configured as input).
5.1.4.2 Data direction registers
Port A Data Direction Register (PADDR) Port B Data Direction Register (PBDDR) Port C Data Direction Register (PCDDR) Read/Write Reset Value: 0000 0000 (00h) (input mode) Bit 7:0 = DD7-DD0 Data Direction Register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bit is set and cleared by software. 0: Input mode 1: Output mode
5.1.4.3 Option registers
Port A Option Register (PAOR) Port B Option Register (PBOR) Port C Option Register (PCOR) Read/Write Reset Value: 0000 0000 (00h) (no interrupt) Bit 7:0 = O7-O0 Option Register 8 bits. For specific I/O pins, this register is not implement- ed. In this case the DDR register is enough to se- lect the I/O pin configuration. The OR register allow to distinguish: in input mode if the interrupt capability or the floating configura- tion is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: input interrupt with or without pull-up Output mode (only for PB0:PB7, PC0:PC5): 0: output open drain (with P-Buffer inactivated) 1: output push-pull Output mode (only for PA0:PA7): 0: output open drain 1: reserved D7 D6 D5 D4 D3 D2 D1 D0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 O7 O6 O5 O4 O3 O2 O1 O0
Table 12. I/O Port Register Map and Reset Values
5.2 WATCHDOG TIMER (WDG)
5.2.1 Introduction
5.2.2 Main Features
Figure 21. Watchdog Block Diagram
5.2.3 Functional Description
programmed by the user in 64 increments. Table 13. Watchdog Timing (f set (the WDGA bit is set and the T6 bit is cleared).
5.2.4 Low Power Modes
5.2.5 Interrupts
5.2.6 Register Description
Bit 7 = WDGA Activation bit. watchdog can generate a reset. Table 14. Watchdog Timer Register Map and Reset Values
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 5.3 16-BIT TIMER
5.3.1 Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input sig- nals ( input capture) or generating up to two output waveforms (output compare and PWM ). Pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequen- cies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).
5.3.2 Main Features
■ Programmable prescaler: fCPU divided by 2, 4 or 8. ■ Overflow status flag and maskable interrupt ■ External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge ■ Output compare functions with: – 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt ■ Input capture functions with: – 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt ■ Pulse Width Modulation mode (PWM) ■ One Pulse mode ■ 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 1. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be ‘1’.
5.3.3 Functional Description
5.3.3.1 Counter
The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): – Counter High Register (CHR) is the most sig- nificant byte (MS Byte). – Counter Low Register (CLR) is the least sig- nificant byte (LS Byte). Alternate Counter Register (ACR) – Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). – Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit tim- er). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 1. The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles de- pending on the CC[1:0] bits. The timer frequency can be f CPU /2, fCPU /4, fCPU /8 or an external frequency.
Figure 22. Timer Block Diagram
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they re- turn the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, out- put compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: – The TOF bit of the SR register is set. – A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).
5.3.3.2 External Clock
The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the exter- nal clock pin EXTCLK that will trigger the free run- ning counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the CPU clock frequency. is buffered Read At t0 Read Returns the buffered LS Byte value at t0At t0 +Δ t Other instructions Beginning of the sequence Sequence completed LS Byte LS Byte MS Byte
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d)
5.3.3.3 Input Capture
In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter after a transition is detected by the ICAP i pin (see figure 5). The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU /CC[1:0]). Procedure: To use the input capture function, select the fol- lowing in the CR2 register: – Select the timer clock (CC[1:0]) (see Table 1). – Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input). And select the following in the CR1 register: – Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1pin must be configured as a floating input). When an input capture occurs: – The ICF i bit is set. – The ICiR register contains the value of the free running counter on the active transition on the ICAP i pin (see Figure 6). – A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Other- wise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICF i bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input cap- ture function. Moreover if one of the ICAP i pin is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the ICIE bit is set. This can be avoided if the input capture func- tion i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh). MS Byte LS Byte ICiR IC iHR IC iLR
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d)
5.3.3.4 Output Compare
In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Com- pare register and the free running counter, the out- put compare function: – Assigns pins with a programmable value if the OCIE bit is set – Sets a flag in the status register – Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC iR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/ CC[1:0]). Procedure: To use the output compare function, select the fol- lowing in the CR2 register: – Set the OCiE bit if an output is needed then the OCMP i pin is dedicated to the output compare i signal. – Select the timer clock (CC[1:0]) (see Table 1). And select the following in the CR1 register: – Select the OLVLi bit to applied to the OCMPi pins after the match occurs. – Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: – OCF i bit is set. – The OCMP i pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). – A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). The OC iR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: Δt = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 de- pending on CC[1:0] bits, see Table 1) If the timer clock is an external clock, the formula is: Where: Δt = Output compare period (in seconds) fEXT = External timer clock frequency (in hertz) Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to pre- vent the OCFi bit from being set between the time it is read and the write to the OCiR register: – Write to the OCiHR register (further compares are inhibited). – Read the SR register (first step of the clearance of the OCFi bit, which may be already set). – Write to the OCiLR register (enables the output compare function and clears the OCFi bit). MS Byte LS Byte OC iRO C iHR OC iLR Δ OCiR = Δt * fCPU PRESC Δ OCiR = Δ t * fEXT
- After a processor write cycle to the OCiHR reg-
until the OCiLR register is also written.
- If the OCiE bit is not set, the OCMPi pin is a
could be generated if the OCIE bit is set.
- When the timer clock is f
behaviour is the same in OPM or PWM mode. ter value plus 1 (see Figure 9).
- The output compare functions can be used both
- The value in the 16-bit OC
waveform or establish a new elapsed timeout. Figure 28. Output Compare Block Diagram
16 BIT FREE RUNNING
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d)
5.3.3.5 One Pulse Mode
One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded- icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 1). Then, on a valid event on the ICAP1 pin, the coun- ter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the Input Capture interrupt request (i.e. clearing the ICF i bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the fol- lowing formula: Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depend- ing on the CC[1:0] bits, see Table 1) If the timer clock is an external clock the formula is: Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 10). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedi- cated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedi- cated to One Pulse mode. event occurs Counter = OC1R OCMP1 = OLVL1 When When on ICAP1 One Pulse mode cycle OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set OC iR Value = t * fCPU PRESC - 5 OCiR = t * fEXT -5
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d)
5.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the com- plete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corre- sponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the oppo- site column. 3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after a successful comparison with OC1R register. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat- ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 1). If OLVL1=1 and OLVL2=0, the length of the posi- tive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OC iR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: t = Signal or pulse period (in seconds) f CPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depend- ing on CC[1:0] bits, see Table 1) If the timer clock is an external clock the formula is: Where: t = Signal or pulse period (in seconds) f EXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 11) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OC iLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the coun- ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is discon- nected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. Counter OCMP1 = OLVL2 Counter = OC2R OCMP1 = OLVL1 When When = OC1R Pulse Width Modulation cycle Counter is reset to FFFCh ICF1 bit is set OC iR Value = t * fCPU PRESC - 5 OCiR = t * fEXT -5
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d)
5.3.4 Low Power Modes
5.3.5 Interrupts
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap- ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
5.3.6 Summary of Timer modes
1) See note 4 in Section 0.1.3.5 One Pulse Mode 2) See note 5 in Section 0.1.3.5 One Pulse Mode 3) See note 4 in Section 0.1.3.6 Pulse Width Modulation Mode Mode Description WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. HALT 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAP i pin, the input capture detection circuitry is armed. Consequent- ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE Yes No Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 OCIE Yes No Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes No MODES AVAILABLE RESOURCES Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) Yes Yes Yes Yes One Pulse mode No Not Recommended 1) No Partially 2) PWM Mode No Not Recommended 3) No No
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d)
5.3.7 Register Description
Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no suc- cessful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg- ister and OCxE is set in the CR2 register. This val- ue is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin when- ever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Output Compare 1 Pin Enable. free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Output Compare 2 Pin Enable. free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. 0: One Pulse mode is not active. contents of the OC1R register. Table 15. Clock Control Bits on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter has rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2-0 = Reserved, forced by hardware to 0. INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. ICF1 OCF1 TOF ICF2 OCF2 0 0 0 70 MSB LSB MSB LSB MSB LSB MSB LSB
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit. ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register. INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event). INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the In- put Capture 2 event). MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB
Table 16. 16-Bit Timer Register Map and Reset Values
5.4 SERIAL PERIPHERAL INTERFACE (SPI)
5.4.1 Introduction
which devices may be either masters or slaves.
5.4.2 Main Features
■ Maximum slave mode frequency = fCPU/2. ■ Master mode fault protection capability.
5.4.3 General description
must be programmed with the same timing mode. Figure 33. Serial Peripheral Interface Master/Slave
Figure 34. Serial Peripheral Interface Block Diagram
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d)
5.4.4 Functional Description
Figure 1 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer to the CR, SR and DR registers in Section 0.1.7 for the bit definitions.
5.4.4.1 Master Configuration
In a master configuration, the serial clock is gener- ated on the SCK pin. Procedure – Select the SPR0 & SPR1 bits to define the se- rial clock baud rate (see CR register). – Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 4). –T h e S S pin must be connected to a high level signal during the complete byte transmit se- quence. – The MSTR and SPE bits must be set (they re- main set only if the SS pin is connected to a high level signal). In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is writ- ten the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A read to the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d)
5.4.4.2 Slave Configuration
In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – For correct data transfer, the slave device must be in the same timing mode as the mas- ter device (CPOL and CPHA bits). See Figure –T h e S S pin must be connected to a low level signal during the complete byte transmit se- quence. – Clear the MSTR bit and set the SPE bit to as- sign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2.A read to the DR register. Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 0.1.4.6 ). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 0.1.4.4 ).
5.4.4.3 Data Transfer Format
ed do not interfere with the SPI transfer. by software, using the CPOL and CPHA bits. be driven by the master device. clock edge before the capture clock edge. the occurrence of the second clock transition. currence of the first clock transition. each byte transmitted (see Figure 3). Figure 35. CPHA / SS Timing Diagram
Figure 36. Data Clock Timing Diagram Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.
5.4.4.4 Write Collision Error
the software write will be unsuccessful. nal MISO pin of the slave device. (SCK) is in the process of transfer. is set (the WCOL bit is a status flag only). Figure 37. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d)
5.4.4.5 Master Mode Fault
Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. – The SPE bit is reset. This blocks all output from the device and disables the SPI periph- eral. – The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing se- quence of the MODF bit. The SPE and MSTR bits may be restored to their original state during or af- ter this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine.
5.4.4.6 Overrun Condition
An overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripher- al.
5.4.4.7 Single Master and Multimaster Configurations
that time, thus disabling the slave devices. through the serial peripheral interface system. Figure 38. Single Master Configuration
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d)
5.4.5 Low Power Modes
5.4.6 Interrupts
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Transfer Event SPIF SPIE Yes No Master Mode Fault Event MODF Yes No
5.4.7 Register Description
Serial peripheral interrupt enable. This bit is set and cleared by software. Bit 6 = SPE Serial peripheral output enable. (see Section 0.1.4.5 Master Mode Fault). eral is not initially connected to the external pins. Bit 5 = SPR2 Divider Enable. set the baud rate. Refer to Table 1. (see Section 0.1.4.5 Master Mode Fault). 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. This bit is set and cleared by software. Bit 1:0 = SPR[1 :0] Serial peripheral rate. These 2 bits have no effect in slave mode. Table 17. Serial Peripheral Baud Rate
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a soft- ware sequence (an access to the SR register fol- lowed by a read or write to the DR register). 0: Data transfer is in progress or has been ap- proved by a clearing sequence. 1: Data transfer between the device and an exter- nal device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 5). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 0.1.4.5 Master Mode Fault). An SPI interrupt can be gen- erated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused. DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/re- ception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A write to the the DR register returns the value lo- cated in the buffer and not the contents of the shift register (See Figure 2 ). S P I F W C O L - M O D F ---- D7 D6 D5 D4 D3 D2 D1 D0
Table 18. SPI Register Map and Reset Values
5.5.1 Introduction
levels from up to 8 different sources. through a Control/Status Register.
5.5.2 Main Features
The block diagram is shown in Figure 1. Figure 39. ADC Block Diagram
5.5.3 Functional Description
loaded or badly decoupled power supply lines. Figure 40. Recommended Ext. Connections never increases if the analog input does not. scale) without overflow indication. cluding a sampling time of 31.5 CPU clock cycles. Electrical Characteristics Section. tion for the bit definitions. log channel to convert. Refer to Table 1. – The COCO bit is set by hardware. – No interrupt is generated. – The result is in the DR register.
5.5.4 Low Power Modes
5.5.5 Interrupts
5.5.6 Register Description
0: Conversion is not complete. 1: Conversion can be read from the DR register. Bit 6 = Reserved. Must always be cleared. This bit is set and cleared by software. 0: A/D converter is switched off. 1: A/D converter is switched on. the ADC to stabilize when the ADON bit is set. Bit 4 = Reserved. Forced by hardware to 0. Bit 3 = Reserved. Must always be cleared. select the analog input to convert. Table 19. Channel Selection the channel selection vary according to the device. REFER TO THE DEVICE PINOUT). Reading this register resets the COCO flag. Table 20. ADC Register Map
6 INSTRUCTION SET
6.1 ST7 ADDRESSING MODES
Table 21. ST7 Addressing Mode Overview
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 ST7 ADDRESSING MODES (Cont’d)
6.1.1 Inherent
All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation.
6.1.2 Immediate
Immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value.
6.1.3 Direct
In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub- modes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF address- ing space. Direct (long) The address is a word, thus allowing 64 Kbyte ad- dressing space, but requires 2 bytes after the op- code.
6.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte ad- dressing space and requires 2 bytes after the op- code.
6.1.5 Indirect (Short, Long)
The required data byte to do the operation is found by its memory address, located in memory (point- er). The pointer address follows the opcode. The indi- rect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations
6.1.6 Indirect Indexed (Short, Long)
er address follows the opcode. and requires 1 byte after the opcode. and requires 1 byte after the opcode. Table 22. Instructions Supporting Direct,
6.1.7 Relative Mode (Direct, Indirect)
register value by adding an 8-bit signed offset to it. The offset follows the opcode.
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213
6.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available op- codes for an 8-bit CPU (256 opcodes), three differ- ent prebyte opcodes are defined. These prebytes modify the meaning of the instruction they pre- cede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruc- tion using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Code Condition Flag modification SIM RIM SCF RCF
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2's compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213
7 ELECTRICAL CHARACTERISTICS
7.1 ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that V I and VO be higher than VSS and lower than VDD . Reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (VDD or VSS ). Power Considerations.The average chip-junc- tion temperature, TJ, in Celsius can be obtained from: TJ= TA + PD x RthJA Where: TA = Ambient Temperature. RthJA = Package thermal resistance (junction-to ambient). PD = P INT + PPORT . PINT =IDD x VDD (chip internal power). PPORT =Port power dissipation determined by the user) Note: Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Symbol Parameter Value Unit VDD Supply Voltage -0.3 to 6.0 V VI Input Voltage V SS - 0.3 to VDD + 0.3 V VAI Analog Input Voltage (A/D Converter) V SS - 0.3 to VDD + 0.3 V VO Output Voltage V SS - 0.3 to VDD + 0.3 V IVDD Total Current into VDD (source) 80 mA IVSS Total Current out of VSS (sink) 80 mA TJ Junction Temperature 150 °C TSTG Storage Temperature -60 to 150 °C
7.2 RECOMMENDED OPERATING CONDITIONS
Note 1: A/D operation and Oscillator start-up are not guaranteed below 1MHz. Figure 41. Maximum Operating Frequency (fOSC ) Versus Supply Voltage (VDD )
1 Suffix Version 0 70 °C
6 Suffix Version -40 85 °C
3 Suffix Version -40 125 °C
16 MHz
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213
7.3 DC ELECTRICAL CHARACTERISTICS
(TA = -40°C to +125°C and VDD = 5V unless otherwise specified) Notes: 1. Hysteresis voltage between switching levels. Based on characterisation results, not tested. 2. CPU running with memory access, no DC load or activity on I/O’s; clock input (OSCIN) driven by external square wave. 3. No DC load or activity on I/O’s; clock input (OSCIN) driven by external square wave. 4. Except OSCIN and OSCOUT 5. WAIT Mode with SLOW Mode selected. Based on characterisation results, not tested. Symbol Parameter Test Conditions Value Unit Min. Typ. Max. VIL Input Low Level Voltage All Input pins 3V < VDD < 5.5V V DD x 0.3 V VIH Input High Level Voltage All Input pins 3V < VDD < 5.5V V DD x 0.7 V VHYS Hysteresis Voltage 1) All Input pins 400 mV VOL Low Level Output Voltage All Output pins IOL = +10µA IOL = + 2mA 0.1 0.4 VLow Level Output Voltage High Sink I/O pins IOL = +10µA IOL = +10mA IOL = + 15mA IOL = + 20mA, TA = 85°C max 0.1 1.5 3.0 3.0 VOH High Level Output Voltage All Output pins IOH = - 10µA IOH = - 2mA 4.9 4.2 V IIL IIH Input Leakage Current All Input pins but RESET 4) VIN = VSS (No Pull-up configured) VIN = VDD 0.1 1.0 µA IIH Input Leakage Current RESET pin VIN = VDD 0.1 1.0 R ON Reset Weak Pull-up RON VIN > VIH VIN < VIL 120 240 kΩ R PU I/O Weak Pull-up RPU VIN < VIL 100 k Ω IDD Supply Current in RUN Mode 2) fOSC = 4 MHz, fCPU = 2 MHz fOSC = 8 MHz, fCPU = 4 MHz fOSC = 16 MHz, fCPU = 8 MHz 5.5 mA Supply Current in SLOW Mode 2) fOSC = 4 MHz, fCPU = 125 kHz fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz 1.5 2.5 mA Supply Current in WAIT Mode 3) fOSC = 4MHz, fCPU = 2MHz fOSC = 8MHz, fCPU = 4 MHz fOSC = 16MHz, fCPU = 8 MHz 3.5 mA Supply Current in WAIT -MINI- MUM Mode 5) fOSC = 4 MHz, fCPU = 125 kHz fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz 0.8 1.6 1.5 3.5 mA Supply Current in HALT Mode ILOAD = 0mA, TA = 85°C max ILOAD = 0mA 20 µA
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213
7.4 RESET CHARACTERISTICS
(TA=-40...+125oC and VDD =5V±10% unless otherwise specified. Note: 1) These values given only as design guidelines and are not tested.
7.5 OSCILLATOR CHARACTERISTICS
(TA = -40°C to +125°C unless otherwise specified) Symbol Parameter Conditions Min Typ 1) Max Unit R ON Reset Weak Pull-up RON VIN > VIH VIN < VIL 120 240 kΩ tRESET Pulse duration generated by watch- dog and POR reset 1 µs tPULSE Minimum pulse duration to be ap- plied on external RESET pin 10 1) ns Symbol Parameter Test Conditions Value Unit Min. Typ. Max. gm Oscillator transconductance 2 9 mA/V fOSC Crystal frequency 1 16 MHz tSTART Osc. start up time V DD = 5V±10% 50 ms
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213
7.6 A/D CONVERTER CHARACTERISTICS (ST72212 and ST72213 only)
(TA = -40°C to +125°C and VDD = 5V±10% unless otherwise specified ) *Note: ADC Accuracy vs. Negative Injection Current: For Iinj-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB by 10KΩ increase of the external analog source impedance. These measurement results and recommendations take worst case injection conditions into account: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V V DD supply, and worst case temperature. Symbol Parameter Conditions Min Typ Max Unit TSAMPLE Sample Duration 31.5 1/f CPU Res ADC Resolution fCPU =8MHz VDD =VDDA =5V 8 bit DLE Differential Linearity Error* ±0.6 ±1 ILE Integral Linearity Error* ±2 VAIN Analog Input Voltage V SSA VDDA V IADC Supply current rise during A/D conversion fCPU =8MHz VDD =VDDA =5V 1m A tSTAB Stabilization time after ADC enable 30 µs tCONV Conversion Time 8 µs 1/fCPU R AIN Resistance of analog sources (VAIN) fCPU =8MHz, T=25°C, VDD =VDDA =5V 15 ΚΩ C HOLD Hold Capacitance 22 pF R SS Resistance of sampling switch and internal trace 2 ΚΩ Px.x/AINx R AIN VAIN C pin 5pF VDD VT = 0.6V leakage max.VT = 0.6V C pin VT leakage C hold SS Sampling Switch SS R SS at the pin due to various junctions C hold 22 pF capacitance = input capacitance = threshold voltage = sampling switch = sample/hold ±1µA VSS = leakage current 2ΚΩ
Figure 42. ADC conversion characteristics
1 LSB (ideal)
7.7 SPI CHARACTERISTICS
Figure 43. SPI Master Timing Diagram CPHA=0, CPOL=0
8 GENERAL INFORMATION
8.1 EPROM ERASURE
lighting may also cause erasure. dow without any interposed filters.
8.2 PACKAGE MECHANICAL DATA
Figure 51. 28-Pin Plastic Small Outline Package, 300-mil Width
8.3 ORDERING INFORMATION
available on the target device.
8.3.1 Transfer Of Customer Code
used bytes must be set to FFh. Figure 54. ROM Factory Coded Device Types Figure 55. OTP User Programmable Device Types Note: The ST72E251G2D0 (CERDIP 25 °C) is used as the EPROM version for the above devices.
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213 ST72101, ST72213 and ST72212 MICROCONTROLLER OPTION LIST STMicroelectronics references Device: [ ] ST72101 [ ] ST72212 [ ] ST72213 Package: [ ] Dual in Line Plastic [ ] Small Outline Plastic with conditioning: [ ] Standard (Stick) [ ] Tape & Reel Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C [ ] - 40°C to + 125°C Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: SDIP32: 10 SO28: 8 Comments: Supply Operating Range in the application: Oscillator Frequency in the application:
Obsolete Product(s) - Obsolete Product(s) ST72101/ST72212/ST72213
9 SUMMARY OF CHANGES
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com Change Description (Rev. 1.5 to 1.6) Page Added new External Connections section 9 Removed RP external resistor 16 Changed ORed to ANDed in External interrupts paragraph, to read “If several input pins, con- nected to the same interrupt vector, are configured as interrupts, their signals are logically AN- Ded before entering the edge/level detection block”. 18 and 24 Added note ”Any modification of one of these two bits resets the interrupt request related to this interrupt vector.” 23 Added clamping diodes to I/O pin figure and table 26 Added sections on low power modes and interrupts to peripheral descriptions 31,43,58,63 Changed 16-bit Timer Chapter 32 to 48 Added details to description of FOLV1 and FOLV2 bits 44 Added ADC recommended external connections 63 Added Reset characteristics section 74 Added figure to ADC electrical characteristics section 75 Change Description (Rev. 1.6 to 1.7) SPR2 bit reinstated in SPI chapter 49 to 61 Change Description (Rev. 1.7 to 1.8) of 31 May 2001 SPI frequency changed from f CPU /2 to fCPU /4 in Table 17.6 0