ST72141K

ST72141K STMICROELECTRONICS | Alldatasheet

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Rev. 1.8 October 2001 1/132 ST72141K 8-BIT MCU WITH ELECTRIC-MOTOR CONTROL, ADC, 16-BIT TIMERS, SPI INTERFACE ■ Memories – 8K Program memory (ROM/OTP/EPROM) – 256 Bytes RAM ■ Clock, Reset and Supply Management – Enhanced reset system – Low voltage supply supervisor – 3 Power saving modes ■ 14 I/O Ports – 14 multifunctional bidirectional I/O lines with: External interrupt capability (2 vectors), 13 al- ternate function lines, 3 high sink outputs ■ Motor Control peripheral – 6 PWM output channels – Emergency pin to force outputs to HiZ state – 3 analog inputs for rotor position detection with no need for additional sensors – Comparator for current limitation ■ 3 Timers – Two 16-bit timers with: 2 input captures, 2 out- put compares, external clock input, PWM and Pulse generator modes – Watchdog timer for system integrity ■ Communications Interface – SPI synchronous serial interface ■ Analog Peripheral – 8-bit ADC with 8 input pins ■ Instruction Set – 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation ■ Development Tools – Full hardware/software development package Device Summary SDIP32 SO34S Features ST72141K2 Program memory - bytes 8K RAM (stack) - bytes 256 (64) Peripherals Motor control, Watchdog, Two 16-bit timers, SPI, ADC Operating Supply 4V to 5.5V CPU Frequency 4 or 8 MHz (with 8 or 16 MHz oscillator) Operating Temperature -40°C to +85°C / -40°C to +125°C

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

Figure 1. Example of a 6-step-controlled Motor Figure 2. Device Block Diagram

1.2 PIN DESCRIPTION

Figure 3. 34-Pin SO Package Pinout Figure 4. 32-Pin SDIP Package Pinout

R = 70Ω /100Ω ratio of logical levels. Note: the Reset configuration of each pin is shown in bold. Table 1. Device Pin Description

9 NC Not Connected

20 21 PA3/OCMP2_B/AIN3 I/O C T X EI0 X X X Port A3 Timer B Output Compare 2 or ADC Analog Input 3 21 22 PA4/OCMP1_B/AIN4 I/O C T X EI0 X X X Port A4 Timer B Output Compare 1 or ADC Analog Input 4 22 23 PA5/ICAP2_A/AIN5 I/O C T X EI0 X X X Port A5 Timer A Input Capture 2 or ADC Analog Input 5 23 24 PA6/ICAP1_A/AIN6 I/O C T X EI0 X X X Port A6 Timer A Input Capture 1 or ADC Analog Input 6 24 25 PA7/OCMP2_A/AIN7 I/O C T X EI0 X X X Port A7 Timer A Output Compare 2 or ADC Analog Input 7

26 NC Not Connected

25 27 OCMP1_A O R Timer A Output Compare 1 26 28 V PP I Must be tied low during normal operating mode,EPROM Programming voltage pin. 27 29 V SS S Ground 28 30 V DD S Main power supply 29 31 MCCFI I A Motor Control Current Feedback Input 30 32 MCIC I A Motor Control Input C 31 33 MCIB I A Motor Control Input B 32 34 MCIA I A Motor Control Input A Pin n° Pin Name Type Level Port / Control Main Function (after reset) Alternate Function SDIP32 SO34 Input Output Input Output float wpu int ana OD PP

1.3 EXTERNAL CONNECTIONS

ternal connections for the device. necessary power consumption on floating lines. ports as inputs with pull-up. Figure 5. Recommended External Connections

1.4 REGISTER & MEMORY MAP

dressing 64K bytes of memories and I/O registers. Figure 6. Memory Map Table 2. Interrupt Vector Map

256 Bytes RAM

Table 3. Hardware Register Map

Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0050h to 005Fh Reserved Area (16 Bytes) 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh MOTOR CONTROL MTIM MZPRV MZREG MCOMP MDREG MWGHT MPRSR MIMR MISR MCRA MCRB MPHST MPAR MPOL Timer Counter Register Zn-1 Capture Register Zn Capture Register C n+1Compare Register D capture/Compare Register Weight Register Prescaler and Ratio Register Interrupt Mask Register Interrupt Status Register Control Register A Control Register B Phase State Register Output Parity Register Output Polarity Register 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 006Eh to 006Fh Reserved Area (2 bytes) 0070h 0071h ADC ADCDR ADCCSR Data Register Control/Status Register 00h 00h Read Only R/W 0072h to 007Fh Reserved Area (14 Bytes) Address Block Register Label Register Name Reset Status Remarks

1.5 EPROM PROGRAM MEMORY

The program memory of the OTP and EPROM de- vices can be programmed with EPROM program- ming tools available from STMicroelectronics. EPROM Erasure EPROM devices are erased by exposure to high intensity UV light admitted through the transparent window. This exposure discharges the floating gate to its initial state through induced photo cur- rent. It is recommended that the EPROM devices be kept out of direct sunlight, since the UV content of sunlight can be sufficient to cause functional fail- ure. Extended exposure to room level fluorescent lighting may also cause erasure. An opaque coating (paint, tape, label, etc...) should be placed over the package window if the product is to be operated under these lighting con- ditions. Covering the window also reduces I DD in power-saving modes due to photo-diode leakage currents.

2 CENTRAL PROCESSING UNIT

2.1 INTRODUCTION

2.2 MAIN FEATURES

2.3 CPU REGISTERS

temporary storage areas for data manipulation. (Program Counter High which is the MSB). Figure 7. CPU Registers

CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions. These bits can be individually tested and/or con- trolled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET in- structions and is tested by the JRM and JRNM in- structions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- tions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. 111HIN Z C

ways pointing to the next free location in the stack. popped from the stack (see Figure 8). mented and the context is pushed on the stack. and the context is popped from the stack. terrupt five locations in the stack area. Figure 8. Stack Manipulation Example

0 SP6 SP5 SP4 SP3 SP2 SP1 SP0

3 SUPPLY, RESET AND CLOCK MANAGEMENT

overview is shown in Figure 9. Figure 9. Clock, RESET, Option and Supply Management Overview

3.1 LOW VOLTAGE DETECTOR (LVD)

well as the power-down keeping the ST7 in reset. The LVD function is illustrated in Figure 10. Figure 10. Low Voltage Detector vs Reset

3.2 RESET MANAGER

dresses FFFEh-FFFFh in the ST7 memory map. Figure 11. Reset Block Diagram

fully stabilize before executing the first instruction. ly following the internal delay. Figure 12. External RESET Sequences

4096 CLOCK CYCLES

up to VLVDr (see Figure 13). Figure 13. LVD RESET Sequences

Figure 14. Watchdog RESET Sequence

3.3 LOW CONSUMPTION OSCILLATOR

pin is tied to VSS (see Figure 15). Figure 15. External Clock output distortion and start-up stabilization time. Figure 16. Crystal/Ceramic Resonator

3.4 MAIN CLOCK CONTROLLER (MCC)

two bits of the MISCR register: SMS and XT16. CPU and the other peripherals. Figure 17. Main Clock Controller (MCC) Block DiagramDIV 2

4 INTERRUPTS

The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: – Normal processing is suspended at the end of the current instruction execution. – The PC, X, A and CC registers are saved onto the stack. – The I bit of the CC register is set to prevent addi- tional interrupts. – The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector address- es). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be inter- rupted because the I bit is set by hardware enter- ing in interrupt routine. In the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the Interrupt Map- ping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifi- cally mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT“ column in the Interrupt Mapping Ta- ble).

4.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc- tion is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 18.

4.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same inter- rupt vector, are configured as interrupts, their sig- nals are logically NANDed before entering the edge/level detection block. Caution: The type of sensitivity defined in the Mis- cellaneous or Interrupt register (if available) ap- plies to the ei source. In case of a NANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity.

4.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: – The I bit of the CC register is cleared. – The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status register or – Access to the status register while the flag is set followed by a read or write of an associated reg- ister. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed.

Figure 18. Interrupt Processing Flowchart

Table 4. Interrupt Mapping

0 Not used FFFAh-FFFBh

4 Motor Control Interrupt (events: C, D) no FFF2h-FFF3h

5 Motor Control Interrupt (events: E, O) no FFF0h-FFF1h

6 SPI SPI Peripheral Interrupts SPISR no FFEEh-FFEFh

7 TIMER A TIMER A Peripheral Interrupts TASR no FFECh-FFEDh

8 TIMER B TIMER B Peripheral Interrupts TBSR no FFEAh-FFEBh

9 Not used FFE8h-FFE9h

10 Not used FFE6h-FFE7h

11 Not used FFE4h-FFE5h

12 Not Used FFE2h-FFE3h

13 Not Used FFE0h-FFE1h

5 POWER SAVING MODES

5.1 Introduction

Figure 19. Power saving mode consumption / transitionsPOWER CONSUMPTION

5.2 HALT Mode

ST7 HALT instruction (see Figure 21). ther an external interrupt or a reset (see Table 2). Register is forced to 0 to enable interrupts. cluding the operation of the on-chip peripherals. Figure 20. HALT Mode timing overview Figure 21. HALT modes flow-chart ** Before servicing an interrupt, the CC register is pushed on the stack.

5.3 WAIT Mode

sumption mode by stopping the CPU. “WFI” ST7 software instruction. address of the interrupt or Reset service routine. or an Interrupt occurs, causing it to wake up.

5.4 SLOW Mode

the available supply voltage. ed by 32 instead of 2 in normal operating mode. bit (XT16) in the MISCR register. Figure 22. WAIT mode flow-chart clock cycle delay is inserted. Note: * The peripheral clock is stopped only when exit caused by RESET and not by an interrupt. ** Before servicing an interrupt, the CC register is pushed on the stack.

6 I/O PORTS

6.1 INTRODUCTION

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

6.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre- sponding register bits in the DDR and OR regis- ters: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not pro- vide this register refer to the I/O Port Implementa- tion section). The generic I/O block diagram is shown in Figure 23

6.2.1 Input Modes

The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external inter- rupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Mis- cellaneous register. Each external interrupt vector is linked to a dedi- cated group of I/O port pins (see pinout description and interrupt section). If several input pins are se- lected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configura- tion, special care must be taken when changing the configuration (see Figure 24). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellane- ous register must be modified.

6.2.2 Output Modes

The output configuration is selected by setting the corresponding DDR register bit. In this case, writ- ing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR reg- ister returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:

6.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip periph- eral, the I/O pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. DR Push-pull Open-drain 0V SS Vss 1V DD Floating

Figure 23. I/O Port General Block Diagram Table 5. I/O Port Mode Options vice against positive stress.

Table 6. I/O Port Configurations

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

1. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

6.3 I/O PORT IMPLEMENTATION

such as spurious interrupt generation. Figure 24. Interrupt I/O Port State Transitions

Table 7. Port Configuration

I/O PORTS (Cont’d)

6.3.1 Register Description

DATA REGISTER (DR) Port x Data Register PxDR with x = A or B. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour accord- ing to the selected input/output configuration. Writ- ing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A or B. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode OPTION REGISTER (OR) Port x Option Register PxOR with x = A or B. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implement- ed. In this case the DDR register is enough to se- lect the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: pull-up input with or without interrupt Output mode: 0: output open drain (with P-Buffer unactivated) 1: output push-pull (when available) D7 D6 D5 D4 D3 D2 D1 D0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 O7 O6 O5 O4 O3 O2 O1 O0

Table 8. I/O Port Register Map and Reset Values

7 MISCELLANEOUS REGISTER

terrupts or the I/O alternate functions.

7.1 I/O Port Interrupt Sensitivity Description

Figure 25. External Interrupt Sensitivity

7.2 I/O Port Alternate Functions

7.4 Miscellaneous Register Description.

7.3 Clock Prescaler Selection

7.4 Miscellaneous Register Description

mum allowed frequency is 4MHz. This bit is set and cleared by software. This bit is set and cleared by software. Table 9. Miscellaneous Register Map and Reset Values

8 ON-CHIP PERIPHERALS

8.1 MOTOR CONTROLLER (MTC)

8.1.1 Introduction

time to be applied before BEMF monitoring.

8.1.2 Main Features

asynchronously forces the outputs in HiZ. Table 10. MTC Registers

8.1.3 Application Example

shows the relevant phase configurations. cally generated after this delay. BEMF zero-crossing detection is enabled. pare feature when no detection is possible.

ble the peripheral to detect another Z event. plied on the high side switches. Figure 26. Chronogram of Events (in Autoswitched Mode)

Figure 27. Example of Command Sequence for 6-step Mode (typical 3-phase PMDC Motor Control) Note: Control & sampling PWM influence is not represented on these simplified chronograms.

Table 11. Step Configuration Summary For a detailed description of the MTC registers, see Section 8.1.7.

8.1.4 Functional Description

shown in the simplified block diagram in Figure 28. a comparator and an input multiplexer. (MTIM) and an 8x8 bit multiplier. emergency HiZ configuration input.

8.1.4.1 Input Detection Block

Figure 28. Simplified MTC Block Diagram

quired to add external pull-up Schottky 0.4 V (e.g. ther Sensorless or Sensor mode. Figure 29. Input Stage

and end of demagnetization events. Timer PWM frequency and duty cycle. uration bits as described in Table 12. event if spurious spikes occur. Table 12. ZVD and CPB Edge Selection Bits Note: The ZVD bit is located in the MPAR register, the CPB bit is in the MCRB register.

no longer goes through the free-wheeling diodes. used if the HDM bit is reset and the SDM bit is set. to avoid a spurious Z event. is generated if the DIM bit of register MIMR is set. should be manipulated with special care. Figure 30. D Event Generation Mechanism

Table 13. Demagnetisation (D) Event Generation (example for ZVD=0)

the PWM is applied on the high side drivers. and function mode of peripheral. an interrupt if the ZIM bit is set. Figure 31. Sampling and Zero Crossing Blocks

• = Preload register, changes taken into account at next C event.

the three inputs MCIA, MCIB and MCIC. are not available (see Table 14).

1. Select the appropriate MCIx input pin by means
2. Switch from direct access mode to indirect
3. Switch back to direct access mode.
4. Read the comparator output (HST bit in the

Table 14. Sensor mode selection

0 Sensors not

1 Sensors

Figure 32. Functional Diagram of Z Detection after D Event

Table 15. Modes permitting BEMF reading after Demagnetization (D event)

0 After D

000 Even 0

001 Odd 1

100 Even 0

101 Odd 1

110 Even 0

110 Odd 1

1 Not Used x xxx Odd or

8.1.4.2 Delay Manager

Figure 33. Overview of MTIM Timer rotor position information and register contents. Table 16. Switched and Autoswitched Modes ing the powerful interrupt set of the peripheral.

0 Switched mode Read/Write

1 Autoswitched mode Read only

loaded (registers marked with (*) in Section 8.1.7). MISR register is set an interrupt is generated. interrupt if the RIM bit is set. count, (at commutation) the RPI or RMI bit is reset. events do not affect the timer contents. Table 17. Step Ratio Update

Figure 34. Step Ratio Functional Diagram

low and in Figure 35. This register is READ ONLY. the MTIM timer is reset. See Figure 26. tents of the MWGHT register and divided by 32. Table 18. Multiplier Result OIM bit in the MIMR register. Figure 35. Commutation Processor Block is generated (timer overflow). pends on the motor symmetry and type. between the motor driven voltage and the BEMF. ware (see Section 8.1.4.2 for more details). is set and an interrupt is generated (if RIM is set). can no longer be automatically incremented. to these registers is summarised in Table 21.

0 MCOMP = MWGHT x MZPRV / 32

1 MCOMP = MWGHT x MZREG / 32

Table 19. MTIM Timer-related Registers 7Fh+(MCOMP+demagnetization_time-FFh)/2. and IS[1:0], OO[5:0] in the MPHST register.

values shown on the graph as the segment ends. quency goes out of this segment. Figure 36. Step Ratio Bits decoding and accuracy results and BEMF Sampling Rate

Table 20. Step Frequency/Period Range Table 21. Modes of Accessing MTIM Timer-Related Registers

8.1.4.3 PWM Manager

depending on the V0C1 bit in the MCRA register. A block diagram of this part is given in Figure 37. erated by the 16-bit A Timer. application (speed regulation for example). mandatory to set a current limitation. done during the PWM off time. ting the CFF bit in the MCRB register. Figure 37. Current Feedback

means of the SA[3:0] bits in the MPRSR register. Table 22. Off-Time Table Table 23. Sampling Frequency Selection Figure 38. Sampling clock generation block

4 MHz1

frequency can be selected in the Miscellaneous register.

8.1.4.4 Channel Manager

The block diagram is shown in Figure 39. Table 24. Output State Figure 39. Channel Manager Block Diagram

6 OS[2:0] bits*

• = Preload register, changes taken into account at next C event.

when the DAC bit in the MCRA register is set. Table 25. DAC and MOE Bit Meaning Table 26. Meaning of the OE[5:0] Bits – Enable Back EMF zero crossing detection. as shown in Figure 41, Figure 42 and Figure 40. voltage mode and in current mode. special configuration value: OS[2:0] = 010.

10 Standard run-

0 Even channel

1 Odd channel

Figure 40. Step Behaviour of one Output Channel MCO[n] in Voltage Mode

000 Odd

001 Even

MOTOR CONTROLLER (Cont’d)

8.1.5 Low Power Modes

Before executing a HALT or WFI instruction, soft- ware must stop the motor, and may choose to put the outputs in high impedance.

8.1.6 Interrupts

The MTC interrupt events are connected to the three interrupt vectors (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction). Mode Description WAIT No effect on MTC interface. MTC interrupts exit from Wait mode. HALT MTC registers are frozen. In Halt mode, the MTC interface is in- active. The MTC interface becomes operational again when the MCU is woken up by an interrupt with “exit from Halt mode” capability. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Ratio increment RPI RIM Yes No Ratio decrement RMI Yes No Multiplier overflow OI OIM Yes No Emergency Stop EI EIM Yes No BEMF Zero-Crossing ZI ZIM Yes No End of Demagnetization DI DIM Yes No Commutation CI CIM Yes No

MOTOR CONTROLLER (Cont’d)

8.1.7 Register Description

TIMER COUNTER REGISTER (MTIM) Read/Write Reset Value: 0000 0000 (00h) Bits 7:0 = T[7:0]: MTIM Counter Value. These bits contain the current value of the 8-bit up counter. CAPTURE Z n-1 REGISTER (MZPRV) Read/Write Reset Value: 0000 0000 (00h) Bits 7:0 = ZP[7:0]: Previous Z Value. These bits contain the previous captured BEMF value (ZN-1). CAPTURE Z n REGISTER (MZREG) Read/Write Reset Value: 0000 0000 (00h) Bits 7:0 = ZC[7:0]: Current Z Value. These bits contain the current captured BEMF val- ue (ZN ). COMPARE C n+1 REGISTER (MCOMP) Read/Write Reset Value: 0000 0000 (00h) Bits 7:0 = DC[7:0]: Next Compare Value. These bits contain the compare value for the next commutation (CN+1 ). DEMAGNETIZATION REGISTER (MDREG) Read/Write Reset Value: 0000 0000 (00h) Bits 7:0 = DN[7:0]: D Value. These bits contain the compare value for software demagnetization (DN ) and the captured value for hardware demagnetization (DH ). A N WEIGHT REGISTER (MWGHT) Read/Write Reset Value: 0000 0000 (00h) Bits 7:0 = AN[7:0]: A Weight Value. These bits contain the AN weight value for the mul- tiplier. In autoswitched mode the MCOMP register is automatically loaded with: when a Z event occurs. (*) depending on the DCB bit in the MCRA regis- ter. PRESCALER & SAMPLING REGISTER (MPRSR) Read/Write Reset Value: 0000 0000 (00h) Bits 7:4 = SA[3:0]: Sampling Ratio. These bits contain the sampling ratio value for cur- rent mode. Refer to Table 23. Bits 3:0 = ST[3:0]: Step Ratio. These bits contain the step ratio value. It acts as a prescaler for the MTIM timer and is auto incre- mented/decremented with each R+ or R- event. Refer to Table 20. T7 T6 T5 T4 T3 T2 T1 T0 Z P 7Z P 6Z P 5Z P 4Z P 3Z P 2Z P 1Z P 0 ZC7 ZC6 ZC5 ZC4 ZC3 ZC2 ZC1 ZC0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0 DN7 DN6 DN5 DN4 DN3 DN2 DN1 DN0 A N 7A N 6A N 5A N 4A N 3A N 2A N 1A N 0 SA3 SA2 SA1 SA0 ST3 ST2 ST1 ST0 Zn x MWGHT 32(d) or ZN -1 x MWGHT 32(d) (*)

MOTOR CONTROLLER (Cont’d) INTERRUPT MASK REGISTER (MIMR) Read/Write (except bits 7:6) Reset Value: 0000 0000 (00h) Bit 7 = HST : Hysteresis Comparator Value. This read only bit contains the hysteresis compa- rator output. 0: Demagnetisation/BEMF comparator is under V REF 1: Demagnetisation/BEMF comparator is above VREF Bit 6 = CL : Current Loop Comparator Value. This read only bit contains the current loop compa- rator output value. 0: Current detect voltage is under VCREF 1: Current detect voltage is above VCREF Bit 5 = RIM : Ratio update Interrupt Mask bit. 0: Ratio update interrupts (R+ and R-) disabled 1: Ratio update interrupts (R+ and R-) enabled Bit 4 = OIM : Multiplier Overflow Interrupt Mask bit. 0: Multiplier Overflow interrupt disabled 1: Multiplier Overflow interrupt enabled Bit 3 = EIM: Emergency stop Interrupt Mask bit. 0: Emergency stop interrupt disabled 1: Emergency stop interrupt enabled Bit 2 = ZIM: Back EMF Zero-crossing Interrupt Mask bit. 0: BEMF Zero-crossing Interrupt disabled 1: BEMF Zero-crossing Interrupt enabled Bit 1 = DIM : End of Demagnetization Interrupt Mask bit. 0: End of Demagnetization interrupt disabled 1: End of Demagnetization interrupt enabled if the HDM or SDM bit in the MCRB register is set Bit 0 = CIM : Commutation Interrupt Mask bit 0: Commutation Interrupt disabled 1: Commutation Interrupt enabled INTERRUPT STATUS REGISTER (MISR) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = Reserved. Forced by hardware to 0. Bit 6 = RPI: Ratio Increment interrupt flag. Autoswitched mode (SWA bit =0): 0: No R+ interrupt pending 1: R+ Interrupt pending Switched mode (SWA bit =1): 0: No R+ action 1: The hardware will increment the ST[3:0] bits when the next commutation occurs and shift all timer registers right. Bit 5 = RMI : Ratio Decrement interrupt flag. Autoswitched mode (SWA bit =0): 0: No R- interrupt pending 1: R- Interrupt pending Switched mode (SWA bit =1): 0: No R- action 1: The hardware will decrement the ST[3:0] bits when the next commutation occurs and shift all timer registers left. Bit 4 = OI: Multiplier Overflow interrupt flag. 0: No Multiplier Overflow interrupt pending 1: Multiplier Overflow interrupt pending Bit 3 = EI: Emergency stop Interrupt flag. 0: No Emergency stop interrupt pending 1: Emergency stop interrupt pending Bit 2 = ZI: BEMF Zero-crossing interrupt flag. 0: No BEMF Zero-crossing Interrupt pending 1: BEMF Zero-crossing Interrupt pending Bit 1 = DI: End of Demagnetization interrupt flag. 0: No End of Demagnetization interrupt pending 1: End of Demagnetization interrupt pending Bit 0 = CI: Commutation interrupt flag 0: No Commutation Interrupt pending 1: Commutation Interrupt pending HST CL RIM OIM EIM ZIM DIM CIM 0R P I R M I O IE I Z I D IC I

Table 27. Step Ratio Update Bit 6 = RST : Reset MTC registers. Table 28. Sensor Mode Selection Bit 4 = DAC : Direct Access to phase state register. into account at the C event. ter are taken into account at the same time. Table 29. DAC Bit Meaning write access, a reset can be done by software. no PWM signal generation in this mode. Table 30. Switched and Autoswitched Modes

10 Ena-

11 Ena-

0 Tristate

1 Output enabled

10 Standard

Table 31. Multiplier Result Figure 41, Figure 42) and Table 32. Table 32. Step Behaviour Summary grams (Figure 40, Figure 41, and Figure 42).

00 On even

01 On odd

10 Continuous

11 All active

1 Alternate

10 Alternate odd/even

0 On even

1 On odd

Table 33. Input Channel Selection Table 34. OO[5:0] Bit Meaning Bit 7 = ZVD : Z vs D edge polarity. Bits 5:0 = OE[5:0]: Output Parity Mode. Bits 7:6 = OT[1:0]: Off Time selection. sorless mode as shown in the following table. Table 35. Off-Time bit Meaning Bits 5:0 = OP[5:0]: Output channel polarity. 1: Output channel is Active High. Table 36. Output Channel State Control

0 Inactive

1 Active

MOTOR CONTROLLER (Cont’d) Note: The CPB, HDM, SDM, OS2 bits in the MCRB and the bits OE[5:0] are marked with *. It means that these bits are taken into account at the following commutation event (in normal mode) or when a value is written in the MPHST register when in direct access mode. For more details, re- fer to the description of the DAC bit in the MCRA register. The use of a Preload register allows all the registers to be updated at the same time. Warning: Access to Preload registers Special care has to be taken with Preload regis- ters, especially when using the ST7 BSET and BRES instructions on MTC registers. For instance, while writing to the MPHST register, you will write the value in the preload register. However, while reading at the same address, you will get the current value in the register and not the value of the preload register. All preload registers are loaded in the real regis- ters at the same time. In normal mode this is done automatically when a C event occurs, however in direct access mode (DAC bit=1) the preload regis- ters are loaded as soon as a value is written in the MPHST register.

Figure 43. Detailed view of the MTC

Table 37. MTC Register Map and Reset Values

0 OO0

8.2 WATCHDOG TIMER (WDG)

8.2.1 Introduction

8.2.2 Main Features

Figure 44. Watchdog Block Diagram

8.2.3 Functional Description

programmed by the user in 64 increments. Table 38. Watchdog Timing (f set (the WDGA bit is set and the T6 bit is cleared).

8.2.4 Low Power Modes

8.2.5 Interrupts

8.2.6 Register Description

watchdog can generate a reset.

Table 39. Watchdog Timer Register Map and Reset Values

8.3 16-BIT TIMER

8.3.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input sig- nals ( input capture) or generating up to two output waveforms (output compare and PWM ). Pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequen- cies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).

8.3.2 Main Features

■ Programmable prescaler: fCPU divided by 2, 4 or 8. ■ Overflow status flag and maskable interrupt ■ External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge ■ Output compare functions with: – 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt ■ Input capture functions with: – 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt ■ Pulse Width Modulation mode (PWM) ■ One Pulse mode ■ 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 45. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be ‘1’.

8.3.3 Functional Description

8.3.3.1 Counter

The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): – Counter High Register (CHR) is the most sig- nificant byte (MS Byte). – Counter Low Register (CLR) is the least sig- nificant byte (LS Byte). Alternate Counter Register (ACR) – Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). – Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit tim- er). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 40 Clock Control Bits. The value in the counter register re- peats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be f CPU /2, fCPU /4, fCPU /8 or an external frequency.

Figure 45. Timer Block Diagram

16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they re- turn the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, out- put compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: – The TOF bit of the SR register is set. – A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

8.3.3.2 External Clock

The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the exter- nal clock pin EXTCLK that will trigger the free run- ning counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the CPU clock frequency. is buffered Read At t0 Read Returns the buffered LS Byte value at t0At t0 +Δ t Other instructions Beginning of the sequence Sequence completed LS Byte LS Byte MS Byte

16-BIT TIMER (Cont’d)

8.3.3.3 Input Capture

In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter after a transition is detected by the ICAP i pin (see figure 5). The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU /CC[1:0]). Procedure: To use the input capture function, select the fol- lowing in the CR2 register: – Select the timer clock (CC[1:0]) (see Table 40 Clock Control Bits). – Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: – Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). When an input capture occurs: – The ICF i bit is set. – The ICiR register contains the value of the free running counter on the active transition on the ICAP i pin (see Figure 50). – A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Other- wise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICF i bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input cap- ture function. Moreover if one of the ICAP i pin is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the ICIE bit is set. This can be avoided if the input capture func- tion i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh). MS Byte LS Byte ICiR IC iHR IC iLR

16-BIT TIMER (Cont’d)

8.3.3.4 Output Compare

In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Com- pare register and the free running counter, the out- put compare function: – Assigns pins with a programmable value if the OC iE bit is set – Sets a flag in the status register – Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC iR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/ CC[1:0]). Procedure: To use the output compare function, select the fol- lowing in the CR2 register: – Set the OCiE bit if an output is needed then the OCMP i pin is dedicated to the output compare i signal. – Select the timer clock (CC[1:0]) (see Table 40 Clock Control Bits). And select the following in the CR1 register: – Select the OLVLi bit to applied to the OCMPi pins after the match occurs. – Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: – OCF i bit is set. – The OCMP i pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). – A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OC iR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: Δt = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 de- pending on CC[1:0] bits, see Table 40 Clock Control Bits) If the timer clock is an external clock, the formula is: Where: Δt = Output compare period (in seconds) fEXT = External timer clock frequency (in hertz) Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to pre- vent the OCFi bit from being set between the time it is read and the write to the OCiR register: – Write to the OCiHR register (further compares are inhibited). – Read the SR register (first step of the clearance of the OCFi bit, which may be already set). – Write to the OCiLR register (enables the output compare function and clears the OCFi bit). MS Byte LS Byte OC iRO C iHR OC iLR Δ OCiR = Δt * fCPU PRESC Δ OCiR = Δ t * fEXT

1. After a processor write cycle to the OCiHR reg-

until the OCiLR register is also written.

1. If the OCiE bit is not set, the OCMPi pin is a

could be generated if the OCIE bit is set.

1. When the timer clock is f

behaviour is the same in OPM or PWM mode. ter value plus 1 (see Figure 53).

1. The output compare functions can be used both
2. The value in the 16-bit OC

waveform or establish a new elapsed timeout. Figure 51. Output Compare Block Diagram

16 BIT FREE RUNNING

16-BIT TIMER (Cont’d)

8.3.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded- icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 40 Clock Control Bits). Then, on a valid event on the ICAP1 pin, the coun- ter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the Input Capture interrupt request (i.e. clearing the ICF i bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the fol- lowing formula: Where: t = Pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depend- ing on the CC[1:0] bits, see Table 40 Clock Control Bits) If the timer clock is an external clock the formula is: Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 54). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedi- cated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedi- cated to One Pulse mode. event occurs Counter = OC1R OCMP1 = OLVL1 When When on ICAP1 One Pulse mode cycle OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set OC iR Value = t * fCPU PRESC - 5 OCiR = t * fEXT -5

16-BIT TIMER (Cont’d)

8.3.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the com- plete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corre- sponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the oppo- site column. 3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after a successful comparison with OC1R register. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat- ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 40 Clock Control Bits). If OLVL1=1 and OLVL2=0, the length of the posi- tive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OC iR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: t = Signal or pulse period (in seconds) f CPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depend- ing on CC[1:0] bits, see Table 40 Clock Control Bits) If the timer clock is an external clock the formula is: Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 55) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OC iLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the coun- ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is discon- nected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. Counter OCMP1 = OLVL2 Counter = OC2R OCMP1 = OLVL1 When When = OC1R Pulse Width Modulation cycle Counter is reset to FFFCh ICF1 bit is set OC iR Value = t * fCPU PRESC - 5 OCiR = t * fEXT -5

16-BIT TIMER (Cont’d)

8.3.4 Low Power Modes

8.3.5 Interrupts

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap- ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

8.3.6 Summary of Timer modes

1) See note 4 in Section 8.3.3.5 One Pulse Mode 2) See note 5 in Section 8.3.3.5 One Pulse Mode 3) See note 4 in Section 8.3.3.6 Pulse Width Modulation Mode Mode Description WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. HALT 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAP i pin, the input capture detection circuitry is armed. Consequent- ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE Yes No Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 OCIE Yes No Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes No MODES AVAILABLE RESOURCES Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) Yes Yes Yes Yes One Pulse mode No Not Recommended 1) No Partially 2) PWM Mode No Not Recommended 3) No No

16-BIT TIMER (Cont’d)

8.3.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no suc- cessful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg- ister and OCxE is set in the CR2 register. This val- ue is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin when- ever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Output Compare 1 Pin Enable. free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Output Compare 2 Pin Enable. free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. 0: One Pulse mode is not active. contents of the OC1R register. Table 40. Clock Control Bits on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

16-BIT TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter has rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2-0 = Reserved, forced by hardware to 0. INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. ICF1 OCF1 TOF ICF2 OCF2 0 0 0 70 MSB LSB MSB LSB MSB LSB MSB LSB

16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit. ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register. INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event). INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the In- put Capture 2 event). MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

Table 41. 16-Bit Timer Register Map and Reset Values

8.4 SERIAL PERIPHERAL INTERFACE (SPI)

8.4.1 Introduction

which devices may be either masters or slaves.

8.4.2 Main Features

■ Maximum slave mode frequency = fCPU /4. ■ Master mode fault protection capability.

8.4.3 General description

must be programmed with the same timing mode. Figure 56. Serial Peripheral Interface Master/Slave

Figure 57. Serial Peripheral Interface Block Diagram

SERIAL PERIPHERAL INTERFACE (Cont’d)

8.4.4 Functional Description

Figure 56 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer to the CR, SR and DR registers in Section 8.4.7for the bit definitions.

8.4.4.1 Master Configuration

In a master configuration, the serial clock is gener- ated on the SCK pin. Procedure – Select the SPR0 & SPR1 bits to define the se- rial clock baud rate (see CR register). – Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 59). –T h e S S pin must be connected to a high level signal during the complete byte transmit se- quence. – The MSTR and SPE bits must be set (they re- main set only if the SS pin is connected to a high level signal). In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is writ- ten the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A read to the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.

SERIAL PERIPHERAL INTERFACE (Cont’d)

8.4.4.2 Slave Configuration

In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – For correct data transfer, the slave device must be in the same timing mode as the mas- ter device (CPOL and CPHA bits). See Figure 59. –T h e S S pin must be connected to a low level signal during the complete byte transmit se- quence. – Clear the MSTR bit and set the SPE bit to as- sign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2.A read to the DR register. Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 8.4.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 8.4.4.4).

8.4.4.3 Data Transfer Format

ed do not interfere with the SPI transfer. by software, using the CPOL and CPHA bits. master and the slave device. be driven by the master device. clock edge before the capture clock edge. the occurrence of the second clock transition. currence of the first clock transition. each byte transmitted (see Figure 58). Figure 58. CPHA / SS Timing Diagram

Figure 59. Data Clock Timing Diagram Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

8.4.4.4 Write Collision Error

the software write will be unsuccessful. nal MISO pin of the slave device. (SCK) is in the process of transfer. is set (the WCOL bit is a status flag only). Figure 60. Clearing the WCOL bit (Write Collision Flag) Software Sequence

SERIAL PERIPHERAL INTERFACE (Cont’d)

8.4.4.5 Master Mode Fault

Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. – The SPE bit is reset. This blocks all output from the device and disables the SPI periph- eral. – The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing se- quence of the MODF bit. The SPE and MSTR bits may be restored to their original state during or af- ter this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine.

8.4.4.6 Overrun Condition

An overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripher- al.

8.4.4.7 Single Master and Multimaster Configurations

that time, thus disabling the slave devices. through the serial peripheral interface system. Figure 61. Single Master Configuration

SERIAL PERIPHERAL INTERFACE (Cont’d)

8.4.5 Low Power Modes

8.4.6 Interrupts

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Transfer Event SPIF SPIE Yes No Master Mode Fault Event MODF Yes No

8.4.7 Register Description

Serial peripheral interrupt enable. This bit is set and cleared by software. Bit 6 = SPE Serial peripheral output enable. (see Section 8.4.4.5 Master Mode Fault). eral is not initially connected to the external pins. Bit 5 = SPR2 Divider Enable. set the baud rate. Refer to Table 42. (see Section 8.4.4.5 Master Mode Fault). 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. This bit is set and cleared by software. Bit 1:0 = SPR[1 :0] Serial peripheral rate. These 2 bits have no effect in slave mode. Table 42. Serial Peripheral Baud Rate

SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a soft- ware sequence (an access to the SR register fol- lowed by a read or write to the DR register). 0: Data transfer is in progress or has been ap- proved by a clearing sequence. 1: Data transfer between the device and an exter- nal device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 60). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 8.4.4.5 Master Mode Fault). An SPI interrupt can be gen- erated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused. DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/re- ception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A read to the the DR register returns the value lo- cated in the buffer and not the contents of the shift register (See Figure 57 ). S P I F W C O L - M O D F ---- D7 D6 D5 D4 D3 D2 D1 D0

Table 43. SPI Register Map and Reset Values

8.5.1 Introduction

levels from up to 8 different sources. through a Control/Status Register.

8.5.2 Main Features

The block diagram is shown in Figure 62. Figure 62. ADC Block Diagram

8.5.3 Functional Description

loaded or badly decoupled power supply lines. Figure 63. Recommended Ext. Connections never increases if the analog input does not. scale) without overflow indication. cluding a sampling time of 31.5 CPU clock cycles. Electrical Characteristics Section. tion for the bit definitions. – The COCO bit is set by hardware. – No interrupt is generated. – The result is in the DR register.

8.5.4 Low Power Modes

8.5.5 Interrupts

8.5.6 Register Description

0: Conversion is not complete. 1: Conversion can be read from the DR register. Bit 6 = Reserved. Must always be cleared. This bit is set and cleared by software. 0: A/D converter is switched off. 1: A/D converter is switched on. the ADC to stabilize when the ADON bit is set. Bit 4 = Reserved. Forced by hardware to 0. Bit 3 = Reserved. Must always be cleared. select the analog input to convert. Table 44. Channel Selection the channel selection vary according to the device. REFER TO THE DEVICE PINOUT). Reading this register resets the COCO flag. Table 45. ADC Register Map and Reset Values

9 INSTRUCTION SET

9.1 ST7 ADDRESSING MODES

Table 46. ST7 Addressing Mode Overview

ST7 ADDRESSING MODES (Cont’d)

9.1.1 Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation.

9.1.2 Immediate

Immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value.

9.1.3 Direct

In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub- modes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF address- ing space. Direct (long) The address is a word, thus allowing 64 Kbyte ad- dressing space, but requires 2 bytes after the op- code.

9.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte ad- dressing space and requires 2 bytes after the op- code.

9.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (point- er). The pointer address follows the opcode. The indi- rect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations

9.1.6 Indirect Indexed (Short, Long)

er address follows the opcode. and requires 1 byte after the opcode. and requires 1 byte after the opcode. Table 47. Instructions Supporting Direct,

9.1.7 Relative Mode (Direct, Indirect)

register value by adding an 8-bit signed offset to it. The offset follows the opcode.

9.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available op- codes for an 8-bit CPU (256 opcodes), three differ- ent prebyte opcodes are defined. These prebytes modify the meaning of the instruction they pre- cede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruc- tion using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF

INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >

INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2's compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z

10 ELECTRICAL CHARACTERISTICS

10.1 ABSOLUTE MAXIMUM RATINGS

This product contains devices for protecting the in- puts against damage due to high static voltages, however it is advisable to take normal precautions to avoid applying any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that V I and VO be higher than VSS and lower than VDD . Reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (VDD or VSS ). Power Considerations. The average chip-junc- tion temperature, TJ, in Celsius can be obtained from: TJ =T A + P D x R t h J A Where: T A = Ambient Temperature. RthJA =Package thermal resistance (junction-to ambient). PD = P INT + PPORT . PINT =I DD x VDD (chip internal power). PPORT =Port power dissipation determined by the user) Note: Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating condi- tions for extended periods may affect device reliability. General Warning: Direct connection to VDD or VSS of the RESET and I/O pins could damage the device in case of unintentional internal reset generation or program counter corruption (due to unwanted change of the I/O configuration). To guarantee safe conditions, this connection has to be done through a 10KΩ typical pull-up or pull-down resistor. Thermal Characteristics Symbol Ratings Value Unit VDD - VSS Supply voltage 6.5 V VIN Input voltage on true open drain pin V SS - 0.3 to 6.5 V Input voltage on any other pin V SS - 0.3 to VDD + 0.3 VOUT Output voltage V SS - 0.3 to VDD + 0.3 V ESD ESD susceptibility 2000 V IVDD_i Total current into VDD_i (source) 80 mA IVSS_i Total current out of VSS_i (sink) 80 Symbol Ratings Value Unit R thJA SDIP32 60 °C/W TJmax Max. junction temperature 150 °C TSTG Storage temperature range -65 to +150 °C PD Power dissipation 500 mW

10.2 RECOMMENDED OPERATING CONDITIONS

10.3 DC ELECTRICAL CHARACTERISTICS

Recommended operating conditions with TA=-40 to +125oC, VDD -VSS =5V unless otherwise specified.

10.4 GENERAL TIMING CHARACTERISTICS

Notes: 1) Unless otherwise specified, typical data is based on TA=25°C and VDD -VSS =5V. This data is provided only as design guidelines and is not tested. 2) Fixed frequencies required to obtain 4MHz for the motor control peripheral. 3) CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS , all peripherals switched off; clock input (OSC2) driven by external square wave. 4) All I/O pins in input mode with a static value at VDD or VSS , all peripherals switched off; clock input (OSC2) driven by external square wave. 5) All I/O pins in input mode with a static value at VDD or VSS . 6) Data based on characterization results, not tested in production. 7) ΔtINST is the number of tCPU to finish the current instruction execution. GENERAL Symbol Parameter Conditions Min Typ 1) Max Unit VDD Supply voltage 4.0 5.5 V fOSC Resonator oscillator frequency 8 or 16 2) MHzExternal clock source TA Ambient temperature range

1 Suffix Version 0 70

°C6 Suffix Version -40 85

3 Suffix Version -40 125

Symbol Parameter Conditions Min Typ 1) Max Unit IDD Supply current in RUN mode 3) fOSC = 8 MHz, fCPU = 4 MHz fOSC = 16 MHz, fCPU = 8 MHz mA Supply current in SLOW mode 3) fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz 0.7 1.1 1.7 Supply current in WAIT mode 4) fOSC = 8MHz, fCPU = 4 MHz fOSC = 16MHz, fCPU = 8 MHz 3.3 Supply current in SLOW WAIT mode 4) fOSC = 8 MHz, fCPU = 250 kHz fOSC = 16 MHz, fCPU = 500 kHz 0.65 0.8 1.4 Supply current in HALT mode 5) ILOAD = 0mA (current on IOs) 200 µA VRM Data retention mode 6) HALT mode 2 V Symbol Parameter Conditions Min Typ Max Unit tINST Instruction time 2 12 t CPU tIRT Interrupt reaction time t IRT = ΔtINST + 10 7) 10 22 t CPU

10.5 I/O PORT CHARACTERISTICS

Recommended operating conditions with TA =-40 to +125oC and 4.5V<VDD -VSS <5.5V unless otherwise specified. Notes: 1) Unless otherwise specified, typical data is based on TA=25°C and VDD -VSS =5V. This data is provided only as design guidelines and is not tested. 2) Data based on design simulations and/or technology characteristics, not tested in production. 3) Hysteresis voltage between Schmitt trigger switching levels. Based on characterisation results, not tested. 4) Data based on characterization results, not tested in production. 5) Positive injection (IINJ+) The IINJ+ is performed through protection diodes insulated from the substrate of the die. The true open-drain pins do not accept positive injection. In this case the maximum voltage rating must be respected. 6) ADC accuracy reduced by negative injection (IINJ- ) The IINJ- is performed through protection diodes NOT INSULATED from the substrate of the die. The drawback is a small leakage (a few µA) induced inside the die when a negative injection is performed. This leakage is tolerated by the digital structure, but it acts on the analog line depending on the impedance versus a leakage current of a few µA (if the MCU has an AD converter). The effect depends on the pin which is submitted to the injection. Of course, external digital signals applied to the component must have a maximum impedance close to 50KΩ . Location of the negative current injection: - Pins with analog input capability are the most sensitive. I INJ- maximum is 0.8 mA (assuming that the impedance of the analog voltage is lower than 25KΩ ) - Pure digital pins can tolerate 1.6mA. In addition, the best choice is to inject the current as far as possible from the analog input pins. 7) When several inputs are submitted to a current injection, the maximum IINJ is the sum of the positive (or negative) cur- rents (instantaneous values). These results are based on characterisation with IINJ maximum current injection on four I/ O port pins of the device. 8) To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source. I/O PORT PINS Symbol Parameter Conditions Min Typ 1) Max Unit VIL Input low level voltage 2) 0.3xVDD VVIH Input high level voltage 2) 0.7xVDD VHYS Schmitt trigger voltage hysteresis 3) 400 mV VOL Output low level voltage for standard I/O port pins I=-5mA 1.3 V I=-2mA 0.5 Output low level voltage for high sink I/O port pins I=-20mA 1.3 I=-8mA 0.5 VOH Output high level voltage I=-5mA V DD -2.0 I=-2mA V DD -0.8 R PU Pull-up equivalent resistor VIN > VIH VIN < VIL 120 240 kΩ IL Input leakage current V SS <VPIN<VDD 1 µAISV Static current consumption 2) Floating input mode 200 IPINJ Single pin injected current Positive 5): VEXT >VDD 5 mANegative 6): VEXT <V SS -5 IINJ Total injected current 7) (sum of all I/O and control pins) Positive: VEXT >VDD 20 Negative: VEXT <V SS 20 tOHL Output high to low level fall time C l=50pF 14.8 4) 25 45.6 4) nstOLH Output low to high rise time 14.4 4) 25 45.9 4) tITEXT External interrupt pulse time 8) 1t CPU

10.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS

10.6.1 Supply Manager

Recommended operating conditions with TA=-40 to +125oC and voltages referred to VSS .

10.6.2 RESET Sequence Manager

10.6.3 Clock System

Recommended operating conditions with TA=-40 to +125oC and voltages referred to VSS . Notes: 1) LVD typical data is based on TA=25°C. This data is provided only as design guidelines and are not tested. 2) The VLVDhyst hysteresis is constant. 3) The VDD rise time rate condition is needed to ensure a correct device power-on reset. Not tested in production. 4) Data based on characterization results, not tested in production. 5) Unless otherwise specified, typical data is based on TA=25°C and VDD -VSS =5V. This data is provided only as design guidelines and is not tested. 6) This data is based on typical a RSmax value. The oscillator selection can be optimized in terms of supply current with a high quality resonator. 7) R Smax is the equivalent serial resistor of the crystal or ceramic resonator. 8) Data based on design simulations and/or technology characteristics, not tested in production. LOW VOLTAGE DETECTOR (LVD) Symbol Parameter Conditions Min Typ 1) Max Unit VLVDhyst VLVD Hysteresis 2) VLVDr - VLVDf 250 mV VtPOR VDD rise time rate 3) 0.2 50 V/ms IDD LVD Supply Current HALT mode 100 200 4) µA RESET SEQUENCE MANAGER (RSM) Symbol Parameter Conditions Min Typ 5) Max Unit R ON Reset weak pull-up resistance VIN > VIH VIN ≥VSS 180 kΩ tDELAYmin Reset delay for external and watchdog reset sources 1/fSFOSC µs tPULSE External RESET pin Pulse time 20 µs EXTERNAL CLOCK SOURCE Symbol Parameter Conditions Min Typ Max Unit VOSC2h OSC2 input pin high level voltage Square wave signal with ~50% Duty Cycle 0.7xVDD VDD VVOSC2l OSC2 input pin low level voltage VSS 0.3xVDD CRYSTAL AND CERAMIC RESONATOR OSCILLATORS Symbol Parameter Conditions Min Typ 5) Max Unit fOSC Oscillator Frequency 6) 81 6 M H z C Li Load Capacitor R Smax =100 Ω 7) 15 8) 18 21 6) pF IDD Supply Current 700 1100 4) µA tSTART Oscillator start-up time Depends on resonator quality. A typical value is 10ms

10.7 MEMORY AND PERIPHERAL CHARACTERISTICS

Recommended operating conditions with TA =-40 to +125oC and VDD -VSS =5V unless otherwise specified. sign guidelines and are not tested. 2) The VMTChyst hysteresis is constant. Figure 64. Motor Control Comparator Characteristics

Figure 65. SPI Master Timing Diagram CPHA=0, CPOL=0 2) 1) Data based on characterization results, not tested in production.

MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) Notes: 1) Unless otherwise specified, typical data is based on TA=25°C and VDD -VSS =5V. This data is provided only for design guidelines and is not tested. 2) Tested in production at TA=25°C, characterized over all temperature range. 3) ADC Accuracy vs. Negative Injection Current: For IINJ-=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB by 10KΩ increase of the external analog source impedance. These measurement results and recommendations have been done under worst conditions for injection: - negative injection - injection to an Input with analog capability, adjacent to the enabled Analog Input - at 5V VDD supply, and worst case temperature. 4) Data based on characterization results, not tested in production. ADC Analog to Digital Converter (8-bit) Symbol Parameter Conditions Min Typ 1) Max Unit |TUE| Total unadjusted error 3) TA=25°C,VDD =V DDA =5V,2) fCPU =8MHz LSB OE Offset error 3) -1 1 GE Gain Error 3) -2 2 |DLE| Differential linearity error 3) 1 |ILE| Integral linearity error 3) 2 VAIN Conversion range voltage V SSA VDDA V IADC A/D conversion supply current fADC =fCPU =4MHz VDD =V DDA =5V 1m A tSTAB Stabilization time after ADC enable 30 µs tLOAD Sample capacitor loading time 8 µs 1/fADC tCONV Hold conversion time 8 µs 1/fADC R AIN External input resistor 20 4) kΩ R ADC Internal input resistor 18 k Ω C SAMPLE Sample capacitor 22 pF

MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) Px.x/AINx R AIN VAIN C pin 5pF VDD VT = 0.6V leakageVT = 0.6V C pin VT leakage C hold SS Sampling Switch SS R SS at the pin due to various junctions C hold 6 pF capacitance = input capacitance = threshold voltage = sampling switch = sample/hold ±1µA V SS = leakage current 2ΚΩ OE GE

1 LSB (ideal)

V DDA V SSA– Vin (LSBideal) (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line TUE =Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. OE =Offset Error: deviation between the first actual transition and the first ideal one. GE =Gain Error: deviation between the last ideal transition and the last actual one. DLE =Differential Linearity Error: maximum devia- tion between actual steps and the ideal one. ILE=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Digital Result ADCDR 255 254 253 1234567 253 254 255 256 (1) (2) TUE DLE ILE (3) VDDAVSSA

11 GENERAL INFORMATION

11.1 PACKAGE MECHANICAL DATA

Figure 73. 32-Pin Plastic Dual In-Line Package, Shrink 400-mil Width Figure 74. 34-Pin Plastic Small Outline Package, Shrink 300-mil Width

11.2 ORDERING INFORMATION

Figure 75. ROM Factory Coded Device Types Figure 76. OTP User Programmable Device Types

MICROCONTROLLER OPTION LIST STMicroelectronics references Device: [ ] ST72141K2 Conditioning: [ ] Tube [ ] Tape & Reel (not available for SDIP packages) Temperature Range: [ ] -40 to 85°C [ ] -40 to 125°C Readout Protection: [ ] Enabled [ ] Disabled Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: DIP32 10 SO34 13 Comments :

12 SUMMARY OF CHANGES

Description of the changes between the current release of the specification and the previous one. Rev. Main Changes Date 1.8 Added VtPOR in section 10.6.1 on page 121 Modified VMTChyst and Voffset in section 10.7 on page 122 Modified Option list in Section 11.2 Oct 01

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