ST7162N

ST7162 STMICROELECTRONICS | Alldatasheet

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UNIVERSAL PROGRAMMABLE DUAL PLL PRODUCT PREVIEW TWO INDEPENDENT PLL WITH 16 BITS PROGRAMMABLE DIVIDERS FROM 13 TO

65535 FOR TRANSMIT AND RECEIVE

ON CHIP REFERENCE OSCILLATOR COM- MON FOR THE TWO LOOPS UP TO 16MHz WITH EXTERNAL CRYSTAL TWO INDEPENDENT PROGRAMMABLE REFERENCE COUNTERS: - 12 bits programmable counter from 13 to 4095 followed by selectable dividers by 1, 4a n d 2 5 - 14 bits auxiliary programmable counter from 13 to 16383 A MCU CLOCK DERIVED FROM REFER- ENCE OSCILLATOR WITH A SELECTABLE DIVISION FACTOR OF 3 OR 4 TWO INDEPENDENT PFD (PHASE FRE- QUENCY DISCRIMINATOR) WITH 3 STATE OUTPUTS LOCK DETECT SIGNAL OUTPUT FOR THE TRANSMIT LOOP 3 & 4 WIRES SELECTABLE MCU SERIAL IN- TERFACE, FOR SIMULTANEOUS PRO- GRAMMING OF 2 COUNTERS STAND-BY MODE MAIN CHARACTERISTICS High input sensitivity: 200mVpkpk @ 60MHz Low consumption: 3.5mA @ 3V for the two loops Power supply voltage: 3V to 5V Operating temperature range: –25°Ct o+ 7 0°C

DESCRIPTION

The ST7162 is a dual frequency synthesizer in High Speed CMOS technology for radio applica- tions with a frequency up to 60MHz. The low power consumption and high flexibility make it well suitable for cordless CT0 applications in vari- ous countries. This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. July 1993 PIN CONNECTION (Top view) DIP16 ORDERING NUMBER: ST7162N SO16 ORDERING NUMBER: ST7162D

Symbol Parameter Value Unit VDD -V SS Supply Voltage – 0.5 to +6 V VIN Input Voltage V SS –0.5 to VDD +0.5 V VOUT Output Voltage V SS –0.5 to VDD +0.5 V IIN,IOUT DC Current per pin – 10 to 10 mA IDD ,ISS DC Current for pin VDD or VSS –3 0t o3 0 m A Tstg Storage Temperature – 55 to +125 °C BLOCK DIAGRAM ST7162

N. Name Function

1 CLOCK MCU Interface

2 AUX DATA IN MCU Interface

3 DATA IN MCU Interface

4 ENABLE MCU Interface

5 MCU CLOCK Scaled down reference frequency for clocking the MCU

6V SS Negative Power Supply

7 OSC OUT Oscillator Output

8 OSC IN Oscillator Input

9 FIN R

X Input to the 16 bits Receive Counter

10 PD R X Phase detector output of the Receive loop

11 Out R X Power saving output bit for the RX loop and FIN RX divided by N1 for testing the RX input

sensitivity.

12 V DD Positive power supply

13 OUT T X Power saving output bit for the TX loop and FIN TX divided by N2 for testing the TX input

sensitivity. 14 FIN T X Input to the 16 bits Transmit counter.

15 PD T X Phase detector output of the transmit loop

16 LD Lock detect output of the transmit loop. ELECTRICAL CHARACTERISTICS (Tamb = 25°C, voltage reference = VSS ) Symbol Parameter Test Condition V DD Min. Typ. Max. Unit SUPPLY VDD Supply Voltage 3 5.5 V IDD up Supply Current 200mVpkpk sinus at input; FIN RX = 36MHz, FIN TX =49MHz; loop in lock condition; f osc = 10.24MHz; no output load 3.7 7.7 mA mA IDDRX Supply Current 200mVpkpk sinus at input; FIN RX = 36MHz; TX Loop in Power down; fosc = 10.24MHz; no output load 2.5 5.3 mA mA IDD down Supply Current Stand-by mode for all counters; OSCIN pin Grounded; MCU interface disabled 150 300 µA µA TX and RX INPUTS C IN Input Capacitance 8p F IIN up Input Current 0 < V IN <V DD 3V –6 0 – 100 100 µA µA Fmax Input Frequency Input = sinus 200mVpkpk AC coupled 3-5V 60 MHz OSCILLATOR C IN Input Capacitance 8p F C OUT Output Capacitance 8 pF IIN up Input Current 0 < V IN <V DD DC measured 3V –6 0 – 100 100 µA µA Fmax Input Frequency 3-5V 16 MHz ST7162

ELECTRICAL CHARACTERISTICS (Tamb = 25°C, voltage reference = VSS ) Symbol Parameter Test Condition V DD Min. Typ. Max. Unit PHASE FREQUENCY DISCRIMINATOR C OUT Output Capacitance 8 pF IOUT HI Output Current Source VOUT = 2.7V VOUT = 4.5V – 200 – 500 µA µA IOUT LO Output Current Sink VOUT = 0.3V VOUT = 0.5V 200 500 µA µA ILEAK Leakage Current Three state output VPDT X,V P D RX = 0 or 5V 5V – 50 50 nA MCU INTERFACE INPUTS C IN Input Capacitance 8p F IIN Input Current DC measured V IN =V DD or VSS 3-5V – 10 10 µA VIH Input Voltage High level ”1” 3V 2.3 3.8 V V VIL Input Voltage Low level ”0” 3V 0.7 1.2 V V Fmax Input Frequency Maximum frequency at clock input 3-5V 500 KHz TW Pulse width Clock and Enable inputs 3V ns ns TSU Set-up Time Data to clock Enable to clock 3-5V 3-5V 100 200 ns ns THOLD Hold Time Clock to data 3V ns ns TREC Recovery Time Enable to Clock 3V ns ns DIGITAL OUTPUTS: OUTT X, OUTRX, MCUCLOCK ,L D C LOAD Output Load Capacitance 25 pF VOUT IH Output Voltage I OUT = 0, High level ”1” 3V 2.95 4.95 V V VOUT LO Output Voltage I OUT = 0, Low level ”0” 3V 0.05 0.05 V V IOUTHI Output Current Source VOUT = 2.7V VOUT = 4.5V – 200 – 500 µA µA IOUTLO Output Current Sink VOUT = 0.3V VOUT = 0.5V 200 500 µA µA THI Output rise Time C LOAD = 25pF 3V 200 100 ns ns TLO Output Fall Time C LOAD = 25pF 3V 200 100 ns ns ST7162

Figure 1:Control Unit Block Diagram Register Adress Number of Data Bits Function A2 A1 A0 R0 0 0 0 13 CIRCUIT CONTROL R1 0 0 1 16 BINARY VALUE OF N1 = RX RATIO R2 0 1 0 16 BINARY VALUE OF N2 = TX RATIO R3 0 1 1 12 BINARY VALUE OF N3 = REF RATIO R4 1 0 0 14 BINARY VALUE OF N4 = AUX REF RATIO Sumary of Internal Registers ST7162

Description of Control Register Bit Name Function D12 TEST 1 Test Mode: See Table 1.D11 TEST 2 D10 TEST 3 D9 AUXILIARY DATA SELECT Set to 0 to select 3 wires serial data bus mode at the next pattern Set to 1 to select 4 wires serial data bus mode at the next pattern D8 REFOUT/3 Set to 0, MCUCLOCK frequency = OSC.OUT frequency / 4 Set to 1, MCUCLOCK frequency = OSC.OUT frequency / 3 D7 TXCE TX Counter Enable bit: if set to 0, TX amplifier, counter and PFD will be in power down mode and OUTTX pin will be set to 1. D6 RXCE RX Counter Enable bit: if set to 0, RX amplifier, counter and PFD will be in power down mode and OUTRX pin will be set to 1. D5 RCE Reference Counter Enable bit: if set to 0, ref counter will be in power down mode. D4 ARCE Auxiliary Reference Counter Enable bit: if set to 0, AUX Ref counter will be in power down mode D3 MUX SELECT 1 Used to connect internally PFD inputs REFTX and REFRX to the chosen Ref frequency output: see Table 2. D2 MUX SELECT 2 D1 MUX SELECT 3 D0 MUX SELECT 4 Table 1. TEST1 TEST2 TEST3 Status of output pin OUTTX Status of output pin OUTRX Status of TX and RX PFD 0 0 0 CONTROL BIT TXCE CONTROL BIT RXCE NORMAL OPERATION 0 0 1 INTERNAL POINT REFTX INTERNAL POINT REFRX TEST MODE NORMAL IUP 0 1 0 INTERNAL POINT FINTX/N2 INTERNAL POINT FINRX/N1 TEST MODE NORMAL IDOWN 0 1 1 INTERNAL POINT FINTX/N2 INTERNAL POINT FINRX/N1 TEST MODE I LEAKAGE 1 0 0 CONTROL BIT TXCE CONTROL BIT RXCE OPERATION WITH INCREASED IUP AND IDOWN 1 0 1 INTERNAL POINT REFTX INTERNAL POINT REFRX TEST MODE INCREASED IUP 1 1 0 INTERNAL POINT FINTX/N2 INTERNAL POINT FINRX/N1 TEST MODE INCREASED IDOWN 1 1 1 INTERNAL POINT FINTX/N2 INTERNAL POINT FINRX/N1 TEST MODE I LEAKAGE ST7162

Figure 2:Reference Frequency Diagram. Table 2. MUX SELECT MUX SELECT MUX SELECT MUX SELECT INPUT OF TX PFD REFTX CONNECTED TO INTERNAL POINT (see Note 1) INPUT OF RX PFD REFRX CONNECTED TO INTERNAL POINT (see Note 2) 0 0 0 0 FREF FREF 0 0 0 1 FREF FREF/4 0 0 1 0 FREF FREF/25 0 0 1 1 FREF AUXFREF 0 1 0 0 FREF/4 FREF 0 1 0 1 FREF/4 FREF/4 0 1 1 0 FREF/4 FREF/25 0 1 1 1 FREF/4 AUXFREF 1 0 0 0 FREF/25 FREF 1 0 0 1 FREF/25 FREF/4 1 0 1 0 FREF/25 FREF/25 1 0 1 1 FREF/25 AUXFREF 1 1 0 0 AUXFREF FREF 1 1 0 1 AUXFREF FREF/4 1 1 1 0 AUXFREF FREF/25 1 1 1 1 AUXFREF AUXFREF Note (1): If the 12 bits REF. counter is disabled (RCE control bit = 0) then the inputs of RX and TX PFD (REF TX and REF RX) are connected to internal point AUX REF. Note (2): If the 14 bits auxiliary reference counter is disabled (ARCE control bit = 0) then the internal point AUXFREF is replaced by FREF/ 25. ST7162

Figure 3:3 Wires Serial Data Transmission Timing ADDRESS A2 A1 A0 000 DATA D12 TEST 1 D11 TEST 2 D10 TEST 3 D9 AUX. DATA SELECT D8 REF OUT/3 D7 TX COUNTER ENABLE D6 RX COUNTER ENABLE D5 REF. COUNTER ENABLE D4 AUX. REF. COUNTER ENABLE D3 MUX SELECT 1 D2 MUX SELECT 2 D1 MUX SELECT 3 D0 MUX SELECT 4 PROGRAMMING THE REGISTER (Figs 3 to 8) When a Low level is present on the ENABLE in- put, information on the DATA and AUX DATA in- puts are used to program the internal registers. Data are shifted at the rising edge of the clock in- put. First the 3 address bits of a register are sent, followed by 12 to 16 data bits, depending on the lenght of the register. The address is latched at the 3rd clock impulse following a falling edge at ENABLE input. This configuration allows to send various lenght patterns. Moreover, fixed patterns of 24 or 32 bits can be sent if dummy bits are in- serted between the address bits and the first data bit. After the last data bit, a rising edge of the EN- ABLE input latches the information. When the V DD supply is switched on, an internal circuit pro- vides a reset of the control register bits. When the serial bus is not used, a Low level at clock input and a HIGH level at ENABLE inputs are applied. PROGRAMMING THE 3/4 WIRES MODE When the Auxiliary Data select bit of the control register is set to 1, the serial bus is switched in 4 wires mode at the next pattern. Then one or other of the 5 registers may be serially loaded by one or other of the DATA or AUX DATA inputs. When loading simultaneously 2 registers with different lenght, dummy bits are inserted between the ad- dress bits and the data bits of the shorter register (see fig. 8). X = DON’T CARE ST7162

Figure 8:4 Wires Serial Data Transmission Timing ADDRESS AUX A2 AUX A1 AUX A0 REGISTER 0 1 1 R3 : REF COUNTER 1 0 0 R4 : AUX REF. COUNTER DATA AUX DATA D11 MSB = 2048 LSB = 1 AUX D13 AUX D0 MSB = 8192 LSB = 1 X = DON’T CARE ST7162

Figure 12:Switching diagrams. THI OUTTX, OUTRX MCU CLOCK, LD D93TL015 90% 90% TW CLOCK ENABLE 50% 50% 10% 10% TLO TREC CLOCK D93TL016 50% 50% ENABLE 50% 50% TSU FIRST CLOCK LAST CLOCK TSU THOLD 50% 50%DATA IN, AUX DATA IN ST7162

Figure 13:Test Circuit. ST7162

DIP16 PACKAGE MECHANICAL DATA DIM. mm inch a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 ST7162

SO16 PACKAGE MECHANICAL DATA DIM. mm inch A 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45 ° (typ.) D 10.1 10.5 0.397 0.413 E 10.0 10.65 0.393 0.419 e 1.27 0.050 e3 8.89 0.350 F 7.4 7.6 0.291 0.300 L 0.5 1.27 0.020 0.050 M 0.75 0.029 S8 ° (max.) ST7162

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men- tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of SGS-THOMSON Microelectronics.  1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. ST7162