ST52E301

ST52T301 STMICROELECTRONICS | Alldatasheet

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 ST52T301/E301 8-Bit OTP/EPROMDuaLogic MCUs WITH ADC, UART , TIMER, TRIAC & PWM DRIVER ADVANCED DATA SHEET High Speed dedicatedstructures forFuzzy Logic (3.5µs to compute a 4 In x 1 Out rule) Capability to perform simpleboolean and arithmetic operations Up to 4 Input, 2 Output ConfigurableVariables for each Fuzzy Algorithm and up to 300 Rules Up to 16 T riangularand TrapezoidalMembership Functions for each Input variable Up to 256 Singleton Membership Functions for all Consequents Program and Data EPROM: 2 Kbytes 16 general purpose registers available as Register File Working Clock Frequencies:5, 10 and 20MHz On-Chip Clock Oscillator driven by Quartz Crystal or Ceramic Resonator One external interrupt Standard TTL compatible input CMOS compatible output 4 channel 8 bit Analog to Digital Converter Bandgap reference 2.5V Digital 8 bit I/O port indepedentlyprogrammable with handshake signal Serial Communication Interface with asynchronousprotocol (UART) Programmable Timer with internal Prescaler Internal Power Fuzzy Control to drive external Triac (up to 25mA source, 50 mA sink current) Internal Fuzzy controlled PWM to drive an external power device Software tools and Emulators availability Windowed and One Time Programmable (OTP) Memory parts available for prototyping and production phases 44 pinPlastic (PLCC44) and Ceramic Windowed Leaded Chip Carrier (CLCC44-W) July 1998 CLCC44-W PLCC44

1.1 GENERAL DESCRIPTION

ST52E301 (1) and ST52T301 (1) devices are membersof the W.A.R.P .family of 8-bitDuaLogic microcontrollers. They are able to perform, in an efficient way, both booleanand fuzzyalgorithms, in order to reach the best performances that the two methodologies allow. TheST52E301is theerasableEPROMversion and the ST52T301 is the OTP version. The ST52x301 is completely developed and produced by STMicroelectronics using the reliable high performance CMOSM5E (O.7µm) process. Thanks to Fuzzy Logic, ST52x301 allows to describe a problemusing a linguistic modelinstead ofa mathematicalmodel.In thisway it is very useful and easy to modelize complex system with very high accuracy . The linguistic approach is based on a set of IF-THEN rules, describing the control behaviour, and on Membership Functions associated to input and output variables. Fuzzy Inference is a set of operations which computes the output values according with the truth values of the involved rules. Note: (1) Formerly W.A.R.P .3TC

TRIACs) and external sensors. and for the pre-production phases. calculator), the inference unit and the defuzzifier. reference is a 2.5V Bandgap reference. current to power external circuitry. new inputs and feedbackoutputs. high frequency PWM controls. using both internal or external clock, is available. configuration and use of ST52x301. strategy to store the MFs in its internal memory . Figure 1. ST52x301 Architectural Block Diagram

PIN NAME TYPE Programming Phase Working Phase 1 not connected - -

2 AV DD Analog VDD Analog VDD

3 AV SS Analog Ground Analog Ground

4 EV DD EPROM Digital Power Supply EPROM Digital Power Supply

5 EV SS EPROM Digital Ground EPROM Digital Ground

6 VPP

Power supply (12V±5%) EPROM V DD (5V±10%)

7 VDD Digital Power Supply Digital Power Supply

8 VSS Digital Ground Digital Ground

9 P0 I/O I/O EPROM Data Digital I/O

10 P1 I/O I/O EPROM Data Digital I/O

11 P2 I/O I/O EPROM Data Digital I/O

12 P3 I/O I/O EPROM Data Digital I/O

13 P4 I/O I/O EPROM Data Digital I/O

14 P5 I/O I/O EPROM Data Digital I/O

15 P6 I/O I/O EPROM Data Digital I/O

16 P7 I/O I/O EPROM Data Digital I/O

17 READY O I/O port Handshaking Signal

18 P8 O Digital Output

19 TEST I (must be set to 0) (must be set to 0)

20 MAIN2 I/O Zero Crossing/Prescaler Output

21 MAIN1 I Zero Crossing

22 VDD Digital Power Supply Digital Power Supply

23 VSS Digital Ground Digital Ground

24 TRIACOUT O Triac/PWM Driver Output Pulses

25 MODE I Functionment Mode Selector Functionment Mode Selector

26 RESET I General Reset General Reset

27 CE/INT I Chip Enable EPROM External Interrupt

28 TIMEROUT O Output Timer

29 ERES / TRES I EPROM Address Counter Reset External Timer Reset

30 OE / TCTRL I EPROM Output Enable Timer Start/Stop Signal

31 OSCout I/O Oscillator Output Oscillator Output

32 OSCin I Oscillator Input Oscillator Input

33 CADD / TCLK I EPROM Change Address Clock Timer External Clock

34 VSS Digital Ground Digital Ground

35 VDD Digital Power Supply Digital Power Supply

36 TxD O SCI Output

37 RxD I SCI Input

40 AIN3 Ainp Analog Input

41 AIN2 Ainp Analog Input

42 AIN1 Ainp Analog Input

43 AIN0 Ainp Analog Input

44 BG Aout Band Gap Output

T able 1. PLCC44 and CLCC44-W Pin Configuration ST52T301/E301

1.2 PIN DESCRIPTION

VDD, EV DD, VSS ,EV SS, AV DD ,A VSS,VPP .In order to avoid noise disturbances, the power supply of the digital part is kept separatedfrom the power supply of the analog part. V DD. Main Power Supply Voltage (5V 10%). VSS . Digital circuit Ground. EV DD. EPROM Main Power Supply Voltage (5V 10%). EV SS . EPROM Digital circuit Ground. AVDD . Analog VDD of the Analog to Digital Converter. AVSS .AnalogVSS of theAnalogtoDigitalConverter. Must be tied to VSS . VPP . Main Power Supply for the internal EPROM (12.5V 5%). OSCin and OSCout. These pins are internally connected with the on-chip oscillator circuit. A quartz crystal or a ceramic resonator can be connectedbetweenthese two pins in order to allow the correct operations of ST52x301 with various stability/cost trade-offs. An external clock signal can be applied to OSCin,in thiscase OSCout must be grounded. RESET . This signal is used to restart ST52x301 at the beginningof its program.It also allowsto select the program mode for the EPROM. INT. External interrupt active on rising or falling edge. AIN0-AIN3.These 4 lines are connected to the inputs of the analog multiplexer. They allow to acquire 4 analog inputs. BG .A Voltageequal to 2.5Vis availableon this pin. It can be used for Analog signal conditioning. P0-P7.These 8 lines are organizedas oneI/O port. During the Programming phase such port is used for the EPROM data read/write. READY . Handshake signal of the parallel port. P8. Digital output. TxD . Serial data output of the SCI transmitter block. RxD . Serial data input of the SCI receiver block. TRES ,TCLK ,TCTRL ,TIMEROUT .These pins are related with the internal Programmable Timer. The Timer can be reset externally by using TRES. In Working Mode, TRES resets the address counter of the Timer. TRES is active at low level The Timer Clock can be the internal clock or can be supplied externally by using the pin TCLK. Anexternal Start/Stopsignal can be used to control theTimer throughthe pin TCTRL.The Timeroutput is available on the pin TIMEROUT . MAIN1 ,MAIN2 ,TRIACOUT . ST52x301 is able to drive a TRIAC in two different modes: Burst mode or Phase Angle Partialization control mode. The Burst mode is used for thermal regulation. MAIN1 and MAIN2 signals are used to detect the zero crossing of the main voltage. Thepulseto drivethe TRIACis givenbyTRIACOUT pin. It is possible to use the same pins to implement a PWM Driver. In this case it is possible to fix the period of PWMand to changethe duty cycle on fly. The PWM output is given by TRIACOUT pin. CE ,OE ,ERES ,CADD ,V PP . These pins are used to manage the EPROM during the Programming phase. During the Programming phase (programming) V PP must be set at 12V. In the Working phase VPP must be equal toVDD . ERES in Programming Mode resets the address counter of the EPROM; it is active at high level. In the Working phase OE, CE and CADD are used like handshaking signals for the parallel port. MODE . It selects the functionment mode (Programming or Working mode). TEST . It enables the testing functionalities;during the Programmingand Working phaseit mustbe set to 0. ST52T301/E301

2 INTERNAL ARCHITECTURE

ST52x301 is made up by the following blocks and peripherals: Control Unit Fuzzy Core ALU EPROM Clock Oscillator Analog Multiplexer and A/D Converter Prescaler Timer Bandgap Triac / PWM Driver Digital I/O port Serial Communication Interface ST52x301 Operating Modes ST52x301 works in two modes, Programming and Working Modes, depending on the control signals level RESET, TEST and MODE. The Operating modes are selected by setting the control signal level as specified in the Control Signals Setting table.

2.1 CONTROL UNIT

The Control Unit (CU) manages: Registers File, Input Registers, Configuration Registers, ALU, Accumulator and Multiplexer inputs. Moreover the CU drives the Fuzzy Core and the peripherals (T riac/PWM Driver and Timer). The CU reads the stored instructions on the EPROM (Fetch) and decodifies them. If the instructions are arithmetic or logic, the CU runs them directly , sending the control signals to the related blocks. If there is a STOP instruction, the CU transfers the control to the Fuzzy Core. The Fuzzy Core (FC) will read the next instruction (that must be a fuzzy instruction)from the EPROM. The FC mantains the control of the program until the next STOP instruction. Then the FC transfers the control to the CU. Thesecharacteristicsallow to mixfuzzy algorithms with mathematical and logic instructions. Figure 2.1 shows a flow-chart reasuming the logic behaviour of the instructions management. Control Signal Programming Reset Working RESET 00 1 TEST 00 0 MODE 10 0 T able 2.1. Control Signals setting CU Reads fromthe EPROM and Decodifies the instruction CU executesinstruction FuzzyCore Reads fromthe EPROM and Decodifiesthe instruction STOP? STOP? No No Fuzzy Core executesinstruction Yes Yes Figure 2.1. Computation Algorithm Flow Chart ST52T301/E301

8 BIT

2 KBytes

P0..P7 AIN0..AIN3 POWER SUPPLY OSCILLATOR RESET TRIAC/PWM DRIVER MAIN1 MAIN2 TRIACOUT CONTROL UNIT RESETOSCinVSSVDD ALUPC Register FileInput Registers INP_PORT SCI_IN SCI_ST FUZZY_OUT_0 FUZZY_OUT_1 ADC_OUT_0 ADC_OUT_1 ADC_OUT_2 ADC_OUT_3 TMR_OUT TMR_ADC_ST VPP Reg 0 Reg 15 Reg 1 REG_CONF0 REG_CONF15 REG_CONF1 Configuration Registers SCI (UART) TxD TCTRL RxD FLAGS READY OSCout Peripheral Register PERIPH_REG_0 PERIPH_REG_1 PERIPH_REG_2 Figure 2.2. ST52x301 Block Diagram ST52T301/E301

It is not possibile to stop the fuzzy inference before the end of the defuzzificationof one output.Aset of 26 different arithmetic and logic instructions is available.Eachinstruction requiresfrom4 to7 clock pulses to be performed.

2.1.1 Program Counter

The Program Counter (PC) is a 11-bit register that contains the address of the next memory location to be processed by the core.This memory location may be an opcode,an operand or an addressof an operand. The 11-bit length allows the direct addressing mode of 2048 bytes in the program space. After having read the current instruction address, the PC value is incremented. To execute relative jumps the PC and the offset are shiftedthrough the Fuzzy Core or the ALU, where they will be added. The result of this operation is shifted back into the PC. The PC can be changed in the following ways: JP (Jump) instruction PC = Jump Address Interrupt PC = Interrupt Vector RETI instruction PC = Pop (stack) Reset PC = Reset Vector Normal Instruction PC = PC + 1

2.1.2 Flags

The ST52x301 core includes two pairs of flags that correspondto 2 differentmodes:normal mode and interrupt mode. Each pair consist of a CARRY flag and a ZERO flag.One pair (CN, ZN) is used during normal operation and one is used during the interrupt mode (CI, ZI). The ST52x301 core uses the pair of flags that correspond to the actual mode: as soon as an interrupt is generated,the ST52x301core uses the interruptflagsinsteadof thenormal flags.When the RETI instruction is executed the normal flags are restored if the MCU was in the normal mode before the interrupt. It should be observed that each flag set can only be addressed in its own routine. The flags are not cleared during the context switching and remain in the state they were at the exit of the last routine switching. The Carry flag is set when a carry or a borrow occurs during arithmetic operations,otherwise it is cleared. The switching between the two sets of flags is automatically performed when an interrupt or a RETI instruction occur.

2.2 ADDRESS SPACES

W.A.R.P3TC has four separate address spaces: Register File: 16 8-bit registers Input Registers:11 8-bit registers Configuration Registers:16 8-bit registers Peripheral Registers: 3 8-bit registers Program memory up to 2K Bytes The Program memory will be described in further detail in the MEMORYsection

2.2.1 Register File

The Register File (RF) consists of 16 general purpose 8-bit registers Reg0 to Reg15. All the registersin theRF can be specifiedby using a decimal address, e.g. 0 identify the first register of the RF , called Reg0. Reg0:3 are directly connected to the FC input. It means that the input values of the fuzzy algorithm must be loaded into these registers by the user. These registers are used as temporary registers during the macros’computation. ST52T301/E301

Figure 2.5. Input Registers Bench description

2.2.2 Input Registers Bench

The Input Registers (IR) bench consists of 11 8-bit registers containing data or status of the peripherals. All the registerscan be specifiedbyusing a decimal address,e.g. 0 identifies the first register of the IR. The first four registers (ADC_OUT_0:3) of the IR are dedicated to the 4 converted values coming from the ADC. TMR_OUT registers contains the current counted value by the internal Timer; whereas TMR_ST is the Timer status. For details about TMR_ST, please refer to Timer description. Data read by the Parallel I/O Port are stored automatically in the 6-th register, INP_PORT . Data read by the SCI are stored automatically in the 7-th register SCI_IN and SCI status is stored in the SCI_ST register. For details about SCI_ST, please refer to SCI description. The Fuzzy Core writes the computed outputvalues in the FUZZY_OUT_0:1 registers. ST52T301/E301

2.2.3 Configuration Registers

The ST52x301 setting permits to configure all blocks.T able2.2 describesthe relatedblocktoeach bit of the Configuration Registers. Use and meaning of eachregisterwill be described in further details in the corresponding section. Register Peripheral Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG_CONF0 PARALLEL PORT IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 REG_CONF1 SCI, CORE, I/O PORT RDRF OVR BRK TDRE TXC ECKF P8 OUT REG_CONF2 ADC not used IADD 1 ADRST REG_CONF3 SCI BRSL T8 M RE TE REG_CONF4 TIMER TMLSB REG_CONF5 TIMER TMMSB REG_CONF6 TIMER not used POL TMS CKSL TMEL IESL TMST TMRST REG_CONF7 TIMER not used FZSL INPSL INTR INTF INTSL REG_CONF8 TRIAC TCLSB REG_CONF9 TRIAC TCMSB REG_CONF10 TRIAC IOSL PSF CKSL MODE TCST TCRST REG_CONF11 TRIAC INTSL TCMSK TCTRS POL REG_CONF12 TRIAC FZSL INPSL UTPMSB REG_CONF13 TRIAC UTPLSB REG_CONF14 INTERRUPT EXTI not used MSKTC MSKTM MSKSCI MSKAD MSKE REG_CONF15 INTERRUPT INT4 INT3 INT2 INT1 T able 2.2. Configuration Registers description ST52T301/E301

2.2.4 Peripheral Registers

Peripheral Registers contain the initialization values for the Timer, Triac/PWM Driver and Parallel Port. The peripheral initialization value is kept from a location of the Register File, by using a LDPR instruction, or from FUZZY_OUT_0/1 Input Register according with the related Configuration Registers. T able 2.3 describes the related peripheral to each Configuration Register. Use and meaning of eachregisterwill be described in further details in the corresponding section. Peripheral Register Peripheral PERIPH_REG_0 Timer PERIPH_REG_1 Triac/PWM Driver PERIPH_REG_2 Parallel Port T able 2.3. Peripheral Register description ST52T301/E301

2.4 FUZZY CORE

ST52x301 Fuzzy Core main features are: Up to 4 Inputs with 8-bit resolution Up to 16 Membership Functions (Mbfs) for each Input (64 possible Mbfs) Up to 2 Outputs with 8-bit resolution Possibility to process fuzzy rules with a max. number of 8 antecedents

2.4.1 Internal Structure

The block diagram shown in figure 2.9 describes thestructureof ST52x301Fuzzy Core.In thisfigure wecan distinguishdifferentfunctionalblocks:Alpha Calculator, Inference Unit and Defuzzifier. These blocks allow to perform a MAMDANI type fuzzy inference with crisp consequents.It is important to underline that the fuzzy inference is performed by using as inputs the first 4 locationsof the Registers File.

2.4.2 Alpha Calculator Unit

This block performs the intersection(alpha weight) between the input values and the related Mbfs (fig. 2.8). Input Value αij j-th Mbf i-th INPUT VARIABLE Figure 2.8. Alpha Weigth calculation Figure 2.9. Fuzzy Core Block Diagram Notice that the inputs for this block come from the first four locationsof the Register File; it means the user, to evaluate a fuzzy function, must load the input values in these registers. Alpha Calculator performs what is called fuzzification: the input data are transformed in activation level (alpha weight) of the Mbfs. ST52T301/E301

2.4.3 Inference Unit

It managesthe alphaweightsobtainedbythe Alpha Calculator Unit to compute the truth value (ω ) for each rule. This is a calculation of the maximum (for the OR operator) and/or minimum (for the AND operator) performedon alpha values according to the logical connectivesof fuzzy rules. It is possibile to link together up to eight conditions by linguistic connectives AND/OR, NOT operator and brackets. Each rule can have at maximum 8 alpha weights (however they are connected). The truth valueω and the related output singleton are passed to the Defuzzifier to complete the inference calculation. Input 1X1 Input 2X2 OR = Max Input 1X1 Input 2X2 Figure 2.10.

2.4.4 Defuzzifier

This block consists of a Multiplier, two Adders and one Divider. It generates the output crisp values implementing the consequent part of the rules. In this phase each consequent Singleton X i is multiplied by its weight valuesω i, calculatedby the Inference Unit in order to compute the upper part of the defuzzification. Each outputvalue (FUZZY_OUT0, FUZZY_OUT1) is deduced from the consequent crisp values (X by using the defuzzification formula: Yi= ∑ Xijω ij j N ∑ ω ij j N where: i = 0,1 identifies the current output variable N = numberof theactive rules on the currentoutput ω ij =weigth of the j-th singleton Xij = abscissa of the j-th singleton The two fuzzy outputs are stored in the location 9 and 10 of the Input Registers (FUZZY_OUT_0, FUZZY_OUT_1). i-th OUTPUT VARIABLE 0 X ij X X in ω ωij ωin j-th Singleton Figure 2.11. ST52T301/E301

2.4.5 Input Membership Function

ST52x301 allows to manage triangular Mbfs. In order to define a Mbf it is necessary to store three different data on the memory: the vertex of the Mbf:V; the lenght of the left semi-base:LVD ; the lenght of the right semi-base:RVD ; In order to reduce the dimension of the memory area and the computational effort the vertical dimension of the vertex is fixed to 15 (4 bits) By using the previous memorization method it is possible to store different kinds of triangular Memberships Functions. In the following figure is shown a typical example of Mbfs that can be defined in ST52x301 Each Mbf is then defined storing 3 bytes.To store all the information related with the fuzzy project Mbfs, it is necessary to use 192 bytes of the memory (3 bytes*16 Mbfs*4 Inputs = 192 bytes). X LVD RVD V Input Mbf Output Sing leton Output Variable Input Variable w Figure 2.12. Mbfs Parameters Figure 2.13. Example of valid Mbfs The Mbf is memorized by using the following instruction: DAT A n m lvd v rvd where n identifies the input, m identifies the Mbf among the 16 possibleMbfs, lvd, v, rvd are the parameters describing the Mbf’s shape.

2.4.6 Output Singleton

ST52x301uses for the output variablesa particular kind of membership function called Singleton. A Singleton has not a shape, like a traditional Mbf, and it is characterized by a single point identified by the couple (X,ω ), where theω is calculated by the Inference Unit as described before. Often a Singleton is simply identified with its Crisp Value X. ST52T301/E301

2.4.7 Fuzzy Rules. The rules can have the following structures: where op is one of the possiblelinguistic operators (AND/OR) In the first case the rule operators are managed sequentially;in the second one, the priority of the operator is fixed by the brakets. Each rule is codified by using an istruction set, the inference time for a rule with 4 antecedents and 1 consequent is about 3 microseconds. The assembler Instruction Set allowing to manage the fuzzy instructions are reported in the following table: Instruction Description DA T A n m lvd v rvd Stores the Mbf m of the input n with the shape identified by the parameters lvd, v and rvd. LDP n m Fixes the alpha value of the input n with the Mbf m and stores it in the data stack. LDN n m Calculates the negated alpha value of the input n with the Mbf m and store the result in the data stack. FZAND Implements the fuzzy operation AND between the last two values stored in the data stack. FZOR Implements the fuzzy operation OR between the last two values stored in the data stack. LDK Stores the result of the last fuzzy operation executed in the data stack. SKM Stores the result of the last fuzzy operation executed in the memory register M. LDM Copies the value of the register M in the data stack. CON crisp Multiplies the crisp value with the lastω weight. OUT n_out Performs the defuzzification. STOP Ends the fuzzy algorithm. T able 2.4. Fuzzy Instructions Set ST52T301/E301

Example 1: IF Input1 IS NOT Mbf1 AND Input4 is Mbf12 OR Input3 IS Mbf8 THEN Crisp1 is codified by the following instructions LDN 1 1 calculates the NOTα value of Input1 with Mbf1 and stores the result in the data stack LDP 4 12 fixes theα value of Input4 with M12 and stores the result in the data stack FZAND adds the NOTα and α values obtained with the operations LDN1 1 and LDP 4 12 LDK stores the result of the operation FZAND in the data stack LDP 3 8 fixes theα value of Input3 with Mbf8 and stores the result in the data stack FZOR implements the operation OR between the results obtained with the operationsLDK and LDP CON crisp1 multiplies the result of the lastΩ operation with the crisp value Crisp1 Example 2, the priority of the operator is fixed by the brakets: IF (Input3 IS Mbf1 AND Input4 IS NOT Mbf15) OR (Input1 IS Mbf6 OR Input6IS NOT Mbf14) THEN Crisp2 LDP 3 1 fixes theα value of Input3 with Mbf1 and stores the result in the data stack LDN 4 15 calculates the NOT α value of Input4 with Mbf15 and stores the result in the data stack FZAND adds NOT α and α values obtained with the operations LDP 3 1 and LDN 4 15 SKM stores the result of the operation FZAND in the memory register M LDP 1 6 fixes theα value of Input1 with Mbf6 and stores the result in the data stack LDN 2 14 calculates the NOT α value of Input6 with Mbf14 and stores the result in the data stack FZOR implements the operation OR between theα and NOT α values obtained with the two previous operations (LDP 1 6 and LDN 2 14) LDK stores the result of the operation OR in the data stack LDM copies the value of the memory register M in the data stack FZOR implements the operation OR between the last two values stored in the data stack (LDK and LDM) CON crips2 multiplies the result of the lastΩ operation with the crisp value Crip2 At the end of the fuzzy rules set a byte, to identify the output involved in the rules, and the STOP istruction must be inserted. When the STOP instruction is performed, the control of the algorithm goes back to the CU. ST52T301/E301

2.5 ARITHMETIC LOGIC UNIT

The 8-bit Arithmetic Logic Unit (ALU) allows to perform arithmetic calculations and logic instructions which can be divided into 4 groups: Load, Arithmetic, Jump and Program Control instructions (refer to the ST52x301 Assembler Set for further details ). Load Instructions Menmonic Instruction Bytes Cycles Z S LDCF LDCF conf, const 2 6 - - LDRC LDRC reg, const 2 6 - - LDRI LDRI reg, inp 2 6 - - LDPR LDPR per, reg 1 6 - - LDRR LDRR regi, regj 2 6 - - Arithmetic Instructions Mnemonic Instruction Bytes Cycles Z S ADD ADD regi, regj 2 7 I I AND AND regi, regj 2 7 I - SUB SUB regi, regj 2 7 I I SUBO SUBO regi, regj 2 7 I I Jump Instructions Mnemonic Instruction Bytes Cycles Z S JP JP addr 2 6 - - JPNS JPNS addr 2 6 - - JPNZ JPNZ addr 2 6 - - JPS JPS addr 2 6 - - JPZ JPZ addr 2 6 - - SCI Instructions Mnemonic Instruction Bytes Cycles Z S SRX SRX regi 2 5 - - STX STX regi 2 5 - - Notes: I affected - not affected T able 2.5. Arithmetic & Logic Instructions Set The computational time required for each instruction consists of one clock pulse for each Cycle plus 3 clock pulses for the decoding phase. ST52T301/E301

Program Control Instructions Mnemonic Instruction Bytes Cycles Z S RETI RETI 1 5 I I RINT RINT int 1 4 - - STOP STOP 1 4 - - WAITI WAITI 1 4 - - UDGI UDGI 1 4 - - UEGI UEGI 1 4 - - MDGI MDGI 1 4 - - MEGI MEGI 1 4 - - IRQ IRQ int label 2 6 - - IRQM IRQM mask 2 6 - - IRQP IRQP cost 2 6 - - Notes: I affected - not affected T able 2.6. Arithmetic & Logic Instructions Set (Continue) ST52T301/E301

3 EPROM

The EPROM memory provides an on-chip user-programmable non-volatile memory, that allows fast and reliable storage of user data. There are 16K bits of memory space with an 8-bit internal parallelism (2Kbytes) addressed by an 11-bit bus. The data bus is of 8 bits. The memory has a double supply: VPP is equal to 12V±5% in Programming Phase and 5V ±10% during Working Phase.VDD is equal to 5V±10%. The EPROM memory of ST52x301 is divided in three main blocks (see Figure 3.1): Mbfs Setting with (0 through 191) contains the coordinatesof the vertexes of every Mbf defined in the program. Interrupt Vectors (192 through 201) contain the addresses for the interrupt routines. Each address is composed of two bytes. Program Instruction Set (202 through 2048) contains the instruction set of the user program. It can be composed of more Boolean and Fuzzy Algorithms The operation that can be performed, during Programming Phase, on the EPROM are: Writing, Verify, Writing Inhibit, Standbyand Erasing. Figure 3.2 shows the signals timing in Programming Mode. 192 191 202 201 2048 Mbfs Setting Interrupt Vectors Program InstructionsSet Boolean Algorithm Boolean Algorithm Fuzzy Algorithm Fuzzy Algorithm INT_EXT INT_TRIAC INT_TIMER INT_SCI INT_ADC Mbf Parameters Figure 3.1. Memory Map

3.1 EPROM Programming Phase Procedure

Programming mode is selected by applying 12V±5% voltage to the VPP pin and set the control signal as following: RESET: 0, TEST:0, MODE:1. CADD, ERES, OE and CE are the control signals used during the Programming Mode. CADD is active on edge, the others are active on level (OE, CE are active low, ERES is active high). 3.1.1EPROM Writing When the memory is blank, all the bits are at logic level ”1”. The data are introduced by programming only the zeros in the desired memory location; however all input data must contain both ”1” and ”0”. The only way to change ”0” into ”1” is to erase the whole memory ( by exposure to Ultra Violet light) and reprogram it. The memory is in Writing mode when: CE = LOW OE = HIGH with stable data on the data bus P(0:7). The total programming pulse width (CE = 0 V) is, typically , 50µs (by means of 5 pulses of 10µs), but beforeactivating such pulse, it is suggestedto wait for at least 2µs after V PP rises at 12 V . After the disactivation of the pulse it is suggested to wait for ST52T301/E301

at least 2µs before updating the data and the address. The data updating for the next programming is performed, directly by the user, on the data bus P(0:7) while the address is incremented through the pin CADD.

3.1.2 EPROM Verify

A Verify mode is available in order to verify the correctness of the data written. It is possible to activate the Verify mode immediately after the writing of each byte: CE = HIGH OE = LOW Then, if any error in writing occured, the user has to repeat the EPROM writing. The data, during this phase, are avalaible on the bus P(0:7)

3.1.3 Writing Inhibit

It occurs between the Writing and Verify Mode: CE = HIGH OE = HIGH

3.1.4 Standby Mode

The EPROM has a standby mode which reduces the active current from 10mA (Programming mode) to less than 100µA. The Memory is placed in standby mode by setting CE at HIGH Logic Level PP might be equal to 5 V too). When in standby mode, the outputs are in high impedance state.

3.2 Eprom Erasure

Thanks to the transparent window present in the CLCC44-W package,its memory contents may be erased by exposure to UV light. Erasure begins when the device is exposed to light with a wavelengthshorter than 4000Å.It should be noted that sunlight, as well as some types of artificial light, includes wavelengths in the 3000-4000Årange which, on prolonged exposure, can cause erasure of memory contents. It is thus recommended that EPROM devices be fitted with an opaque label over the window area in order to prevent unintentionalerasure. The recommended erasure procedure for EPROM devicesconsistsof exposureto shortwaveUV light having a wavelength of 2537Å. The minimum recommended integrated dose (intensity x expo-sure time) for complete erasure is 15Wsec/cm 2 . This is equivalent to an erasure time of 15-20 minutes using a UV source having an intensity of 12mW/cm 2 at a distance of 25mm (1 inch) from the device window. OE P(0:7) DATA IN VPP 12V CE Inhibit min 2us 2us typ. DATA OUT RESET CADD Writing Verify ERES INPUT PORT 50us typ. OUTPUT PORT3us min. Figure 3.2. EPROM Programming Timing ST52T301/E301

4 INTERRUPTS

The Control Unit (CU) responds to peripheral events and external events through its interrupt channels. When such an event occurs,if it is not maskedand according to a priority order, the current program execution can be suspended to allow the CU to execute a specific response routine. Eachinterrupt is associatedwith an interruptvector that contains the memory address of the related interrupt service routine. Each vector is located in the Program Space (EPROM Memory) at a fixed address (see Interrupt Vectors table fig.4.2).

4.1 Interrupt Functionment

If, at the end of an arithmetic or logic instruction, there are pending interrupts, the one with the highest priority is passed. To pass an interrupt means to storethe arithmetic flags and the current PC in the stack and execute the associated Interrupt routine, whose address is located in one of the EPROM memory location between address 192 and 201. TheInterruptroutine is performedas a normal code checking, at the end of each instruction, if a higher priority interrupt has to be passed. An Interrupt request with the higher priority stops the lower priority Interrupt. The Program Counter and the arithmetic flags are stored in the stack. With the instruction RETI (Return from Interrupt) the arithmetic flags and ProgramCounter (PC) are restored from the top of the stack.This stack, used for the Interrupt priority, is a LIFO queue. An Interrupt request cannot stop the processing of the fuzzy rules but this is passed only after the definitionof the fuzzy output or at the end of a logic or arithmetic instruction.

4.2 Global Interrupt Request Enabling

When an Interrupt occurs, it generates a Global Interrupt Pending(GIP), that can be hanged up by software. After a GIP a Global Interrupt Request (GIR) will be generate and Interrupt Service Routine associated to the interrupt with higher priority will start. In order to avoid possible conflicts between interrupt masking set in the main programor inside macros, the GIP is hanged up through the User Global Interrup Mask or the Macro Global Interrup Mask (see fig.4.3). UEGI/UDGI instruction switches on/off the User GlobalInterrupMask enabling/disablingthe GIR for the main program. MEGI/MDGI instructions set the Macro Global InterruptMask in order toassure that the macrowill not be broken. NORMAL PROGRAM FLOW INTERRUPT SERVICE ROUTINE RETI INSTRUCTION INTERRUPT Figure 4.1. Interrupt Flow Interrupt VectorsINT_TIMER 198 196 200 199 197 195 194 193 192 191 INT_SCI INT_ADC INT_TRIAC INT_EXT 202 201 Figure 4.2. Interrupt Vectors Mapping Global Interrup t Pending User Global Interrupt Mask Macro Global Interrupt Mask Global Interru pt Request Figure 4.3. Global Interrupt Request generation ST52T301/E301

4.3 Interrupt Sources

ST52x301manages interrupt signalsgenerated by the internal peripherals (Timer, T riac/PWM Driver,Analog to Digital Converter and Serial Communication Port) or coming from the INT pin. The polarity of the External Interrupt is programmed by the EXTI bit of the REG_CONF14 (see Table 4.1 and fig. 4.4). EXTI=0 means that INT_EXT is active on rising edge, otherwise it is active on falling edge. Each peripheral can be programmed in order to generatethe associate interrupt;further detailsare described in the related chapter.

4.4 Interrupt Maskability

The interrupts can be masked by configuring the REG_CONF14. The interrupt is enabled when the bit associated to the mask interrupt is ”1”. Viceversa, when the bit is ”0”, the interrupt is masked and is kept pendent. For exampleLDCF 14, 6 (CONF_REG14 =00000110) enables interrupts coming from the ADC (INT_ADC) and from the SCI (INT_SCI).

4.5 Interrupt Priority

Six priority levels are available: level 5 has the lowest priority, level 0 has the highest priority. Level 5 is associated to the Main Program, levels 4 to 1 are programmable by means of the priority register called REG_CONF15 (see fig.4.5); whereas the higher level is related to the external interrupt (INT_EXT). Timer, Triac/PWM Driver, SCI and ADC are identified by a two bits Peripheral Code (see T able 4.2); in order to set the i-th priority level the user must write the peripheral labeliin the related INTi priority level. Bit Name Value Description

0 MSKE

0 External Interrupt

1 External Interrupt

1 MSKAD

0 A/D Converter Interrupt

1 A/D Converter Interrupt

2 MSKSCI

0 SCI Interrupt

1 SCI Interrupt

3 MSKTM

0 TIMER Interrupt

1 TIMER Interrupt

4 MSKTC

0 TRIAC/ PWM Interrupt

1 TRIAC/ PWM Interrupt

7 EXTI

0 Active on Rising Edge

1 Active on Falling Edge

T able 4.1. Configuration Register 14 Description Name Description Priority Peripheral Code Maskable EPROM Locations INT_EXT External Interrupt (INT) Ext Highest - yes 200-201 INT_ADC ADC Int Programmable 00 yes 192-193 INT_SCI SCI Int Programmable 01 yes 194-195 INT_TIMER TIMER Int Programmable 10 yes 196-197 INT_TRIAC TRIAC Int Programmable 11 yes 198-199 T able 4.2. Interrupts Description ST52T301/E301

i.e.LDCF 15, 201(REG_CONF15=11001001) define the following priority levels: Level 1: INT_SCI(SCI Code: 01) Level 2: INT_TIMER(TIMER Code: 10) Level 3: INT_ADC(ADC Code: 00) Level 4: INT_TRIAC(TRIAC Code: 11) When a source provides an Interrupt request, and the request processing is also enabled, the CU changes the normal sequential flow of a program bytransferingprogramcontrol toa selectedservice routine. Whenan interruptoccurs the CU executes a JUMP instruction to the address loaded in the related location of the Interrupt Vector Whenthe executionreturnsto the originalprogram, it begins immediately following the interrupted instruction.

4.6 Interrupt RESET

An eventually pending interrupts can be reset with the instructionRINT int iwhich resets thei-th interrupt Bit Name Value Level 0, 1 INT1 Peripheral Code High 2, 3 INT2 Peripheral Code Medium-High 4, 5 INT3 Peripheral Code Medium-Low 6, 7 INT4 Peripheral Code Low T able 4.3. Configuration Register 15 Description Figure 4.6. Example of a Sequenceof Interrupt Requests ST52T301/E301

5 CLOCK

ST52x301 can work by using a 5, 10 or 20 MHz clock. The ST52x301 Clock Generatormodule generates the internal clock for the internal Control Unit, ALU, Fuzzy Core and on-chip peripherals and it is designed to require a minimum of external components. Thesystemclock maybe generatedby usingeither a quartz crystal, or a ceramic resonator (CERALOC); or, at least, by means of an external clock. The different clock generator options connection methods are shown in Figure 5.1. When an external clock is used, it must be connectedon thepin OSCin while OSCoutmust be grounded. The crystal oscillator start-up time is a function of manyvariables:crystal parameters(especiallyR S), oscillator load capacitance (CL), IC parameters, ambient temperature, supply voltage. It must be observed that the crystal or ceramic leads and circuit connections must be as short as possible. Typical values for CL1, CL2 are 10pF for a 20 MHz crystal. Figure 5.1. Oscillator Connections ST52T301/E301

1. A/D CONVERTER The A/D Converter of ST52x301 is an 8-bit analog to digital converter with up to 4 analog inputs offering 8 bit resolution with a total accuracy of 2 LSB and a typical conversion time of 32µs. The conversion range is 0 - 2.5 V. The A/D peripheral converts the input voltage with a process of successive approximations using a fixed clock frequency derived from the oscillator. The ADC uses 5 registers: one Configuration Register, REG_CONF2, and four Data Registers. These 4 registers are the first 4 Input Registers. The A/D converter drives the analog Multiplexer in order to sequentially pick up the external inputs to be put in output and stored automatically in 4 8-bit registers. It is possibileto configurethe Multiplexerby means of the register REG_CONF2, in order to select the number of analog inputs to convert. For example, if the bit 3 and bit 2 of REG_CONF2 are configured at 10, then the Multiplexer will sequentially pick up only the inputs 0,1 and 2. Table 6.1 shows the convertion sequences according to the possible values of the two bit REG_CONF2 (3:2). The A/D Converter, at the end of the conversion, will send a signal (end-of-conversion)which can be used like an interrupt signal. The user can select the priority of the A/D interrupt and mask it (see ”Interrupt Routine” chapter) The conversion starts writing ”1” on REG_CONF2(0).The A/D is reset by writing ”0” in REG_CONF2(0). The converted dataare automaticallystored in four 8-bit Input Registers. By performing an instruction: LDRI regj ingi theanalog input ”ingi”is loadedin theregister”regj” of the Register File. Figure 6.1. A/D Converter Structure CONF_REG2 (3:2) INPUT SEQUENCE

00 Ain0

01 Ain 0, Ain1

10 Ain 0, Ain 1, Ain 2

11 Ain 0, Ain 1, Ain 2, Ain 3

T able 6.1. ST52T301/E301

The power consumption of the device can be reduced by turning off the A/D converter, T o switchoff the A/Dconverter the CONF_REG2(0) bit must be reset to ”0”. The A/D Converter features a sample and hold. The input voltage Ain, which has to be converted must be constant, for 12.8µs. An internal bandgap reference is available on pin 44, BG. By using this signal as reference for the signal to be converted, the conversion accuracy is not strongly related with the variation of the power supply. The power supply of the A/D converter (AV DD and AVSS ) in order to avoidinterferencesis mantained separatedfrom the powersupply of the digitalcore. D7 D6 D5 D4 D3 D2 D1 D0 ADC Configuration Register REG_CONF2 Reset ADC Must be 1 ADC input selection Not used Figure 6.2. Configuration Register REG_CONF2 ST52T301/E301

7.TIMER ST52x301 offers one on-chip Timer peripheral. TheTimer consists of an 8-bit counter with a 16-bit programmable prescaler, thus giving a maximum count of 2 24, and control logic that allows configuring the functionment and the type of peripheral outputs. Figure 7.2 shows the Timer block diagram and Figure 7.3 shows the internal structure of the Timer. Thecontent of the 8-bit countercan be read/written and is incrementedon the RisingEdge of the 16-bit prescaleroutput(PRESCOUT).Moreover,it can be read under program control at any instant of the counting phase and loaded in a location of the RegisterFile.The prescalercan be given any value between 0 and FFFFh setting the 4-th (TMLSB) and 5-th (TMMSB) locations of the Configuration Registers Bench.

7.1 Timer Functionment

The Timer requires three signals: TMRCLK, TRST and TSTART (see Figure7.3). Each of them can be generatedinternally or externally, this possibility is programmable by the user. TMRCLK increments the counted value of the Prescaler. It can be, by setting CKSL of REG_CONF6 register, the internal clock signal (CLKM) or the signal provided on the pin TCLK. TRST resetsto zerothe contentof the 8 bit counter. It is generated by the TRES or RESET external signalsor it is forcedby TMRSTbit of REG_CONF6 register. TST ART starts/stops the Prescaler counting.It can be given on the pin TCTRL or it is forced by TMST bit of REG_CONF6 register. The TST ART signal allows to work in two different modes: LEVEL (Time Counter): If the TST ART signal is high the Timer starts the count.When the TST ART is low the count is stoppedand the current value is stored in the TMR_OUT register of the Input registerBench, then it can be transferred to the j-th location of the Registers File by using the instruction: LDRI reg-j 4 EDGE(Period Counter): After the reset, when the first edge of the TST ART signal appears, the Timer starts the count, at the next TST ART the Timer is stopped.In this way it is possible to measure the period of an external signal. The functionment modality is set by the TMEL configuration bit of REG_CONF6 register. The starting value of the Counter can be either a value contained in the Register File or directly a Fuzzy Output.If INPSL (REG_CONF7(3)) is set to ”1” then the value comes from one of the locations of the Register File (LDRP 0, reg-i);on the contrary it is generated by the Fuzzy Core. The choice between the two possible fuzzy outputs is set by the FZSL configuration bit of REG_CONF6 register FZSL=0/1 means the starting value is the loaded from the FUZZY_OUT_0/1. Level Edge start stop start start stop start 00 0 33321 Reset Clock Counted Value Figure 7.1. Timer Functionalities ST52T301/E301

Figure 7.2. Timer Peripheral Block Diagram ST52T301/E301

Figure 7.3. Timer Internal Structure ST52T301/E301

7.2 Timer Interrupt

It is possible to enable the Timer Interrupt by software control.The Timer can be programmedto generate an Interrupt request until the end of the count or when there is an external TSTART signal. The Timer can generate programmable Interrupts in to 4 different modes: Interrupt mode 1: Interrupt on counter Stop. Interrupt mode 2: Interrupt on Rising Edge of TIMEROUT . Interrupt mode 3: Interrupt on Falling Edge of TIMEROUT . Interrupt mode 4: Interrupt on both edges of TIMEROUT . Inorder toprogramtheinterruptmode INTSL,INTF and INTR bits of the REG_CONF7 must be set following theindicationsshownin the Table7.1.The Timer interrupt can be used to exit the MCU from the WAIT mode.

7.3 Timer Configuration

The Timer configurationneeds to set 4 registersof the Configuration Register Bench. CONF_REG4: TMLSB contains the less significative bits of the Prescaler starting value. CONF_REG5: TMMSB contains the more significative bits of the Prescaler starting value Timer Output Type 1 Type 2 Prescout*Counter Figure 7.4.TIMEROUT Signal Type INTERRUPT MODE INTSL INTF INTR

11 X X

T able 7.1. Timer Interrupt Setting D7 D6 D5 D4 D3 D2 D1 D0 REG_CONF4 Timer TMLSB - Prescaler Init Value Less Significative Bits D7 D6 D5 D4 D3 D2 D1 D0 REG_CONF5 Timer TMMSB - Prescaler Init Value More Significative Bits Figure 7.5. Timer Configuration Register 4 and 5 ST52T301/E301

REG_CONF6 Timer TMRST - Internal Timer Reset TMST - Internal Timer Start not used IESL - Internal/External Signals Selector TMEL - Edge/Level Timer Abilitation TMS - Timer Output Shape POL - Timer Output Polarity CKSL - Internal/External Clock Select Figure 7.6. Timer Configuration Register 6 Bit Name Value Description

0 TMRST

0 Stop

1 Start

1 TMST

2 IESL

0 Internal Signals

1 External Signals

3 TMEL

4 CKSL

0 Internal Timer Clock

1 External Timer Clock

0 Pulse Wave (Type 2)

1 Square Wave (Type 1)

6 POL

0 Positive Polarity

1 Negative Polarity

T able 7.2. Configuration Register 6 DescriptionCONF_REG6: TMRST sets the internal INR signal. TMST sets the internal INS signal. IESL selects the source of the TRES and TST ART signals. IESL=”0”signalsare the internal INRand INS. IESL=”1” signals come from the TRES and TCTRL pins. TMEL selects the TST ART signal allowing to work inLevelMode or inEdge Mode like previously described. TMEL=”0” means Edge Mode TMEL=”1” means Level Mode. CKSL selectsthe source of the TMRCLK(work- ing Timer frequency). CKSL=”0”, the TMRCLK is the internal MCLK divided by the Prescaler starting value. CKSL=”1”, the TMRCLK is an external clock by TCLK pin. TMS TIMEROUT is a signal with frequency equal to the working Timer frequency divided by the starting value of the Pres- caler (16 bit) and Counter (8 bit). The Timer outputcan be eithera squarewave with duty-cycle 50% or a pulse signal (with the pulse durationequal tothe Pres- caler output signal period). TMS=”1”, TIMEROUT is a square wave TMS= ”0”, TIMEROUT is a pulse signal. POL defines the polarity of the Timer output signal (TIMEROUT). ST52T301/E301

Bit Name Value Description

0 INTSL

0 INT_TMR on Falling Edge of

1 INT_TMR on Edges of

1 INTF

0 NO INT_TMR on Falling

1 INT_TMR on Falling Edge of

2 INTR

0 NO INT_TMR on Rising

1 INT_TMR on Rising Edge of

3 INPSL

0 Timer Data Input coming

1 Timer Data Input coming

from a Register File location

4 FZSL

from FUZZY_OUT_0 from FUZZY_OUT_1 5 not used - 6 not used - 7 not used - T able 7.3. Configuration Register 7 Description D7 D6 D5 D4 D3 D2 D1 D0 REG_CONF7 Timer INTSL - Interrup t GeneratorSelector INTF - Interrupt on TIMEROUT Falling Edge INTR - Interrupt on TIMEROUT Rising Edge INPSL - Input Data Selector FZSL - Fuzzy Input Selector not used not used not used Figure 7.7. Timer Configuration Register 7 CONF_REG7: INTSL It allows to select the interrupt mode for the Timer. INTSL=”0” Interrupt is generated on the falling edge of the Counter Stop. INTSL=”1” the interrupt is generated on the edges of TIMEROUT . INTF INTR INPSL selects the source of the value of the Counter between a location of the Regis- ter File and the Fuzzy Core. INPSL=”0”, Counter value coming from the FC. INPSL=”1”, Counter value coming from the RF . FZSL FZSL=”0”,the valueof the TimerCounter is equal to FUZZY_OUT_0 FZSL=”1”,the valueof the TimerCounter is equal to FUZZY_OUT_1 ST52T301/E301

8 I/O PORT

ST52x301 is provided with dedicated lines for input/output.These lines, grouped into an 8-bit I/O Port P(0:7), can be programmedto provide parallel input/output with a handshake line (READY) to carry data in/out. The I/O Port is not able to perform operations on the single bit, and the communication cannot be performed at the same time in input and output. It is possible to program the parallel port direction by using the register REG_CONF0 in order to set which bits are in input and which are in output. The port has an internal register (PERIPH_REG_2) dedicated to hold output data coming from the Register File through an LDPR instruction. Inputdata are automaticallystored in the IN_PORT register, 6-th location of the Input Register. P8 pin is a digital output line available directly connected to the OUT bit of the REG_CONF1; then it can be set by using a LDCF instruction. (see table 8.2 and Figure 8.8) PERIPH_ REG_2(i) P(0:7) I/O PIN TTL CMOS IO(i) INP_PO RT(i) TRISTATE REG_CO NF0(i ) OUTPUT PINREG_CO NF1(0 ) OUT Figure 8.1. Figure 8.2. ST52T301/E301

8.1 I/O PORT CONFIGURATION

REG_CONF0 allows dynamic change in I/O Port configurationduring program execution setting the communication direction of each bit. IOi setting equal to ”0” configures the i-th bit of the P(0:7) I/O Port in input. Data com- ing from external digital devices are stored in the 6-th location (INP_PORT)of the Input register bench. IOi=”1” sets the i-th bit of the port in output. Data stored in the i-th location of the Register File is written on the port by using the instruction: LDPR 2, regi Bit Name Value Description

0 IO0

0 Input Pin

1 Output Pin

1 IO1

2 IO2

3 IO3

4 IO4

5 IO5

6 IO6

7 IO7

T able 8.1. Configuration Register 0 Setting D7 D6 D5 D4 D3 D2 D1 D0 REG_CONF0 I/O Port IO0 - I/O Communication Direction Bit IO1 - I/O Communication Direction Bit IO2 - I/O Communication Direction Bit IO3 - I/O Communication Direction Bit IO4 - I/O Communication Direction Bit IO5 - I/O Communication Direction Bit IO6 - I/O Communication Direction Bit IO7 - I/O Communication Direction Bit Figure 8.3. Configuration Register 0 ST52T301/E301

8.2 INPUT HANDSHAKE

Figure 8.5 illustrates the timing associatedwith the READY Handshake signal, when the instruction LDRI reg 6 is performed. When the LDRI instruction is executed to read the port, ST52x301 resets the READY signal to indicate that it is not possible to change the input data during this phase of reading. T o synchronizethetransmission withREADYsignal will prevent the INP_PORT data from changing while ST52x301 is reading the port. READ PORT signal represented in figure 8.5 is an ST52x301 internal signal. Input data on the port are continuously sampled and are strobed into the port only when READY is set. W.A.R.P .3TC xxxxxx0 x REG_CONF1 P(7:0) IOP EXTERNA L PERIPHERA L DATA READY I/O PORT Figure 8.4. One Line Input Handshake PIO(7:0) READY DATA IN READ PORT CLK NEW DATA IN Figure 8.5. One Line Input HandshakeTiming ST52T301/E301

8.3 OUTPUT HANDSHAKE

Figure 8.7 illustrates the timing associatedwith the READY Handshake signal, when the instruction LDPR 2 reg is performed. WhenREADY is reset no significantdata are on the output port pins, because ST52x301 is writing into the PERIPH_REG_2. When the data is ready in PERIPH_REG_2, READY signal is set. The rising edge of READY signal can be used as a latching signal. No peripheral acknowledge is waited for. If the signal READY is high, it means that the data out is still not read.In this case, the followingLDPR instruction is stored in a one register peripheral stack. If the READY is maintained high, the following LDPR instructions store the data coming from the Registers File on the same register stack. Figure 8.6. One Line Output Handshake Figure 8.7. One Line Output Handshake Timing ST52T301/E301

It means thateach LDPRinstruction deletesthe old value contained in the parallel port stack register and rewrite a newvalue on the samestackregister. Only the last LDPR instruction is executed if the READY signal is maintained high during several LDRP instructions. Bit Name Value Description 0P 8 - Digital Output Bit ECKF 00 5 MHz 01 10 MHz 10 20 MHz 11 20 MHz

3 TXC

0 SCI End Transmission

1 SCI End Transmission

4 TDRE

5 BRK

0 SCI Break Error Interrupt

1 SCI Break Error Interrupt

6 OVR

0 SCI Overrun Error Interrupt

1 SCI Overrun Error Interrupt

7 RDRF

0 SCI Received Data Register

1 SCI Received Data Register

T able 8.2 Configuration Register 1 Setting Figure 8.8. ST52T301/E301

9 SERIAL COMMUNICATION INTERFACE

The Serial Communication Interface (SCI) integrated into the fuzzy processor ST52x301 provides a general purpose shift register peripheral, that allows to link several widely distributed MCUs, through their SCI subsystem. The SCI gives a serial interface providing communication with common baud rates, up to 38400 Hz, and flexible character format. The SCI is a full-duplex UART -type asynchronous system with standard Non Return to Zero (NRZ) format for the transmitted/received bit. The length of the transmittedword is 10/11 bits (1 start bit, 8/9 data bits, 1 stop bit). The SCI is composed of three modules: Receiver, T ransmitter and Baud-Rate Generator and it is configured by means of Configuration Registers 3 and 1.

9.1 SCI RECEIVER BLOCK

The SCI Receiver block manages the synchronization of the serial data stream and stores the data characters. The SCI Receiver is mainly formed by two sub-systems: Recovery Buffer Block and SCDR_RX Block. The RE configuration bit set to ”1” (Configuration Register 3) enables the SCI Receiver. The SCI receives data coming from the RxD pin and drives the Recovery Buffer Block, that is a high-speed shift register operating at a clock frequency (CLOCK_RX) 16 times higher than the fixed baud rate (CLOCK_TX). This sampling rate, higher than the Baud Rate clock, allows to detect Figure 9.1. SCI transmitted word structures Figure 9.2. SCI Block Diagram ST52T301/E301

Bit Name Value Description 0T E

0 Transmission DISABLED

1 Transmission ENABLED

0 Receiver DISABLED

1 Receiver ENABLED

M 00 8, No Parity, 1 bit stop 01 8, No Parity, 2 bit stop 10 8, Parity, 1 bit stop 11 9, No Parity, 1 bit stop 4T 8 Parity Odd, if Parity is selected (M= 10); otherwise 9th Data bit Parity Even, if Parity is selected (M = 10); otherwise 9th Data bit BRSL 000 600 Hz 001 1200 Hz 010 2400 Hz 011 4800 Hz 100 9600 Hz 101 19200 Hz 110 38400 Hz

111 External Clock

T able 9.1 ConfigurationRegister 3 SettingtheSTART condition,theNoiseerrorand theFrame error. When the SCI Receiver is in IDLE status, it is waiting for the START condition, that is obtained with a logic level 0, consecutive to a logic level 1. Thisconditionis detected,if,with thefixedsampling time, three logic levels 0 are sampled after three logic levels 1. The recognition of the ST ART bit forces the SCI Receiver Block to enter in an data acquisition sequence, according to serial mode. The 2 bits, M, of the ConfigurationRegister 3 allow todefinethe serial modewith theconventionshown in table 9.2. Thebit, T8,in caseof M= 10 is used to setthe parity check to perform,as indicatedin the previoustable 9.2. The recognition of STOP condition allows to transferthe received data, from Recovery Bufferto SCDR_RX buffer, adding the eventual ninth data bit,accordingto the meaningshown in the previous table 9.2. After this operation, RXF flag of SCI Status Input Register 8 (fig.9.3) is set to logic level 1.The Control Unit reads the data from SCDR_RX buffer (in read-only mode) with SRX instruction and provides a reset at logic level 0 to RDRF flag. If a data of Recovery Buffer is ready to be transferred into SCDR_RX buffer, but the previous one was not yet read by the Core, an OVERRUN Error takes place: the status flag OVERR indicates the error condition. In this case the information stored in SCDR_RX buffer is not altered, but the one that has caused the OVERRUN error can be overwritten by a new data coming from the serial data line. Recovery Buffer Block This block is structured as a synchronised finite state machine on the CLOCK_RX signal falling edge. When the Recovery Buffer Block is in IDLE state it waits for the reception of the correct 1 and 0 sequence representing the ST ART . The recognition takes place by sampling the input RxD at CLOCK_RX frequency, that has a frequency 16 times higher than CLOCK_TX. For this reason, while the external transmitter sends a single bit, the Recovery Buffer Block samples 16 states (from SAMPLE1 to SAMPLE16). ST52T301/E301

Bit Name Value Description 0P 8 - Digital Output Bit ECKF 00 5 MHz 01 10 MHz 10 20 MHz 11 20 MHz T able 9.2 Configuration Register 1 SettingThe analysis of RxD input signal is carried out looking three samples for each bits received.0 If these threesamples are not equal, then the noise error flag, NSERR, of Input Register 8 is set to 1 and the received data value will be the one assumed by the majority of the samples. By means of the procedure described above, to avoid SCI becomes IDLE, because of a limited noise due to an erroneous sampling, the transmissionis recognizedas correctand the noise flag error is set. At the end of the cycle relative to the reception of a bit, Recovery Buffer Block will repeat the same steps 9 times: one step for each received bit, plus oneforthe stop acquisition(10timesin caseof 9-bit data, double stop or parity check). Atthe endof datareception,RecoveryBufferBlock, will supply information on eventual frame errors by setting to 1 FRERR flag bit of Input Register 8. A frame error can occur if the parity check has not been successfully achieved or if STOP bit has not been detected. If Recovery Buffer Block receives 10 consecutive bits at logic level 0, a break error occurres, and interrupt routine request starts. SCDR_RX block It is a finite state machine synchronized with the falling edge of the clock master signal, CKM. The SCDR_RX block waits the signal of complete reception, from the Recovery Buffer, to load the word received. Moreover, the SCDR_RCX block loads the values of FRERR and NSERR flag bits (Input Register 8), and sets the RXF flag to 1. Using SRX instruction the data are transferred to Register File and RXF flag is reset to 0, to indicate SCDR_RX block is empty. If a new data arrives before the previous one has been transferred to Register File, an overrun error occurres and OVERR flag, of Input Register 8, is set to 1. ST52T301/E301

9.2 SCI TRANSMITTER BLOCK

The SCI T ransmitter Block consists of the following underblocks: SCDR_TX and SHIFT REGISTER, synchronized, respectively , with the clock master signal (CKM) and the CLOCK_TX. The whole block receives through Configuration Register 3 (M bits) the settings for the following transmission modes (see table 9.1): 8-bit word and a single stop signal 8-bit wordplus a paritybit and a singlestop signal 8-bit word plus a double stop signal 9-bit word In case of 9 bit frame transmission, the most significative bit arrives through T8 of the Configuration Register 3. In an 8-bit transmission, instead, T8 is used to configure the SCI, according to information containedin M (seetable9.1):in particularto chose the polarity control (even or odds) to implement the parity check. After a RESET signal, RST , the SCDR_TX block is in IDLE stateuntil it receivesenablingsignal,TE=1, of Configuration Register 3. If TE=1, using STX instruction the data, to be transmitted, are transferred from Register File to SCDR_TX block and the flag of Input Register 8, TXEM, is reset to 0, to indicate SCDR_TX block is full. If the core supplies a new data, this could not be loaded in the SCDR_TX blockuntil the current data has not been unloaded on the Shift Register block. This means that only when TXEM is 1, it is possible to load data in the SCDR_TX Block. When the SHIFT REGISTER Block loads the data to be transmitted on an internal buffer, TXEND is reset to 0 to indicate the beginning of a new transmission. At the end of transmission TXEND is set to 1, allowing to load in the SHIFT REGISTER a new data coming from SCDR_TX. It is important to underline that TXEND = 1 does notmean SCDR_TXis readyto receivea newdata. Forthis reason it is better to utilisethe TXEM signal to synchronize the STX instruction to the SCI TRANSMITTER block If ST52x301 core resets TE to 0, the transmission is interrupted, but the SCI Transmitter block completes the transmission in progress before to reset.

9.3 Baud Rate Generator Block

The Baud Rate Generator Block performs the division of the clock master signal (CKM), in a set of synchronism frequencies for the serial bit reception/transmissionon the external line. T able 9.1.shows the set of frequenciesselected by means of BRSL (Configuration Register 3). Reception frequency (CLOCK_RX) is 16 times higher than transmission frequency(CLOCK_TX) . If BRSL is equal to 111, CLOCK_RX and CLOCK_TX signals coincide with clock master, CKM. Figure 9.3. SCI Status Input Register ST52T301/E301

10 TRIAC/PWMDRIVER

ST52x301 offers a peripheral able to generate a signal on pin 24, TRIACOUT , to drive an external device, like a TRIAC, a IGBT or a Power Mos. T riac/PWM driver can perform 3 different working modes according to REG_CONF10 bits, MODE (see T able 10.4): MODE = ”01”: PWM MODE = ”10”: Burst Mode Triac Control (Thermal Regulations) Note: in this case CKSL of REG_CONF10 must be set to ”1x”. (see Table 10.4) MODE = ”11”: Phase Angle Partialization Triac Control (Motor Control) The Triac/PWM Driver can be initialized by using a valuefixed by a controlalgorithm, that can be either the output of a fuzzy inference or the result of an arithmetic calculus stored in the Register File. In the latter case, by using theLDPR 1,reg-i instruction, the value, contained in the i-th register of Register File, is stored in the T riac Driver/PWM peripheral register PERIPH_REG_1. Figure 10.1 shows the internal structure of T riac/PWM Driver. PWM Mode The PWM working mode is obtained by setting REG_CONF10 bits, MODE, at ”01” value. It consistsof a signal,with fixed period, whoseduty cycle can be modified. Figure 10.1. TRIAC/PWM Driver Simplified Block Diagram ST52T301/E301

REG_CONF8 TRIAC / PWM TCLSB - Prescaler init value Least Significative Bits D7 D6 D5 D4 D3 D2 D1 D0 REG_CONF9 TRIAC / PWM TCMSB - Prescaler init value Most Significative Bits Figure 10.2. TRIAC/PWM Configuration Register 8 and 9 The PWM period can be generated, internally, by dividing the masterclock or, externally, by using an external clock signal. In both cases, the clock signal is dividedby a 16-bit Prescaler, managed by REG_CONF8 and REG_CONF9 (see Figure 10.2). The duty cycle is fixedby a value,that can be either the output of a fuzzy inference or the result of an arithmetic calculus. In the first case, it can be loaded directly in the register of the peripheral, otherwise it can be stored in one location of the Register File for further manipulations and then used for the control of the PWM. Burst Mode It is based on turning on and off the TRIAC, for a fixed integer number of main voltage periods, in order to control the power transferred to the load. For this reason a Burst Mode TRIAC control consists of a signal, with a period, T, containing an integer number of the main voltageperiods, whose duty cycle is proportional to the number of periods in whichthe TRIAC is ON (Duty Cycle).This kind of T riac control is mainly used for thermal regulation. Theduty cycle is fixedbya valuethatcan be directly the output of a fuzzy inference or the result of an arithmetic calculus. In order to work in Burst mode, it is necessary to detect the pre-post zero-crossing of main voltage, by using an external inserting circuitry. The user can define the period T , by means of the internal 16-bit prescaler, setting REG_CONF8 and REG_CONF9 (see Figure 10.2).T is proportionalto the main voltage period, it is in the range 0 to 21.8 sec (if the main frequencyis 50Hz). The width and the polarity of the pulses can be programmed according to the T riac and the circuit characteristics. Phase Angle Partialization Mode This methodis based on turning on the TRIAC only for a part (phase angle) of each main voltage period. When the phase angle is large the energy (power)supplied to the loadis low,viceversa,when the phase angle is small the energy supplied to the load is high. The phase angle can be fixed by a fuzzy algorithm or by a value stored in the Register File. The phase angle is an 8-bit value. The peripheral is programmable in order to work with a main voltage frequency of 50 or 60 Hz. ST52T301/E301

10.1 PWM GENERATOR WORKING MODE

When REG_CONF10 (3:2) bits, MODE, are ”01”, the peripheral is programmed to work in PWM Mode. By using the 16-bit prescaler, the PWM period can be generated by dividing the internal master clock, or an external clock signal applied on the pin MAIN1,or the main voltagefrequency,by using the circuit shown in Figure 10.6. NOTE: The external clock signal, applied on MAIN1 pin,must have a frequency at least three time smaller than the internal master clock. The clock source can be selected by using REG_CONF10(5:4)bits,CKSL(see Table10.4and Figure 10.9).If the clock source selected is not the main voltagefrequency(CKSL=1x), MAIN2pin can be configured as input or output, by using REG_CONF10(7) bit, IOSL (see T able 10.4). If MAIN2 is an output, on this pin it is possible to get the prescaler output signal Tck. The period of the PWM signal is obtained by using the following relation: T=256*Tck where Tck is the output of the 16-bit prescaler managedby REG_CONF8 and REG_CONF9(see Figure 10.2). NOTE. In PWM working mode, the value N, stored in the 16-bit prescaler, must be in the range from 2 to 2 16-1 By using a 20 MHz clock master it is possible to obtain a PWM frequency in the range 1.2 Hz to 26.04 KHz. The value T on is proportional to a value, INIT_VALUE, that can be a fuzzy output or a value Value Description

01 PWM Driver

10 Burst Mode Control(1)

11 Phase Angle Control

Note:(1)REG_CONF10(5) must be set to ”1” T able 10.1.MODE - Triac/PWMWorking Mode Settings MCLK Frequency 1/T min max 5 MHz 0.3Hz 6.51 kHz 10 MHz 0.6 Hz 13.02 kHz 20 MHz 1.2 Hz 26.04 kHz T able 10.2. PWM Frequencies T=2 5 6*T c k Ton = INIT_VALUE* Tck Toff TRIACOUT Figure 10.3. PWM Functionament coming from Register File, according with the INPSL and FZSL configuration bits of REG_CONF12 (see Table 10.6 and Figure 10.12). The Ton is equal to: T on= INIT_VALUE*Tck. It means the Ton can be fixed by the control algorithm that can be either the output of a fuzzy inference or the result of an arithmetic calculus. In thesecond case,the data,stored in the i-th location of the Register File, can be loaded by using the instruction: LDPR 1, reg-i. If the INIT_VALUE is 255 the Toff is equal to Tck. ST52T301/E301

10.2 BURST MODE

When REG_CONF10 (3:2) bits, MODE, are ”10” the peripheral is programmed to work in BURST MODE. Notice that when you are working in Burst mode CKSL must be set to ”1x”. (see Table 10.4) A square wave, Tb, is generated with a duty cycle proportional to the power the user intends to transfer on the load. A pulse is generated for each zero crossing of the main voltage included in the T on of the fixed period. Figure 10.4 shows the typical Burst Controlworking mode.The periodT of the signal Tb (see Figure 10.4) is equal to 256*Tck. Thesignal Tckis generatedprogrammingthe 16-bit Prescaler, by REG_CONF8 and REG_CONF9 (see Figure 10.2). Tck is equal to the main voltage frequency (50 or 60 Hz) divided by N+1, where N value is from 0 to 2 16-1. The value T on is proportional to a value, INIT_VALUE, that can be a fuzzy output or a value coming from Register File, according with the INPSL and FZSL configuration bits of REG_CONF12 (see T able 10.6 and Figure 10.12). On TRIACOUT pin is generated a sequence of pulses, programmed, by using REG_CONF11(0) bit, POL (see T able 10.5), in order to be positive or negative, to drive the Triac in different quadrants. The number of generated pulses, N_PULSES, is: N_PULSES = 2 [(N+1)*INIT_VALUE - N] where N is the value stored in the 16-bit pescaler. Then Ton = (N_PULSES / 2)* T POWER LINE The first pulse is obtained during the first zero crossing of the main voltage and the last one is generated after INIT_VALUE*Tck clock pulses, where Tck is the Prescaler output, generated by using the main voltagefrequencyapplied to MAIN1 and MAIN2 pins. Theperipheral can be programmed inorderto work with 50 or 60 Hz main voltage frequency,by setting the REG_CONF10(6) bit, PSF (see Table 10.4). Ranges of the Tb signal period depend on the power line frequency(see Table 10.3). In order to drive a Triac in Burst Mode it is required to generate a sequence of pulse, that must be centred on the zero crossing of the power line as shown in the Figure 10.7. For this reason, the pre zero crossing and the post zero crossing of the power line must be detected. T o detect the zero-crossing and get also the main voltage frequency, the user must generate MAIN1 and MAIN2 signals, by using the circuit shown in Figure 10.6. MAIN1 and MAIN2 signals are used in the block called PULSE GENERA TOR of the peripheral (see Figure 10.1). In particular the pulses are generatedby using the rise edge of the signal MAIN1 and the falling edge of the signal MAIN2. Figure 10.5 shows the generation of the T riac pulses Tp . The first firing pulse for the Triac is generated on the zero crossing of the power line, while the next pulses are centred on the zero crossing. Power Line Frequency T min max 50 Hz 5.12 s 335544 s 60 Hz 4.26 s 279620 s T able 10.3. TRIACOUT Signal Period -1.5 -0.5 0.5 1.5 Ton Tb Power Line TRIACOUT T = 256 * Tck Figure 10.4. Burst Working Mode ST52T301/E301

and Figure 10.11), is introduced after each firing pulse (see Figure 10.7): Masking time =(2^TCMSK*200 +100) nS. If TCMSK is 0 then Masking time is 0. In fact, to avoid the detection of electrical noise, during the masking time no signal, coming from MAIN1 and MAIN2, is taken into account. Working in the II and III quadrant the peripheral implements the following procedure: 1) The firing pulse is set to ”1”on the rising edge of MAIN1. 2) The firing pulse is reset to ”0” after the time Tp fixed by program. 3) The firing pulse is reset to ”0”for a time equal to the fixed masking time. 4) On the falling edge of MAIN2 the firing pulse is set to ”1” 5) The firing pulse is reset to ”0” after the time Tp fixed by program. 6) The firing pulse is reset to ”0”for a time equal to the fixed masking time. Following this approach it is possible to filter electrical noise and oscillations on the signal MAIN1 and MAIN2. It is possible to generatea programmable Interrupt in four different ways: 1) No Interrupt; 2) Interrupt on the rising edge of the signal Tb. 3) Interrupt on the falling edge of the signal Tb. 4) Interrupt on both the edge of the signal Tb. TheInterruptis programmablebyusing the register REG_CONF11(7:6), INTSL (see Table 10.5). (1.5) (1) (0.5) 0.5 1.5 (1.5) (1) (0.5) 0.5 1.5 VA2-A1 Il 180 360 α γ Phase Angle Current Flow Angle L N Loa d Il Figure 10.8. Phase Angle Partialization Mode

10.3 PHASE ANGLE PARTIALIZATION WORK-

When REG_CONF10 (3:2) bits, MODE, are ”11” the peripheral is programmed to work in PHASE ANGLE PARTIALIZATION mode. In this mode T riac is controlled each period of the main voltage. The power transferred to the load is proportional to the CURRENT FLOW ANGLEγ. Thiskind ofTriac controlis suitableto drivethe Triac TCMSK MaskingTime 0000 0 µs 0001 0.5 µs 0010 0.9 µs 0011 1.7 µs 0100 3.3 µs 0101 6.5 µs 0110 12.9 µs 0111 25.7 µs 1000 51.3 µs 1001 102.5 µs 1010 204.9 µs 1011 409.7 µs 1100 819.3 µs 1101 1638.9 µs 1110 3276.9 µs 1111 6553.7 µs ST52T301/E301

Bit Name Value Description

0 TCRST

0 Triac Reset

1 Triac Set

1 TCST

0 Triac Stop

1 Triac Start

01 PWM signal Generator

10 Burst Mode(1)

11 Phase Partialization

00 Clock Master

01 External Clock on MAIN1

51 x Main Voltage Frequency

6 PSF

0 Main Power at 50 Hz

1 Main Power at 60 Hz

7 IOSL

0 MAIN2 Input pin

1 MAIN2 Output pin

Note:(1)CKSL must be set to ”1x” Table 10.4 Configuration Register 10 Description Bit Name Value Description

0 POL

0 Output pulse Polarity =

1 Output pulse Polarity =

1 TCTRS

0 TRIACOUT status = Tristate

1 TRIACOUT status = Enabled

=(2^TCMSK*200 +100) nS. TCMSK=0 → Masking time=0 INTSL

00 No Interrupt source selected

Interrupt on falling edge of the TRIAC/PWM signal, or of the Main Voltage Interrupt on rising edge of the TRIAC/PWM signal, or of the Main Voltage Interrupt on both of edges of the TRIAC/PWM signa,l or of the Main Voltage T able 10.5 Configuration Register 11 Description Bit Name Value Description 0 ÷ 5 UTPMSB Output Impulse Width most significative bits

6 INPSL

0 TRIAC/PWM Input from

1 TRIAC/PWM Input from

7 FZSL

T able 10.6. Configuration Register 12 Description It is possible SET or RESET the TRIAC/PWM Peripheral by using the REG_CONF10(0) bit, TCRST (see Table 10.4). If TRIAC/PWM Peripheral is SET, It is possible ST ART or STOP it, by using the REG_CONF10(1) bit, TCST (see Table 10.4), to start or stop the internal counter without resetting it. It is possibleto enablethe TRIACOUT , byusing the REG_CONF11(0) bit, TCTRS (see Table 10.5 and Figure 10.11). IF TCTRSis 0 the TRIAC/PWM Peripheraloutput is in tristate status. ST52T301/E301

Symbol Parameter Value Unit VDD Supply Voltage -0.5 to 7 V VI Input Voltage VSS -0.3 to VDD +0.3(1) V VO Output Voltage VSS -0.3 to VDD +0.3(1) V VDDA ,VSSA Analog Supply Voltage VSS -0.3 to VDD +0.3(1) V VPP EPROM Programming Voltage 13 V IO Standard Output Source Sink Current(2) ±20 mA TRIACOUT Output Source Sink Current ±80 (3) mA TOPT Operating Temperature 0 to +85 °C TSTG Storage Temperature -65 to +150 °C T able 11.1. Absolute Maximum Ratings Note: Stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 1. Within these limits, clamping diodes are garanteed to be not conductive. 2. All except TRIACOUT pin 3. For not more than 1 sec.

11 ELECTRICAL CHARACTERISTICS

This product contains devices to protect the inputs against damage due to high static voltages, however it is advised to take normal precaution to avoid any voltage higher than maximum rated voltagees. For proper operation it is recommended that V Iand VO must be higher than VSS and smaller than VDD . Reliability is enhanced if unused inputs are connected to an appropriated logic voltage level ST52T301/E301

(VSS or VDD) RECOMMENDED OPERATING CONDITIONS (Operating Condition: VDD =5V±5%-TA=0 °Ct o8 5°C, unless otherwise specified) Symbol Parameters Test Conditions Min Typ Max Unit V DD Operating Supply Voltage 4.75 5.0 5.25 V VPP Programming Voltage 11.4 12 12.6 V V O Ouput Voltage VSS VDD V VDDA ,VSSA Analog Supply Voltage Vss ≤ VSSA <V DDA ≤ VDD VSS V DD V fOSC Oscillator Frequency(1) 5 10 20 MHz T able 11.2. Recommended Operation Condition Notes: 1. For correct behaviour of some peripherals, it is possible to work only with one of the 5 - 10 - 20 MHz frequencies. ST52T301/E301

Symbol Parameter Test Conditions Min Typ Max Unit VIL TTL type Schmitt trig. Low Level Input Voltage VDD =4.75 V see fig.11.6 0.7 V CMOS type Schmitt trig. Low Level Input Voltage VDD =4.75 V see fig.11.7 1.2 V V IH TTL type Schmitt trig. High Level Input Voltage VDD =5.25 V see fig.11.6 2V CMOS type Schmitt trig. High Level Input Voltage VDD =5.25 V see fig.11.7 3.5 V VOL Standard Low Level Output Voltage IOL =4mA 0.4 V TRIACOUT Low Level Output Voltage IOL =50mA 2 V VOH Standard High Level Output Voltage(1) IOL =-4mA V DD -0.5 V TRIACOUT High Level Output Voltage(1) IOL =50mA V DD -2 V VHys TTL type Schmitt trig. Hysteresis Voltagesee fig.11.6 1.2 V CMOS type Schmitt trig. Hysteresis Voltagesee fig.11.7 2.0 V IIL Low Level Leakage Input Current VI=V SS -1 µA IIH High Level Leakage Input Current VI=V DD +4 µA IOL Tri-State Output Leakage Current VO =V SS or VDD ±10 mA IDD Supply Current in RESET mode VPP connected with VDD; VRESET =V SS FOSC = 10 MHz 11 mA Supply Current in RUN mode VPP connected with VDD; FOSC = 10 MHz 11 mA IDDA Analog Supply Current in RESET mode VPP connected with VDD; VRESET =V SS FOSC = 10 MHz 3m A Analog Supply Current in RUN mode VPP connected with VDD; FOSC = 10 MHz 10 mA T able 11.3 DC Electrical Characteristics DC ELECTRICAL CHARACTERISTICS (Operating Condition: VDD =5V±5%-TA=0 °Ct o8 5°C, unless otherwise specified) ST52T301/E301

Symbol Parameter Test Conditions Min Typ Max Unit R S Input protection Resistor All Input Pins 1 kΩ C IN Input Capacitance All Input Pins 10 pF C OUT Output Capacitance All Ouput Pins 10 pF T able 11.4. AC Electrical Characteristics AC ELECTRICAL CHARACTERISTICS (Operating Condition: VDD =5V±5%-TA=0 °Ct o8 5°C, unless otherwise specified) Symbol Parameters Test Conditions Min Typ Max Unit fOSC Oscillator Frequency 20 MHz tCLH Clock High 25 ns tCLL Clock Low 25 ns tSET Setup see fig 11.1 5 ns tHLD Hold see fig.11.1 5 ns tWRESET Minimum Reset Pulse Width 100 ns tWINT Minimum External Interrupt Pulse Width 100 ns tIR Input Rise Time see fig.11.2 15 ns tIF Input Fall Time see fig.11.2 15 ns tOR Output Rise Time C LOA D=10 pF see fig.11.2 10 ns tOF Output Fall CLOAD=10 pF see fig.11.2 10 ns T able 11.5. Timing Parameters Figure 11.1. Data Input Timing Figure 11.2. I/O Rise and Fall Timing ST52T301/E301

Figure 11.6. TTL-level Input Schmitt Trigger Figure 11.7. CMOS-level Input Schmitt Trigger Note: Only for RETE1 and RETEIO signals TIMER CHARACTERISTICS (Operating Condition: VDD =5V±5%-TA=0 °Ct o8 5°C, unless otherwise specified) Symbol Parameter Min Typ Max Unit tRES Resolution 1/FOSC µs fIN External Input Frequency on timer Internal Input Frequency on timer

20 MHz

tW Pulse Width on TIMEROUT pin 1/FOSC µs T able 11.7. Timer Characteristics ST52T301/E301

A/D CONVERTER CHARACTERISTICS (Operating Condition: VDD =5V±5%-TA=0 °Ct o8 5°C, unless otherwise specified) Symbol Parameter Test Conditions Min Typ Max Unit Res Resolution 8b i t ATOT Total Accuracy(1) FOSC > 5 MHz FOSC > 10 MHz FOSC > 20 MHz ±2 LSB tC Conversion Time FOSC =5 - 10 - 20 MHz 32 µs VAN Conversion Range VSSA 2.5 V VZI Zero Scale Voltage Conversion result=

00 Hex VSSA V

VFS Full Scale Voltage (bandgap) Conversion result= FF Hex 2.474 V ΔV FS % Full Scale Voltage (bandgap) precision v/s VDDA variation VDDA=5V ±5% 1% AD I Analog Input Current during Conversion fOSC = 20 MHz 2 µΑ AC IN (2) Analog Input Capacitance 2p F ASI Analog Source Impedance 1 kΩ ORI Output Reference Impedance 100 Ω ORL Output Reference Load 0.1 mA ORLC Analog Reference Load Capacitance 10 pF Source-Off and Drain-Off Leakage Currents are in the range of nA. Notes: 1. Noise at VDDA, VSSA <40 mV 2. Excluding Pad Capacitance. T able 11.8. A/D Converter Characteristics ST52T301/E301

Format: ADD regi, regj Operation: regi <- regi + regj Description:The contents of the Register File j-th register specified as source is added to the destina- tion i-th register, leaving the result in the destination register.The result is 255 if overflow occurs. Flags: Z set if result is zero, cleared otherwise. S set if overflow, cleared otherwise. Bytes: 2 Cycles: 7 Example: If the register 4 contains the value 45 and the register 11 contains the value 15, then the instruction ADD 4,11 1001000 0100|1011 causes the register 4 of the Register File to be loaded with the value 60. If the register 4 contains the value 200 and the register 11 contains the value 100, the in- struction causes the register 4 to be loaded with the value 44 (result-256) and the S flag to be set INSTRUCTION SET ST52T301/E301

Format: AND regi, regj Operation: regi <- regi AND regj Description:The instruction logically ANDs the contents of the Register File j-th register specified as source and the destinationi-th register in the Register File, leaving the result in the desti- nation register. Flags: Z set if result is zero, cleared otherwise. S not affected. Bytes: 2 Cycles: 7 Example: If the register 4 contains the value 10011100 and the register 12 contains the value 01010101, then the instruction AND 4,12 10010001 0100|1100 causes the register 4 of the Register File to be loaded with the value 00010100. ST52T301/E301

Format: CON cost Operation: Dividend Register <- Dividend Register + cost*teta Divisor <- Divisor + teta Description:This intruction computes the values to add in the defuzzification registers, at the end of the single rule. The specified constant is the crisp value representing the output crisp membership function:it is multiplied by the last fuzzy operation result. ST52T301/E301

Format: DATA var mbf lvd vtx rvd Operation: ADM location 16*var+mbf <- lvd ADM location 16*var+mbf+64 <- vtx ADM location 16*var+mbf+128 <- rvd Description:This instruction is a pseudo instruction (it does not correspond to any operation executed by the processor) that allows to store membership functions data in the ADM (Antece- dent Data Memory).The var and the mbf data identify the membership function.The lvd data is the left semibase distance of the M.F ., the vtx data is the position of the vertex and rvd is the right semibase distance. ST52T301/E301

Format: FZAND Operation: K <- stack0 AND stack1 Description:This instruction computes the AND operation between the two values stored in the fuzzy stack, previously loaded with LDP , LDN or LDK instructions, and stores it in the register ST52T301/E301

Format: FZOR Operation: K <- stack0 OR stack1 Description:This instruction computes the OR operation between the two values stored in the fuzzy stack, previously loaded with LDP , LDN or LDK instructions and stores it in the register K. ST52T301/E301

Format: IRQ int label Operation: interrupt vector <- label (PC = Program Counter) Description:This instruction allows to specify the interrupt int service routine start address at label lo- cation. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: IRQ 1 IntRout1 determinates that if interrupt 1 is serviced, the program counter (PC) is loaded with the memory address value labelled with IntRout1. Remark: The instruction IRQ is a dummy instruction used to store data in the chip memory. It is neither stored in memory nor executed.A series of IRQ instructions must be ended by a dummy end operation. ST52T301/E301

Format: IRQM mask Operation: interrupt mask register <- mask Description:The interrupts are masked with the specified mask. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: IRQM 10 1011|1110 00001010 enables the interrupts 1 and 3 and disables all the others. ST52T301/E301

Format: IRQP cost Operation: interrupt priority register <- cost Description:The interrupts priority is set according the specified values. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: IRQP 198 1011|1111 11|00|01|10 determines the interrupt 2 to have highest priority, interrupt 1 medium priority and inter- rupt 0 lower priority. Remark: each couples of bits must have different values, that is interrupts must have different priority level.enables the interrupts 1 and 3 and disables all the others. ST52T301/E301

Format: JP addr Operation: PC <- addr (PC = ProgramCounter) Description:The instruction replaces the PC value with the specified value causing an unconditional jump to another location in the program memory. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: JP 1123 1010|0100 01100011 causes the PC to be loaded with the value 1123 and the program to continue from that location. ST52T301/E301

Format: JPNS addr Operation: if S=0,PC <- addr (PC = Program Counter) Description:If the S flag is cleared then the PC value is replaced with the specified value, causing a jump to another location in the program memory. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the S flag is cleared then the instruction: JPNS 1123 1111|0100 01100011 causes the PC to be loaded with the value 1123 and the program to continue from that location. ST52T301/E301

Format: JPNZ addr Operation: if Z=0, PC <- addr (PC = Program Counter) Description:If the Z flag is cleared then the PC value is replaced with the specified value, causing a jump to another location in the program memory. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the Z flag is cleared then the instruction: JPNZ 1123 1101|0100 01100011 causes the PC to be loaded with the value 1123 and the program to continue from that location. ST52T301/E301

Format: JPS addr Operation: if S=1,PC <- addr (PC = Program Counter) Description:If the S flag is set then the PC value is replaced with the specified value, causing a jump to another location in the program memory. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the S flag is set then the instruction: JPS 1123 1110|0100 01100011 causes the PC to be loaded with the value 1123 and the program to continue from that location. ST52T301/E301

Format: JPZ addr Operation: if Z=1, PC <- addr (PC = Program Counter) Description:If the Z flag is set then the PC value is replaced with the specified value, causing a jump to another location in the program memory. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the Z flag is set then the instruction: JPZ 1123 1110|0100 01100011 causes the PC to be loaded with the value 1123 and the program to continue from that location. ST52T301/E301

Load Constant into Configuration Register Format: LDCF conf, const Operation: conf <- const Description:The immediate constant value (const) specified as source is loaded into the destination peripheral configuration register (conf). Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: LDCF 5,43 1011|0101 00101011 causes the peripheral configuration register 5 to be loaded with the value 43. ST52T301/E301

Load Stack with K register Format: LDK Operation: stack0 <- K Description:This instruction loads in the stack the value temporarily stored in the register K that is the result of the last fuzzy operation. ST52T301/E301

Load Stack with M register Format: LDM Operation: stack0 <- M Description:This instruction loads in the stack the value temporarily stored in the register M with a SKM operation. ST52T301/E301

Format: LDN var mbf Operation: stack <- 15 - computed alpha value related to mbf M.F .of var Variable Description:This instruction performs the fuzzyfication and loads in the stack the negated alpha value of the M.F .mbf of var Variable. ST52T301/E301

Format: LDP var mbf Operation: stack <- computed alpha value related to mbf M.F . of var Variable Description:This instruction performs the fuzzyfication and loads in the stack the alpha value of the M.F . mbf of var Variable. ST52T301/E301

Load Register into Peripheral Register Format: LDPR per, reg Operation: per <- reg Description:The contents register specified as source (reg) is loaded into the destinationperipheral register (per). Flags: Z, S not affected. Bytes: 1 Cycles: 5 (6 if parallel port with H/S is addressed) Example: If the register 7 of the Register File contains the value 25 then the instruction: LDPR 2,7 01|10|0111 causes the register 2 of the Peripheral Register (i.e. parallel port) to be loaded with the value 25. ST52T301/E301

Load constant into Register Format: LDRC reg, const Operation: reg <- const Description:The immediate constant value specified as source is loaded into the destination register in the Register File. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: The instruction: LDRC 5,43 1000|0101 00101011 causes the register 5 of the Register File to be loaded with the value 43. ST52T301/E301

Load Input register into Register file Format: LDRI reg, inp Operation: reg <- inp Description:The contents of a input register specified as source (inp) is loaded into the destination register in the Register File (reg). Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the register 2 of the A/D converter contains the value 25 then the instruction: LDRI 5,2 000|xxxxx 0101|0010 x = don’t care causes the register 5 of the Register file to be loaded with the value 25. ST52T301/E301

Load Register into Register Format: LDRR regi, regj Operation: regj <- regi Description:The contents of the Register File j-th register specified as source is loaded into the desti- nation i-th register. Flags: Z,S not affected. Bytes: 2 Cycles: 6 Example: If the register 2 of the Register File contains the value 25 then the instruction: LDRR 5,2 100101100101|0010 causes the register 5 of the Register file to be loaded with the value 25. ST52T301/E301

Macro Disable Global Interrupt Format: MDGI Operation: MGI bit <- 0 Description:All the interrupts are disabledby this instruction.This instruction is used by FUZZYSTU- DIO 3.0 Compiler macros to disable interrupt during macro execution. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: After the instruction: MDGI 10011010 all the interrupts cannot be acknowledged and remain pending ST52T301/E301

Macro Enable Global Interrupt Format: MDGI Operation: MGI bit <- 1 Description:The not masked interrupts are enabledby this instruction only if a UDGI instruction has not specified before, not followed by a UEGI instruction. This instruction is used by FUZZYSTUDIO  3.0 Compiler macros to disable interrupt during macro execution. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: After the instruction: MEGI 10011011 not masked interrupts can be acknowledged if the interrupts are not globally disabled by the UDGI instruction ST52T301/E301

Format: OUT const Operation: Output Register const <- defuzzyfication result of the const output Description:This instruction performs the defuzzyfication of the specified output (const can assume only the values 0 or 1) and loads in the correspondent Fuzzy Output Register the result. ST52T301/E301

Format: RETI Operation: PC <- stack Z <- stack S <- stack Description:This instruction resumes the program execution exactly at the point it was left when an in- terrupt occurred.Z and S flag are set to the status they had when the interrupt service routine was started. Flags: Z,S restored to the original setting before an interrupt occured. Bytes: 1 Cycles: 5 Example: If the PC stack contains the value 1123 and the program is processing an interrupt ser- vice routine, then the instruction RETI 10010101 causes the PC to be loaded with the value 1123 and the flags to be restored to the status before the interrupt occurred. ST52T301/E301

Format: RINT int Operation: cancel pending interrupt n. int Description:The specified pending interrupt is cancelled if not currently in service. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: The instruction: RINT 2 0001|x|010 x = don’t care causes the bit 2 of the interrupt pending register to be cleared so that the interrupt 2 is not acknowledged. Remark: The use of RINT istruction has no effect if a specifiedinterrupt has already been aknowl- edged and related service routine has not been completed. ST52T301/E301

Store K register in M register Format: SKM Operation: M< -K Description:This instruction stores the result of the last performed fuzzy operation (stored in the tem- porary register K) in the temporary buffer M. ST52T301/E301

Format: SRX regi Operation: regi <- SCDR_RX Description:The contents of the SCDR_RX block of the SCI receiver block, is transferred in the Reg- ister File i-th register specified as destination. Flags: Z,S not affected. Bytes: 2 Cycles: 5 Example: If the SCDR_RX block of the SCI receiver block contains the value 45, then the instruc- tion SRX 4 00101101 causes the register 4 of the Register File to be loaded with the value 45. ST52T301/E301

Format: STOP Operation: Stop section Description:This instruction separates arithmetic instructions and fuzzy instructions.Also it ends a IRQ specification section. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: The instruction: STOP 10010111 if put after arithmetic instructions, it allows to start a block of fuzzy instruction and vice versa. ST52T301/E301

Format: STX regi Operation: SCDR_TX <- regi Description:The contents of the Register File i-th register specified as source is transferred in the SCDR_TX block of the SCI transmitter block, to be transmitted. Flags: Z,S not affected. Bytes: 2 Cycles: 5 Example: If the register 4 contains the value 45, then the instruction STX 4 00101101 causes the serial transmission of 45. ST52T301/E301

Format: SUB regi, regj Operation: regi <- regi -regj Description:The contents of the Register File j-th register specified as source is subtractedfrom the destination i-th register, leaving the result in the destinationregister. Flags: Z set if result is zero, cleared otherwise. S set if underflow, cleared otherwise. Bytes: 2 Cycles: 7 Example: If the register 4 contains the value 45 and the register 11 contains the value 15, then the instruction SUB 4,11 10010010 0100|1011 causes the register 4 of the Register File to be loaded with the value 30. If the register 4 contains the value 100 and the register 11 contains the value 200, the in- struction causes the register 4 to be loaded with the value 156 (result+256) and the S flag to be set. ST52T301/E301

Format: SUBO regi, regj Operation: regi <- regi - regj +128 Description: The contents of the Register File register specified as source are subtracted from the destination register in the Register File, the value 128 is added to the result that is stored in the destination register.This operation allows the use of the signed byte considering the values between 0 and 127 as negative,128 as 0, and the values between 129 and 255 as positive. Flags: Z set if result is zero or if overflow occurs, cleared otherwise. S set if underflow or overflow, cleared otherwise. Bytes: 2 Cycles: 7 Example: If the register 4 contains the value 45 and the register 11 contains the value 15, then the instruction SUBO 4,11 10010011 0100|1011 causes the register 4 of the Register File to be loaded with the value 158. The value 45 corresponds to -83, the value 11 corresponds to -113; so the operation is equivalent to perform -83 - (-113) = 30. As a matter of fact the result 158 corresponds to the value 30. If the register 4 contains the value 50 and the register 11 contains the value 200, the in- struction causes the register 4 to be loaded with the value 234 (result+256) and the S flag to be set. If the register 4 contains the value 200 and the register 11 contains the value 50, the in- struction causes the register 4 to be loaded with the value 22 (result-256) and the S and Z flags to be set. ST52T301/E301

User Disable Global Interrupt Format: UDGI Operation: UGI bit <- 0 Description:All the interrupt are disabled by this instruction. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: After the instruction: UDGI 10011000 all the interrupts cannot be acknowledged and remain pending. ST52T301/E301

User Enable Global Interrupt Format: UEGI Operation: UGI bit <- 1 Description:All the interrupts are enabledby this instruction. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: After the instruction: UEGI 10011001 not masked interrupts can be acknowledged if the interrupt are not globally disabled by the MDGI instruction. ST52T301/E301

Format: WAITI Operation: Wait state Description:This instruction causes the program to stop, without halting the peripherals, until an inter- rupt occurs.. Flags: Z,S not affected. Bytes: 1 Cycles: 4 Example: The instruction: WAITI 10010100 halts the program execution leaving the peripherals running on, until an interrupt occurs. ST52T301/E301

DIM mm inch. MIN TYP MAX MIN TYP MAX A 17.27 17.78 .680 .662 B 16.33 16.81 .643 .662 C 12.01 .475 C1 13.03 .513 c1 1.30 0.52 D 1.82 2.23 0.72 .088 d1 0.889 .035 d2 2.362 .093 E 16.26 16.76 .640 .660 e 1.27 .050 e3 12.50 .500 F 0.431 .017 F1 0.762 .030 F2 0.965 .038 M 0.508 .020 M1 1.016 .040 R 0.762 .030 CLCC44 PACKAGE MECHANICAL DA T A ST52T301/E301

DIM mm inch. MIN TYP MAX MIN TYP MAX A 17.4 17.65 0.685 0.695 B 16.51 16.65 0.650 0.656 C 3.65 3.7 0.144 1.146 D 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 E 14.99 16 0.590 0.630 e 1.27 0.050 e3 1.27 0.500 F 0.46 0.018 F1 0.71 0.028 G 0.101 0.004 M 1.16 0.046 M1 1.14 0.045 PLCC44 PACKAGE MECHANICAL DA T A ST52T301/E301

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