ST5090TQFP

ST5090 STMICROELECTRONICS | Alldatasheet

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LOW VOLTAGE 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END FEATURES: Complete CODEC and FILTER system including:

14 BIT LINEAR ANALOG TO DIGITAL AND

DIGITAL TO ANALOG CONVERTERS.

8 BIT COMPANDED ANALOG TO DIGITAL

AND DIGITAL TO ANALOG CONVERTERS A-LAW OR µ-LAW. TRANSMIT AND RECEIVE BAND-PASS FILTERS ACTIVE ANTIALIAS NOISE FILTER. Phone Features: THREE SWITCHABLE MICROPHONE AM- PLIFIER INPUTS. GAIN PROGRAMMABLE: 20 dB PREAMP. (+MUTE), 0 . . 22.5 dB AM- PLIFIER, 1.5 dB STEPS. EARPIECE AUDIO OUTPUT. ATTENUATION PROGRAMMABLE: 0 . . 30 dB, 2 dB STEPS. EXTERNAL AUDIO OUTPUT. ATTENUATION PROGRAMMABLE: 0 . . 30 dB, 2 dB STEPS. TRANSIENT SUPRESSION SIGNAL DURING POWER ON AND DURING AMPLIFIER SWITCHING. INTERNAL PROGRAMMABLE SIDETONE CIRCUIT. ATTENUATION PROGRAMMABLE: 16 dB RANGE, 1 dB STEP. ROUTING POSSI- BLE TO BOTH OUTPUTS. INTERNAL RING OR TONE GENERATOR IN- CLUDING DTMF TONES, SINEWAVE OR SQUAREWAVE WAVEFORMS. ATTENU- ATION PROGRAMMABLE: 27dB RANGE, 3dB STEP. THREE FREQUENCY RANGES: PROGRAMMABLE PULSE WIDTH MODU- LATED BUZZER DRIVER OUTPUT. General Features: SINGLE 3.3V ±10% OR 5V ±10% SUPPLY SELECTABLE. EXTENDED TEMPERATURE RANGE OPERA- TION (*) -40°Ct o8 5°C. 1.5µW STANDBY POWER (TYP. AT 3V). 21 mW OPERATING POWER (TYP. AT 3V). CMOS COMPATIBLE DIGITAL INTERFACES. PROGRAMMABLE PCM AND CONTROL IN- TERFACE MICROWIRE COMPATIBLE. APPLICATIONS: GSM DIGITAL CELLULAR TELEPHONES. CT2 DIGITAL CORDLESS TELEPHONES. DECT DIGITAL CORDLESS TELEPHONES. BATTERY OPERATED AUDIO FRONT-ENDS FOR DSPs. (*)Functionality guaranteed in the range – 40°C to +85°C; Timing and Electrical Specifications are guaranteed in the range –3 0°C to +85°C. GENERAL DESCRIPTION ST5090 is a high performancelow power combined PCM CODEC/FILTER device tailored to implement the audio front-end functions required by the next generation low voltage/low power consumption digital terminals. ST5090 offers a number of programmable func- tions accessed through a serial control channel that easily interfaces to any classical microcontroller. The PCM interfacesupports both non-delayed(nor- mal and reverse) and delayed frame synchroniza- tion modes. ST5090 can be configurated either as a 14-bit lin- ear or as an 8-bit compandedPCM coder. Additionally to the CODEC/FILTER function, ST5090 includes a Tone/Ring/DTMF generator, a sidetone generation,and a buzzer driver output. ST5090 fulfills and exceeds D3/D4 and CCITT rec- ommendations and ETSI requirements for digital handsetterminals. Main applications include digital mobile phones, as cellular and cordless phones, or any battery pow- ered equipment that requires audio codecs operat- ing at low single supply voltages This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. February 1996 TQFP44(10x10x1.4) SO28 ORDERING NUMBERS: Package Dim. Cond. ST5090AD ST5090ADTR ST5090TQFP ST5090TQFPTR SO28 SO28 TQFP44 TQFP44 10x10x1.4 10x10x1.4 Tube Tape&Reel Tray 8x20 Tape&Reel

VS & TE MIC PREAMP 20dB + MUTE MIC AMP 0 -> 22.5 1.5dB STEP DE (A) (B) PREFILTER & BANDPASS FILTER PCM ADC BANDPASS FILTER PCM DAC TRANSMIT REGISTER RECEIVE REGISTER 12dB 12dB OE TONE, RING & DTMF GENER. & FILTER EARA OUTPUT 0 -> -30dB, 2dB STEP EXTA OUTPUT RTE SE SI TONE AMP 0 -> -27dB 3dB STEP SIDETONE AMP -12.5 -> -27.5dB 1dB STEP CONTROL INTERFACE µ-WIRE CLOCK GENERATOR & SYNCHRONIZER INTERFACE LATCH BUZZER DRIVERBE EN EN GNDP GNDA GND VCCA VCC VCCP LEVEL ADJUST (PWM) MIC3- MIC2- MIC1- MIC2+ MIC1+ MIC3+ VFr+ VFr- VLr- VLr+ DX CO DR CI CS- CCLK FS MCLK LO BZ D93 TL074 BLOCK DIAGRAM PIN CONNECTIONS (Top view) N.C. VCCA VCCP N.C. VFr- VLr- VFr+ VLr+ GNDP MCLK LO MIC2- MIC1- MIC2+ MIC1+ GNDA MIC3- MIC3+1 D R FS D94TL094 CCLK CS- CI CO D x GND11 1514BZ V CC 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 VLr+ VLr- N.C. VFr- N.C. VFr+ N.C. DR N.C. N.C. GNDP N.C. N.C. CCLK CS- BZ CI VCC CO DX GND N.C. N.C. N.C. VCCP VCCA N.C. N.C. MIC3+ MIC3- GNDA N.C. MIC1+ N.C. N.C. LO FS N.C. MCLK MIC1- N.C. MIC2+ N.C. MIC2- D94TL095 12 13 14 15 16 TQFP44SO28 ST5090

PIN FUNCTIONS (SO28) Pin Name Description 1 N.C. Not Connected. 2V CCA Positive power supply input for the analog section. +5V ±10% or 3.3V±10% selectable. VCC and V CCA must be directly connected together. 3V CCP Positive power supply input for the power section. 5V±10% or 3.3V±10% selectable VCCP and VCC must be connected together. 4 N.C. Not Connected. 5,6 V Fr+,VFr– Receive analog earpiece amplifier complementary outputs. These outputs can drive directly earpiece transductor. The signal at this output can be the sum of: - Receive Speech signal from DR , - Internal Tone Generator, - Sidetone signal. 7,8 V Lr+,VLr– Receive analog extra amplifier complementary outputs. The signal at these outputs can be the sum of: - Receive Speech signal from DR , - Internal Tone generator, - Sidetone signal. 9 GNDP Power ground. V Fr and VLrdriver are referenced to this pin. GNDP and GND must be connected together close to the device. 10 D R Receive data input: Data is shifted in during the assigned Received time slots In delayed and non- delayed normal frame synchr. modes voice data byte is shifted in at the MCLK frequency on the falling edges of MCLK, while in non-delayed reverse frame synchr. mode voice data byte is shifted in at the MCLK frequency on the rising edges of MCLK. 11 CCLK Control Clock input: This clock shifts serial control information into CI and out from CO when the CS- input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. 12 CS- Chip Select input: When this pin is low, control information is written into and out from the ST5090 via CI and CO pins. 13 CI Control data Input: Serial Control information is shifted into the ST5090 on this pin when CS- is low on the rising edges of CCLK. 14 BZ Pulse width modulated buzzer driver output. 15 V CC Positive power supply input for the digital section. +5V±10% or 3.3V±10% selectable.

16 CO Control data Output: Serial control/status information is shifted out from the ST5090 on this pin

when CS- is low on the falling edges of CCLK. 17 D X Transmit Data ouput: Data is shifted out on this pin during the assigned transmit time slots. Elsewhere DX output is in the high impedance state. In delayed and non-delayed normal frame synchr. modes, voice data byte is shifted out from TRISTATE output DX at the MCLK on the rising edge of MCLK, while in non-delayed reverse frame synchr mode voice data byte is shifted out on the falling edge of MCLK. 18 GND Ground: All digital signals are referenced to this pin.

19 FS Frame Sync input: This signal is a 8kHz clock which defines the start of the transmit and receive

frames. Any of three formats may be used for this signal: non delayed normal mode, delayed mode, and non delayed reverse mode. 20 MCLK Master Clock Input: This signal is used by the switched capacitor filters and the encoder/decoder sequencing logic. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of Control Register CRO. MCLK is used also to shift-in and out data.

21 LO A logic 1 written into DO (CR1) appears at LO pin as a logic 0

A logic 0 written into DO (CR1) appears at LO pin as a logic 1. 22 MIC2- Second negative high impedance input to transmit pre-amplifier for microphone connection. 23 MIC2+ Second Positive high impedance input to transmit pre-amplifier for microphone connection. 24 MIC1- Negative high impedance input to transmit pre-amplifier for microphone connection. 25 MIC1+ Positive high impedance input to transmit pre-amplifier for microphone connection. 26 GNDA Analog Ground: All analog signals are referenced to this pin. GND and GNDA must be connected together close to the device. 27 MIC3- Third negative high impedance output to transmit preamplifier for microphone connection. 28 MIC3+ Third positive high impedance output to transmit preamplifier for microphone connection. ST5090

PIN FUNCTIONS (TQFP44) Pin Name Description 1 N.C. Not Connected. 2,3 V Fr+,VFr– Receive analog earpiece amplifier complementary outputs. These outputs can drive directly earpiece transductor. The signal at this output can be the summ of: - Receive Speech signal from DR , - Internal Tone Generator, - Sidetone signal. 4 N.C. Not Connected. 5,6 V Lr+,VLr– Receive analog extra amplifier complementary outputs. The signal at these outputs can be the sum of: - Receive Speech signal from DR, - Internal Tone generator, - Sidetone signal. 7 N.C. Not Connected. 8 GNDP Power ground. V Fr and VLrdriver are referenced to this pin. GNDP and GND must be connected together close to the device. 9 N.C. Not Connected. 10 D R Receive data input: Data is shifted in during the assigned Received time slots In delayed and non- delayed normal frame synchr. modes voice data byte is shifted in at the MCLK frequency on the falling edges of MCLK, while in non-delayed reverse frame sinchr. mode voice data byte is shifted in at the MCLK frequency on the rising edges of MCLK. 11,12,13 N.C. Not Connected. 14 CCLK Control Clock input: This clock shifts serial control information into CI and out from CO when the CS- input is low, depending on the current instruction. CCLK may be asynchronous with the other system clocks. 15 CS- Chip Select input: When this pin is low, control information is written into and out from the ST5090 via CI and CO pins. 16 CI Control data Input: Serial Control information is shifted into the ST5090 on this pin when CS- is low on the rising edges of CCLK. 17 BZ Pulse width modulated buzzer driver output. 18 V CC Positive power supply input for the digital section. +5V±10% or 3.3V±10% selectable.

19 CO Control data Output: Serial control/status information is shifted out from the ST5090 on this pin

when CS- is low on the falling edges of CCLK. 20 D X Transmit Data ouput: Data is shifted out on this pin during the assigned transmit time slots. Elsewhere D X output is in the high impendance state. In delayed and non-delayed normal frame synchr. modes, voice data byte is shifted out from TRISTATE output DX atthe MCLK on the rising edge of MCLK, while in non-delayed reverse frame synchr mode voice data byte is shifted out on the falling edge of MCLK. 21 GND Ground: All digital signals are referenced to this pin. 22,23 N.C. Not Connected.

24 FS Frame Sync input: This signal is a 8kHz clock which defines the start of the transmit and receive

frames. Either of three formats may be used for this signal: non delayed normal mode, delayed mode, and non delayed reverse mode. 25 MCLK Master Clock Input: This signal is used by the switched capacitor filters and the encoder/decoder sequencing logic. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by means of Control Register CRO. MCLK is used also to shift-in and out data.

26 LO A logic 1 written into DO (CR1) appears at LO pin as a logic 0

A logic 0 written into DO (CR1) appears at LO pin as a logic 1. 27,28,29 N.C. Not Connected. 30 MIC2- Second negative high impedance input to transmit pre-amplifier for microphone connection. 31 MIC2+ Second Positive high impedance input to transmit pre-amplifier for microphone connection. 32 N.C. Not Connected. 33 MIC1- Negative high impedance input to transmit pre-amplifier for microphone connection. 34 MIC1+ Positive high impedance input to transmit pre-amplifier for microphone connection. 35 N.C. Not Connected. 36 GNDA Analog Ground: All analog signals are referenced to this pin. GND and GNDA must be connected together close to the device. 37 MIC3- Third negative high impedance output to transmit preamplifier for microphone connection. 38 MIC3+ Third positive high impedance output to transmit preamplifier for microphone connection. 39,40 N.C. Not Connected. 41 V CCA Positive power supply input for the analog section. +5V ±10% or 3.3V±10% selectable. VCC and V CCA must be directly connected together. 42 V CCP Positive power supply input for the power section. 5V±10% or 3.3V±10% selectable VCCP and VCC must be connected together. 43,44 N.C. Not Connected. ST5090

I.1Power on initialization: When power is first applied, power on reset cir- cuitry initializes ST5090 and puts it into the power down state. Gain Control Registers for the various programmable gain amplifiers and programmable switches are initialized as indicated in the Control Register description section. All CODEC functions are disabled. The desired selection for all programmable func- tions may be intialized prior to a power up com- mand using the MICROWIRE control channel. I.2Power up/down control: Following power-on initialization, power up and power down control may be accomplished by writ- ing any of the control instructions listed in Table 1 into ST5090 with ”P” bit set to 0 for power up or 1 for power down. Normally, it is recommended that all programma- ble functions be initially programmed while the device is powered down. Power state control can then be included with the last programming in- struction or in a separate single byte instruction. Any of the programmable registers may also be modified while ST5090 is powered up or down by setting ”P” bit as indicated. When power up or down control is entered as a single byte instruc- tion, bit 1 must be set to a 0. When a power up command is given, all de-acti- vated circuits are activated, but output D X will re- main in the high impedance state until the second Fs pulse after power up. I.3Power down state: Following a period of activity, power down state may be reentered by writing a power down in- struction. Control Registers remain in their current state and can be changed by MICROWIRE control inter- face. In addition to the power down instruction, detec- tion of loss MCLK (no transition detected) auto- matically enters the device in ”reset” power down state with D X output in the high impedance state. I.4Transmit section: Transmit analog interface is designed in two stages to enable gains up to 42.5 dB to be real- ized. Stage 1 is a low noise differential amplifier providing 20 dB gain. A microphone may be ca- pacitevely connected to MIC1+, MIC1- inputs, while the MIC2+ MIC2– and MIC3+ MIC3- inputs may be used to capacitively connect a second mi- crophone or a third microphone respectively or an auxiliary audio circuit. MIC1 or MIC2 or MC3 or transmit mute is selected with bits 6 and 7 of reg- ister CR4. In the mute case, the analog transmit signal is grounded and the sidetone path is also disabled. Following the first stage is a programmable gain amplifier which provides from 0 to 22.5 dB of ad- ditional gain in 1.5dB step. The total transmit gain should be adjusted so that, at reference point A, see Block Diagram description, the internal 0 dBm0 voltage is 0.49 Vrms (overload level is 0.7 Vrms). Second stage amplifier gain can be pro- grammed with bits 4 to 7 of CR5. An active RC prefilter then precedes the 8th order band pass switched capacitor filter. A/D converter can be either a 14-bit linear (bit CM = 0 in register CR0) or can have a compressing characteristics (bit CM = 1 in register CR0) according to CCITT A or MU255 coding laws. A precision on chip volt- age reference ensures accurate and highly stable transmission levels. Any offset voltage arising in the gain-set amplifier, the filters or the comparator is cancelled by an in- ternal autozero circuit. Each encode cycle begins immediatly at the be- ginning of the selected Transmit time slot. The to- tal signal delay referenced to the start of the time slot is approximatively 195µs (due to the transmit filter) plus 125µs (due to encoding delay), which totals 320µs. Voice data is shifted out on D X dur- ing the selected time slot on the transmit rising edges of MCLK in delayed or non-delayed normal mode or on the falling edges of MCLK in non-de- layed reverse mode. I.5Receive section: Voice Data is shifted into the decoder’s Receive voice data Register via the D R pin during the se- lected time slot on the falling edges of MCLK in delayed or non-delayed normal mode or on the rising edges of MCLK in non-delayed reverse mode. The decoder consists of either a 14-bit linear or an expanding DAC with A or MU255 law decod- ing characteristic. Following the Decoder is a

3400 Hz 8th order band-pass switched capacitor

filter with integral Sin X/X correction for the 8 kHz sample and hold. 0 dBmO voltage at this (B) reference point (see Block Diagram description) is 0.49 Vrms. A tran- scient suppressing circuitry ensure interference noise suppression at power up. The analog speech signal output can be routed either to earpiece (V FR+ ,VFR- outputs) or to an ex- tra analog output (VLr+,V Lr- outputs) by setting bits OE and SE (1 and 0 of CR4). Total signal delay is approximatively 190µs (filter plus decoding delay) plus 62.5µs (1/2 frame) which gives approximatively 252µs. Differential outputs VFR+ ,VFR- are intended to di- rectly drive an earpiece. Preceding the outputs is a programmable attenuationamplifier, which must ST5090

be set by writing to bits 4 to 7 in register CR6. At- tenuations in the range 0 to -30 dB relative to the maximum level in 2 dB step can be programmed. The input of this programmable amplifier is the sum of several signals which can be selected by writing to register CR4.: - Receive speech signal which has been de- coded and filtered, - Internally generated tone signal, (Tone ampli- tude is programmed with bits 4 to 7 of register CR7), - Sidetone signal, the amplitude of which is pro- grammed with bits 0 to 3 of register CR5 V FR+ and VFR- outputs are capable of driving output power level up to 66mW into differentially con- nected load impedance of 30Ω . Piezoceramic re- ceivers up to 50nF can also be driven. Differential outputs VLr+,VLr- are intended to di- rectly drive an extra output. Preceding the outputs is a programmable attenuation amplifier, which must be set by writing to bits 0 to 3 in register CR6. Attenuations in the range 0 to -30 dB rela- tive to the maximum level in 2.0 dB step can be programmed. The input of this programmable am- plifier can be the sum of signals which can be se- lected by writing to register CR4: - Receive speech signal which has been de- coded and filtered, - Internally generated tone signal, (Tone ampli- tude is programmed with bits 4 to 7 of register CR7), - Sidetone signal, the amplitude of which is pro- grammed with bits 0 to 3 of register CR5. V Lr+ and VLr-outputs are capable of driving output power level up to 66mW into differentially con- nected load impedance of 30Ω . Piezoceramic re- ceivers up to 50nF can also be driven. BUZZER OUTPUT: Single ended output BZ is intended to drive a buzzer, via an external BJT, with a squarewave pulse width modulated (PWM) signal the fre- quency of which is stored into register CR8. For some applications it is also possible to ampli- tude modulate this PWM signal with a square- wave signal having a frequency stored in register CR9. Maximum load for BZ is 5kΩ and 50pF. I.6Digital Interface(Fig. 1) FS Frame Sync input determines the beginning of frame. It may have any duration from a single cy- cle of MCLK to a squarewave. Three different re- lationships may be established between the Frame Sync input and the first time slot of frame by setting bits DM1 and DM0 in register CR1. Non delayed data mode is similar to long frame timing on ST5080A: first time slot begins nomi- nally coincident with the rising edge of F S. Alter- native is to use delayed data mode, which is simi- lar to short frame sync timing on ST5080A, in which FS input must be high at least a half cycle of MCLK earlier the frame beginning. In the case of companded code only (bit CM = 1 in register CRO) a time slot assignment circuit on chip may be used with all timing modes, allowing connec- tion to one of the two B1 and B2 voice data chan- nels. Two data formats are available: in Format 1, time slot B1 corresponds to the 8 MCLK cycles follow- ing immediately the rising edge of FS, while time slot B2 corresponds to the 8 MCLK cycles follow- ing immediately time slot B1. In Format 2, time slot B1 is identical to Format 1. Time slot B2 appears two bit slots after time slot B1. This two bits space is left available for inser- tion of the D channel data. Data format is selected by bit FF (2) in register CR0. Time slot B1 or B2 is selected by bit TS (1) in Control Register CR1. Bit EN (2) in control register CR1 enables or dis- ables the voice data transfer on D X and DR as appropriate. During the assigned time slot, DX output shifts data out from the voice data register on the rising edges of MCLK in the case of de- layed and non-delayed normal modes or on the falling edges of MCLK in the case of non-delayed reverse mode. Serial voice data is shifted into D R input during the same time slot on the falling edges of MCLK in the case of delayed and non- delayed normal modes or on the rising edges of MCLK in the case of non-delayed reverse mode. D X is in the high impedance Tristate condition when in the non selected time slots. I.7Control Interface: Control information or data is written into or read- back from ST5090 via the serial control port con- sisting of control clock CCLK, serial data input CI and output CO, and Chip Select input, CS-. All control instructions require 2 bytes as listed in Ta- ble 1, with the exception of a single byte power- up/down command. To shift control data into ST5090, CCLK must be pulsed high 8 times while CS- is low. Data on CI input is shifted into the serial input register on the rising edge of each CCLK pulse. After all data is shifted in, the content of the input shift register is decoded, and may indicate that a 2nd byte of control data will follow. This second byte may either be defined by a second byte-wide CS- pulse or may follow the first contiguously, i.e. it is not mandatory for CS- to return high in between the first and second control bytes. At the end of the 2nd control byte, data is loaded into the ap- ST5090

propriate programmable register. CS- must return high at the end of the 2nd byte. To read-back status information from ST5090, the first byte of the appropriate instruction is strobed in during the first CS- pulse, as defined in Table 1. CS- must be set low for a further 8 CCLK cy- cles, during which data is shifted out of the CO pin on the falling edges of CCLK. When CS- is high, CO pin is in the high imped- ance Tri-state, enabling CO pins of several de- vices to be multiplexed together. Thus, to summarise, 2 byte READ and WRITE in- structions may use either two 8-bit wide CS- pulses or a single 16 bit wide CS- pulse. I.8Control channel access to PCM interface: It is possible to access the B channel previously selected in Register CR1 in the case of com- panded code only. A byte written into Control Register CR3 will be automatically transmitted from D X output in the following frame in place of the transmit PCM data. A byte written into Control Register CR2 will be automatically sent through the receive path to the Receive amplifiers. In order to implement a continuous data flow from the Control MICROWIRE interface to a B chan- nel, it is necessary to send the control byte on each PCM frame. A current byte received on D R input can be read in the register CR2. In order to implement a con- tinuous data flow from a B channel to MI- CROWIRE interface, it is necessary to read regis- ter CR2 at each PCM frame. (non delayed timing) (delayed timing)F5 XB2B1 XX B2B1 MCLK DR DX FORMAT 1 (non delayed timing) (delayed timing)F8 XB 2B1 XX B2B1 MCLK DR DX FORMAT 2 D93TL075 Figure 1:Digital Interface Format (*) (*) Significant Only For Companded Code. ST5090

For both formats of Digital Interface, programma- ble functions are configured by writing to a num- ber of registers using a 2-byte write cycle. Most of these registers can also be read-back for verification. Byte one is always register address, while byte two is Data. Table 1 lists the register set and their respective adresses. Table 1:Programmable Register Intructions Function Address byte Data byte 76543210 Single byte Power up/down P X X X X X 0 X none Write CR0 P 000001X s e e C R 0 TABLE 2 Read-back CR0 P 0 0 0 0 1 1 X see CR0 Write CR1 P 000101X s e e C R 1 TABLE 3 Read-back CR1 P 0 0 0 1 1 1 X see CR1 Write Data to receive path P 001001X s e e C R 2 TABLE 4 Read data from D R P001011X s e e C R 2 Write Data to DX P001101X s e e C R 3 TABLE 5 Write CR4 P 010001X s e e C R 4 TABLE 6 Read-back CR4 P 0 1 0 0 1 1 X see CR4 Write CR5 P 010101X s e e C R 5 TABLE 7 Read-back CR5 P 0 1 0 1 1 1 X see CR5 Write CR6 P 011001X s e e C R 6 TABLE 8 Read-back CR6 P 0 1 1 0 1 1 X see CR6 Write CR7 P 011101X s e e C R 7 TABLE 9 Read-back CR7 P 0 1 1 1 1 1 X see CR7 Write CR8 P 100001X s e e C R 8 TABLE 10 Read-back CR8 P 1 0 0 0 1 1 X see CR8 Write CR9 P 100101X s e e C R 9 TABLE 11 Read-back CR9 P 1 0 0 1 1 1 X see CR9 Write CR10 P 101001X s e e CR10 TABLE 12 Read-back CR10 P 1 0 1 0 1 1 X see CR10 Write CR11 P 101101X s e e CR11 TABLE 13 Read-back CR11 P 1 0 1 1 1 1 X see CR11 Write Test Register CR14 P 111001X reserved NOTE 1: bit 7 of the address byte and data byte is always the first bit clocked into or out from: CI and CO pins when MICROWIRE serial port is enabled. X = reserved: write 0 NOTE 2: ”P” bit is Power up/down Control bit. P = 1 Means Power Down. Bit 1 indicates, if set, the presence of a second byte. NOTE 3: Bit 2 is write/read select bit. NOTE 4: Registers CR12, CR13, and CR15 are not accessible. ST5090

Table 2:Control Register CR0 Functions

76543210 Function

MCLK = 512 kHz MCLK = 1.536 MHz MCLK = 2.048 MHz MCLK = 2.560 MHz Linear code Companded code Linear Code Companded Code 2-complement * sign and magnitude 2-complement 1-complement MU-law: CCITT D3-D4 * MU-law: Bare Coding A-law including even bit inversion A-law: Bare Coding B1 and B2 consecutive B1 and B2 separated * (1) (1) 8 bits time-slot 7 bits time-slot * (1) (1) Normal operation Digital Loop-back *: state at power on initialization (1): significant in companded mode only Table 3:Control Register CR1 Functions X delayed data timing non-delayed normal data timing non-delayed reverse data timing L0 latch set to 1 L0 latch set to 0 D R connected to rec. path CR2 connected to rec. path (1) Trans path connected to DX CR3 connected to DX (1) voice data transfer disable voice data transfer enable B1 channel selected B2 channel selected * (1) (1) 3.3V power supply 5.0V power supply *: state at power on initialization (1): significant in companded mode only ST5090

Table 4:Control Register CR2 Functions msb lsb Data sent to Receive path or Data received from D R input (1) (1) Significant in companded mode only. Table 5:Control Registers CR3 Functions msb lsb D X data transmitted (1) (1) Significant in companded mode only Table 6:Control Register CR4 Functions Internal sidetone disabled Internal sidetone enabled Receive output muted VFr output selected VLr output selected NOT ALLOWED Ring / Tone to V Fr or VLrdisabled Ring / Tone to VFr or VLrenabled X Receive Signal to VFr or VLr disabled Receive Signal to VFr or VLr enabled *: state at power on initialization X: reserved: write 0 ST5090

Table 8:Control Register CR6 Functions 76543210 FunctionEarpiece ampifier [EARA] Extra amplifier [EXTA] 0 dB gain -2 dB gain in 2 dB step -30 dB gain 0 dB gain -2 dB gain in 2 dB step -30 dB gain *: state at power on initialization Table 9:Control Register CR7 Functions Tone gain F1 F2 SN DE Attenuation f1 V pp f2 Vpp X X X X ....0d B * -3 dB -6 dB -9d B -12 dB -15 dB -18 dB -21 dB -24 dB -27 dB ...1.6(2) 0.066 1.26(2) 0.053 f1 and f2 muted f2 selected f1 selected f1 and f2 in summed mode Squarewave signal selected Sinewave signal selected Normal operation Tone / Ring Generator connected to Transmit path *: state at power on initialization (2): value provided if f1 or f2 is selected alone. if f1 and f2 are selected in the summed mode, f1=0.89 Vpp while f2=0.7 Vpp. X reserved: write 0 Table 7:Control Register CR5 Functions Transmit amplifier Sidetone amplifier 0 dB gain 1.5 dB gain in 1.5 dB step 22.5 dB gain -12.5 dB gain -13.5 dB gain in 1 dB step -27.5 dB gain *: state at power on initialization ST5090

Table 10:Control Register CR8 Functions f17 f16 f15 f14 f13 f12 f11 f10 msb lsb Binary equivalent of the decimal number used to calculate f1 Table 11:Control Register CR9 Functions f27 f26 f25 f24 f23 f22 f21 f20 msb lsb Binary equivalent of the decimal number used to calculate f2 Table 13:Control Register CR11 Functions BE BI BZ5 BZ4 BZ3 BZ2 BZ1 BZ0 Buzzer output disabled (set to 0) * Buzzer output enabled Duty Cycle is intended as the relative width of logic 1 * Duty cycle is intended as the relative width of logic 0 msb lsb Binary equivalent of the decimal number used to calculate the duty cycle. * state at power on initialization Table 12:Control Register CR10 Functions (*) Standard Frequency Tone Range Halved Frequency Tone Range Doubled Frequency Tone Range Forbidden (*) Default values inserted into the Register at Power On. X reserved, write 0. ST5090

First byte of a READ or a WRITE instruction to Control Register CR0 is as shown in TABLE 1. Second byte is as shown in TABLE 2. Master Clock Frequency Selection A master clock must be provided to ST5090 for operation of filter and coding/decoding functions. MCLK frequency can be either 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz. Bit F1 (7) and F0 (6) must be set during initializa- tion to select the correct internal divider. Default value is 512 kHz. Any clock different from the default one must be selected prior a Power-Up instruction. Coding Law Selection Bits MA (4) and IA (3) permit selection of Mu-255 law or A law coding with or without even bit inver- sion if companded code (bit CM = 1) is selected. Bits MA(4) and IA(3) permit selection of 2-com- plement, 1-complement or sign and magnitude if linear code (bit CM = 0) is selected. Coding Selection Bit CM (5) permits selection either of linear coding (14-bit) or companded coding (8-bit). Default value is linear coding. Digital Interface format (1) Bit FF(2) = 0 selects digital interface in Format 1 where B1 and B2 channel are consecutive. FF=1 selects Format 2 where B1 and B2 channel are separated by two bits. (See digital interface for- mat section.) 56+8 selection (1) Bit ’B7’ (1) selects capability for ST5090 to take into account only the seven most significant bits of the PCM data byte selected. When ’B7’ is set, the LSB bit on D R is ignored and LSB bit on DX is high impedance. This function al- lows connection of an external ”in band” data generator directly connected on the Digital Inter- face. Digital loopback Digital loopback mode is entered by setting DL bit(0) equal 1. In Digital Loopback mode, data written into Re- ceive PCM Data Register from the selected re- ceived time-slot is read-back from that Register in the selected transmit time-slot on D X . No PCM decoding or encoding takes place in this mode. Transmit and Receive amplifier stages are muted. CONTROL REGISTER CR1 First byte of a READ or a WRITE instruction to Control Register CR1 is as shown in TABLE 1. Second byte is as shown in TABLE 3. Digital Interface Timing Bit DM1(7) = 0 selects digital interface in delayed timing mode, while DM1 = 1 and DM0 = 0 selects non-delayed normal data timing mode, and DM1 = 1 and DM0 = 1 selects non-delayed reverse data timing mode. Default is delayed data timing. Latch output control Bit DO controls directly logical status of latch out- put LO: ie, a ”ZERO” written in bit DO puts the output LO at logical 1, while a ”ONE” written in bit DO sets the output LO to zero. Microwire access to B channel on receive path (1) Bit MR (4) selects access from MICROWIRE Register CR2 to Receive path. When bit MR is set high, data written to register CR2 is decoded each frame, sent to the receive path and data in- put at D R is ignored. In the other direction, current PCM data input re- ceived at DR can be read from register CR2 each frame. Microwire access to B channel on transmit path (1) Bit MX (3) selects access from MICROWIRE write only Register CR3 to D X output. When bit MX is set high, data written to CR3 is output at DX every frame and the output of PCM encoder is ignored. Mu 255 law True A law even bit inversion A law without even bit inversion msb lsb msb lsb msb lsb Vin = + full scale 100000001010101011111111 Vin = 0 V 1 Vin = - full scale 000000000010101001111111 MSB is always the first PCM bit shifted in or out of: ST5090. (1) Significant in companded mode only ST5090

Transmit/Receive enabling/disabling Bit ’EN’ (2) enables or disables voice data trans- fer on D X and DR pins. When disabled, PCM data from DR is not decoded and PCM time-slots are high impedance on DX. Default value is disabled. B-channel selection (1) Bit TS(1) permits selection between B1 or B2 channels. Default value is B1 channel. Supply Voltage selection Bit SV (0) permits selection of the power supply of the ST5090. Default value is 3.3V. CONTROL REGISTER CR2 (1) Data sent to receive path or data received from D R input. Refer to bit MR(4) in ”Control Register CR1” paragraph. CONTROL REGISTER CR3 (1) D X data transmitted. Refer to bit MX(3) in ”Control Register CR1” paragraph. CONTROL REGISTER CR4 First byte of a READ or a WRITE instruction to Control Register CR4 is as shown in TABLE 1. Second byte is as shown in TABLE 6. Transmit Input Selection MIC1 or MIC2 or MIC3 or transmit mute can be selected with bits 6 and 7 (V S and TE). Transmit gain can be adjusted within a 22.5 dB range in 1.5 dB step with Register CR5. Sidetone Selection Bit ”SI” (5) enables or disables Sidetone circuitry. When enabled, sidetone gain can be adjusted with Register (CR5). When Transmit path is dis- abled, sidetone circuit is also disabled. Output Driver Selection Bits OE1(4) and OE2(3) provide the selection among the earpiece output or the extra amplifier output or both outputs muted. OE1 = 1 and OE2 = 1 is not allowed. Ring/Tone signal selection Bit RTE (2) provide select capability to connect on-chip Ring/Tone generator either to an extra amplifier input or to earpiece amplifier input. PCM receive data selection Bits ”SE” (0) provide select capability to connect received speech signal either to an extra amplifier input or to earpiece amplifier input. CONTROL REGISTER CR5 First byte of a READ or a WRITE instuction to Control Register CR5 is as shown in TABLE 1. Second byte is as shown in TABLE 7. Transmit gain selection Transmit amplifier can be programmed for a gain from 0dB to 22.5dB in 1.5dB step with bits 4 to 7. 0 dBmO level at the output of the transmit ampli- fier (A reference point) is 0.492 Vrms (overload voltage is 0.707 Vrms). Sidetone attenuation selection Transmit signal picked up after the switched ca- pacitor low pass filter may be fed back into both Receive amplifiers. Attenuation of the signal at the output of the sidetone attenuator can be programmed from –12.5dB to -27.5dB relative to reference point A in 1 dB step with bits 0 to 3. CONTROL REGISTER CR6 First byte of a READ or a WRITE instruction to Control Register CR6 is as shown in TABLE 1. Second byte is as shown in TABLE 8. Earpiece amplifier gain selection: Earpiece Receive gain can be programmed in 2 dB step from 0 dB to -30 dB relative to the maxi- mum with bits 4 to 7. 0 dBmO voltage at the output of the amplifier on pins V Fr+ and VFr-is then 1.965 Vrms when 0dB gain is selected down to 61.85 Vrms when -30dB gain is selected. Extra amplifier gain selection: Extra Receive amplifier gain can be programmed in 2 dB step from 0 dB to -30 dB relative to the maximum with bits 0 to 3. 0 dBmO voltage on the output of the amplifier on pins V Lr+ and VLr-1.965 Vrms when 0 dB gain is selected down to 61.85 mVrms when -30 dB gain is selected. CONTROL REGISTER CR7: First byte of a READ or a WRITE instruction to Control Register CR7 is as shown in TABLE 1. Second byte is as shown in TABLE 9. (1) Significant in companded mode only ST5090

Tone/Ring amplifier gain selection Output level of Ring/Tone generator, before at- tenuation by programmable attenuator is 1.6 Vpk- pk when f1 generator is selected alone or summed with the f2 generator and 1.26 Vpk-pk when f2 generator is selected alone. Selected output level can be attenuated down to -27 dB by programmable attenutator by setting bits 4 to 7. Frequency mode selection Bits ’F1’ (3) and ’F2’ (2) permit selection of f1 and/or f2 frequency generator according to TA- BLE 9. When f1 (or f2) is selected, output of the Ring/Tone is a squarewave (or a sinewave) signal at the frequency selected in the CR8 (or CR9) Register. When f1 and f2 are selected in summed mode, output of the Ring/Tone generator is a signal where f1 and f2 frequency are summed. In order to meet DTMF specifications, f2 output level is attenuated by 2dB relative to the f1 output level. Frequency temporization must be controlled by the microcontroller. Waveform selection Bit ’SN’ (1) selects waveform of the output of the Ring/Tone generator. Sinewave or squarewave signal can be selected. DTMF selection Bit DE (0) permits connection of Ring/Tone/DTMF generator on the Transmit Data path instead of the Transmit Amplifier output. Earpiece or extra receive output feed-back may be provided by sidetone circuitry by setting bit SI or directly by setting bit RTE in Register CR4. Loudspeaker feed-back may be provided directly by setting bit RTL in Register CR4. CONTROL REGISTERS CR8 AND CR9 First byte of a READ or a WRITE instruction to Control Register CR8 or CR9 is as shown in TA- BLE 1. Second byte is respectively as shown in TABLE 10 and 11. If ”standard frequency tone range” is selected, Tone or Ring signal frequency value is defined by the formula: f1 = CR8 / 0.128 Hz and f2 = CR9 / 0.128 Hz where CR8 and CR9 are decimal equivalents of the binary values of the CR8 and CR9 registers respectively. Thus, any frequency between 7.8 Hz and 1992 Hz may be selected in 7.8 Hz step. If ”halved frequency tone range”is selected, Tone or Ring signal frequency value is defined by the formula: f1 = CR8 / 0.256 Hz and f2 = CR9 / 0.256 Hz This any frequency between 3.9Hz and 996Hz may be selected in 3.9Hz step. If ”doubled frequency tone range”is selected, Tone or Ring signal frequency value is defined by the formula: f1 = CR8 / 0.064 Hz and f2 = CR9 / 0.064 Hz Thus any frequency between 15.6Hz and 3984Hz may be selected in 15.6Hz step. TABLE 12 gives examples for the main frequen- cies usual for Tone or Ring generation. CONTROL REGISTER CR10 Bit DFT(1) and HFT(0) permits the selection among ”standard frequency tone range” (i.e. from 7.8Hz to 1992Hz in 7.8Hz step), ”halved fre- quency tone range” (i.e. from 3.9Hz to 996Hz in 3.9Hz step), and ”doubled frequency tone range” (i.e. from 15.6Hz to 3984Hz in 15.6Hz step) ac- cording to the values described in CONTROL REGISTER CR8 and CR9. CONTROL REGISTER CR11 Bit BE(7) permits connection of a f1 squarewave PWM Ring signal, amplitude modulated or not by a f2 squarewave signal, to buzzer driver output BZ. Bits BZ5 to BZ0 define the duty cycle of the PWM squarewave, according to the following for- mula: Duty Cycle = CR11(5÷ 0) x 0.78125% where CR11(5 ÷ 0) is the decimal equivalent of the binary value BZ5÷ BZ0. When BE = 1, if bits F1 = 1 and F2 = 0 in regis- ter CR7, a f1 PWM ring signal is present at the buzzer output, while if bits F1 = 1 and F2 = 1 in register CR7 the f1 PWM ring signal is also am- plitude modulated by a f2 squarewave fre- quency. Bit BI (6) allows to chose the logic level at which the duty cycle is referred: BI = 0 means that duty cycle is intended as the relative width of the logic1, while BI = 1 means that duty cycle is intended as the relative width of the logic 0. When BE = 0 (or during power down) BZ = 0 if BI = 0 or BZ = 1 if BI = 1. ST5090

Table 12:Examples of Usual Frequency Selection (Standard frequency tone range) Description f1 value (decimal) Theoretic value (Hz) Typical value (Hz) Error % Tone 250 Hz Tone 330 Hz Tone 425 Hz Tone 440 Hz Tone 800 Hz Tone 1330 Hz 102 170 250 330 425 440 800 1330 250 328.2 421.9 437.5 796.9 1328.1 .00 –.56 –.73 –.56 –.39 –.14 DTMF 697 Hz DTMF 770 Hz DTMF 852 Hz DTMF 941 Hz DTMF 1209 Hz DTMF 1336 Hz DTMF 1477 Hz DTMF 1633 Hz 109 120 155 171 189 209 697 770 852 941 1209 1336 1477 1633 695.3 773.4 851.6 937.5 1210.9 1335.9 1476.6 1632.8 –.24 +.44 –.05 –.37 +.16 –.01 .00 .00 SOL LA SI DO RE MI flat MI FA FA sharp SOL SOL sharp LA SI DO RE MI 100 106 113 126 134 150 169 392 440 494 523.25 587.33 622.25 659.25 698.5 740 784 830.6 880 987.8 1046.5 1174.66 1318.5 390.6 437.5 492.2 523.5 586.0 625.0 656.3 695.3 742.2 781.3 828.2 882.9 984.4 1046.9 1171.9 1320.4 –.30 –.56 –.34 +.04 –.23 +.45 –.45 –.45 +.30 –.34 –.29 +.33 –.34 +.04 –.23 +.14 ST5090

Non Delayed Data Timing Mode (Normal) (*) Delayed Data Timing Mode (*) 16 17 16 17 (*) In the case of companded code the timing is applied to 8 bits instead of 16 bits (see ST5080A data sheet) ST5090

TIMING DIAGRAM (continued) Non Delayed Reverse Data Timing Mode (*) Serial Control Timing (MICROWIRE MODE) (*) In the case of companded code the timing is applied to 8 bits instead of 16 bits. ST5090

TIMING SPECIFICATIONS (unless otherwise specified, VCC = 3.3V+ 10%or5V± 10%, TA =– 3 0°Ct o8 5°C; typical characteristics are specified VCC = 3.3V, TA =2 5°C; all signals are referenced to GND, see Note 5 for timing definitions) NOTICE: All timing specifications can be changed. MASTER CLOCK TIMING Symbol Parameter Test Condition Min. Typ. Max. Unit fMCLK Frequency of MCLK Selection of frequency is programmable (see table 2) 512 1.536 2.048 2.560 kHz MHz MHz MHz tWMH Period of MCLK high Measured from V IH to VIH 80 ns tWML Period of MCLK low Measured from V IL to VIL 80 ns tRM Rise Time of MCLK Measured from V IL to VIH 30 ns tFM Fall Time of MCLK Measured from V IH to VIL 30 ns PCM INTERFACE TIMING Symbol Parameter Test Condition Min. Typ. Max. Unit tHMF Hold Time MCLK low to FS low 0 ns tSFM Setup Time, FS high to MCLK low 30 ns tDMD Delay Time, MCLK high to data valid Load = 100 pf 100 ns tDMZ Delay Time, MCLK low to DX disabled 10 100 ns tDFD Delay Time, FS high to data valid Load = 100 pf ; Applies only if FS rises later than MCLK rising edge in Non Delayed Mode only 100 ns t SDM Setup Time, DR valid to MCLK receive edge 20 ns tHMD Hold Time, MCLK low to DR invalid 10 ns tHMFR Hold Time MCLK High to FS low 30 ns tSFMR SetupTime, FS high toMCLK High 30 ns tDMDR Delay Time, MCLK low to data valid Load = 100pF 100 ns tDMZR Delay Time, MCLK High to DX disabled 10 100 ns tHMDR Hold Time, MCLK High to DR invalid 20 ns ABSOLUTE MAXIMUM RATINGS Parameter Value Unit VCC to GND 7V Voltage at MIC (VCC ≤ 5.5V) V CC +1 to GND -1 V Current at VFr and VLr + 100 mA Current at any digital output + 50 mA Voltage at any digital input (V CC ≤ 5.5V); limited at + 50mA V CC + 1 to GND - 1 V Storage temperature range - 65 to + 150 °C Lead Temperature (wave soldering, 10s) + 260 °C ST5090

SERIAL CONTROL PORT TIMING Symbol Parameter Test Condition Min. Typ. Max. Unit fCCLK Frequency of CCLK 2.048 MHz tWCH Period of CCLK high Measured from V IH to VIH 160 ns tWCL Period of CCLK low Measured from V IL to VIL 160 ns tRC Rise Time of CCLK Measured from V IL to VIH 50 ns tFC Fall Time of CCLK Measured from V IH to VIL 50 ns tHCS Hold Time, CCLK high to CS– low 10 ns tSSC SetupTime, CS– low to CCLK high 50 ns tSDC Setup Time, CI valid to CCLK high 50 ns tHCD Hold Time, CCLK high to CI invalid 50 ns tDCD Delay Time, CCLK low to CO data valid Load = 100 pF 80 ns tDSD Delay Time, CS–low to CO data valid 50 ns tDDZ Delay Time CS–high or 8th CCLK low to CO high impedance whichever comes first 10 80 ns t HSC Hold Time, 8th CCLK high to CS– high 100 ns tSCS Set up Time, CS– high to CCLK high 100 ns Note 5: A signal is valid if it is above VIH or below VILand invalid if it is between VILand VIH. For the purpoes of this specification the following conditions apply: a) All input signal are defined as: VIL = 0.2VCC ,VIH = 0.8VCC ,tR < 10ns, tF < 10ns. b) Delay times are measured from the inputs signal valid to the output signal valid. c) Setup times are measured from the data input valid to the clock input invalid. d) Hold times are measured from the clock signal valid to the data input invalid. ELECTRICAL CHARACTERISTICS (unless otherwise specified, VCC = 3.3V + 10% or 5V±10%,T A =– - 3 0°C to85°C ; typical characteristic are specified at VCC = 3.3V,TA =2 5°C ; all signals are referenced to GND) DIGITAL INTERFACES Symbol Parameter Test Condition Min. Typ. Max. Unit VIL Input Low Voltage All digital inputs DC AC 0.3VCC V 0.2VCC V V IH Input High Voltage All digital inputs DC AC 0.7VCC V 0.8VCC V VOL Output Low Voltage All digital outputs, I L =1 0µA All digital outputs, IL = 2mA 0.1 0.4 V V VOH Output High Voltage All digital outputs, I L =1 0µA All digital outputs, IL = 2mA VCC -0.1 VCC -0.4 V V IIL Input Low Current Any digital input, GND < V IN <V IL -10 10 µA IIH Input High Current Any digital input, VIH <V IN <V CC -10 10 µA IOZ Output Current in High impedance (Tri-state) D X and CO -10 10 µA A.C. TESTING INPUT, OUTPUT WAVEFORM 0.8VCC 0.2VCC 0.7VCC 0.3VCC 0.7VCC 0.3VCC TEST POINTS INTPUT/OUTPUT D93TL077 AC Testing: inputs are driven at 0.8VCC for a logic ”1”and 0.2VCC for a logic ”0 ”. Timing measurements are made at 0.7V CC for a logic ”1”and 0.3VCC for a logic ”0”. ST5090

Symbol Parameter Test Condition Min. Typ. Max. Unit IMIC Input Leakage GND < V MIC <V CC -100 +100 µA R MIC Input Resistance GND < V MIC <V CC 50 k Ω R LVFr Load Resistance (*) V Fr+ to VFr- 30 Ω C LVFr Load Capacitance (*) From V Fr+ to VFr- 50 nF R OVFr0 Output Resistance Steady zero PCM code applied to DR; I = + 1mA 1.0 Ω VOSVFr0 Differential offset: Voltage at VFr+,V Fr- Alternating + zero PCM code applied to DR maximum receive gain; R L = 100Ω -100 +100 mV R LvLr Load Resistance (*) V Lr+ to VLr- 30 Ω C LvLr Load Capacitance (*) from V Lr+ to VLr- 50 nF R OLVrO Output Resistance Steady zero PCM code applied to DR; I + 1mA 1 Ω VOSVLrO Differential offset Voltage at VLr+,VLr- Alternating + zero PCM code applied to DR maximum receive gain; R L =5 0Ω –100 +100 mV (*) See application note for VFr and VLrconnections. POWER DISSIPATION Symbol Parameter Test Condition Min. Typ. Max. Unit ICC0 Power down Current at 3.3V± 10% CCLK,CI = 0.1V; CS = VCC -0.1V 0.5 5 µA ICC0 Power down Current at 5V± 10% CCLK,CI = 0.1V; CS = VCC -0.1V 1 10 µA ICC1 Power Up Current at 3.3V± 10% V Lr+,VLr- and VFr+,VFr-not loaded 71 0 m A ICC1 Power Up Current at 5V± 10% V Lr+,VLr- and VFr+,VFr-not loaded 81 2 m A TRANSMISSION CHARACTERISTICS (unless otherwise specified, VCC = 3.3V + 10% or 5V ± 10%, T A = –30 °Ct o8 5 °C; typical characteristics are specified at VCC =3 . 3 V ,TA =2 5 °C, MIC1/2/3 = 0dBm0 , D R = –6dBm0 PCM code, f = 1015.625 Hz; all signal are referenced to GND) AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Transmit path - Absolute levels at MIC1 / MIC2 / MIC3 Parameter Test Condition Min. Typ. Max. Unit 0 dBm0 level Transmit Amps connected for 20dB gain 49.26 mV RMS Overload level 70.71 mV RMS 0 dBm0 level Transmit Amps connected for 42.5dB gain 3.694 mV RMS Overload level 5.302 mV RMS ST5090

TRANSMISSION CHARACTERISTICS (continued) AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Receive path - Absolute levels at VFR (Differentiallymeasured) Parameter Test Condition Min. Typ. Max. Unit 0 dBM0 level Receive Amp programmed for 0dB gain

1.965 V RMS

0 dBM0 level Receive Amp programmed for - 30dB attenuation 61.85 mV RMS AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Receive path - Absolute levels at VLr (Differentially measured) Parameter Test Condition Min. Typ. Max. Unit 0 dBM0 level Receive Amp programmed for 0dB gain 0 dBM0 level Receive Amp programmed for - 30dB gain 61.85 mV RMS AMPLITUDE RESPONSE Transmit path Symbol Parameter Test Condition Min. Typ. Max. Unit G XA Transmit Gain Absolute Accuracy Transmit Gain Programmed for maximum. Measure deviation of Digital PCM Code from ideal 0dB PCM code at DX -0.5 0.5 dB G XAG Transmit Gain Variation with programmed gain Measure Transmit Gain over the range from Maximum to minimum setting. Calculate the deviation from the programmed gain relative to GXA, i.e. G AXG =G actual-G prog.-G XA -0.5 0.5 dB G XAT Transmit Gain Variation with temperature Measured relative to GXA . min. gain < GX < Max. gain -0.1 0.1 dB G XAV Transmit Gain Variation with supply Measured relative to GXA G X = Maximum gain -0.1 0.1 dB G XAF Transmit Gain Variation with frequency Relative to 1015,625 Hz, multitone test technique used. min. gain < G X < Max. gain f = 60 Hz f = 100 Hz f = 200 Hz f = 300 Hz f = 400 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz f = 4600 Hz (*) f = 8000 Hz (*) -1.5 -0.5 -1.5 -30 -20 0.5 0.5 0.0 -14 -35 -47 dB dB dB dB dB dB dB dB dB G XAL Transmit Gain Variation with signal level Sinusoidal Test method. Reference Level = -10 dBm0 V MIC = -40 dBm0 to +3 dBm0 VMIC = -50 dBm0 to -40 dBm0 VMIC = -55 dBm0 to -50 dBm0 -0.5 -0.5 -1.2 0.5 0.5 1.2 dB dB dB (*) The limit at frequencies between 4600Hz and 8000Hz lies on a straightline connecting the two frequencies on a linear (dB) scale versus log (Hz) scale. ST5090

Symbol Parameter Test Condition Min. Typ. Max. Unit G RAE Receive Gain Absolute Accuracy Receive gain programmed for maximum Apply -6 dB m0 PCM code to DR Measure VFr+ -0.5 0.5 dB G RAL Receive Gain Absolute Accuracy Receive gain programmed for maximum Apply -6 dBm0 PCM code to DR Measure VLr+ -0.5 0.5 dB G RAGE Receive Gain Variation with programmed gain Measure VFr Gain over the range from Maximum to minimum setting. Calculate the deviation from the programmed gain relative to GRAE, i.e. G RAGE =G actual-G prog.-G RAE -0.5 0.5 dB G RAGL Receive Gain Variation with programmed gain Measure VLrGain over the range from Maximum to minimum setting. Calculate the deviation from the programmed gain relative to GRAL, i.e. G RAGL =G actual-G prog.-G RAL -0.5 0.5 dB G RAT Receive Gain Variation with temperature Measured relative to GRA. (VLr and VFr) min. gain < GR < Max. gain -0.1 0.1 dB G RAV Receive Gain Variation with Supply Measured relative to GRA. (VLr and VFr) G R = Maximum Gain -0.1 0.1 dB G RAF Receive Gain Variation with frequency (VLrand VFr) Relative to 1015,625 Hz, multitone test technique used. min. gain < GR < Max. gain f = 60Hz f = 100Hz f = 200 Hz f = 300 Hz f = 400 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz -1.5 -0.5 -1.5 -20 -12 0.5 0.5 0.0 -14 dB dB dB dB dB dB dB G RAL E Receive Gain Variation with signal level (VFr) Sinusoidal Test Method Reference Level = –10 dBm0 D R = -40 dBm0 to -3 dBm0 D R = -50 dBm0 to -40 dBm0 D R = -55 dBm0 to -50 dBm0 -0.5 -0.5 -1.2 0.5 0.5 1.2 dB dB dB G RAL L Receive Gain Variation with signal level (VLr) Sinusoidal Test Method Reference Level = –10 dBm0 D R = -40 dBm0 to -3 dBm0 D R = -50 dBm0 to -40 dBm0 D R = -55 dBm0 to -50 dBm0 -0.5 -0,5 -1.2 0.5 0.5 1.2 dB dB dB ST5090

ENVELOPE DELAY DISTORTION WITH FREQUENCY Symbol Parameter Test Condition Min. Typ. Max. Unit DXA Tx Delay, Absolute f = 1600 Hz 320 µs DXR Tx Delay, Relative f = 500 - 600 Hz f = 600 - 800 Hz f = 800 - 1000 Hz f = 1000 - 1600 Hz f = 1600 - 2600 Hz f = 2600 - 2800 Hz f = 2800 - 3000 Hz 290 180 180 µs µs µs µs µs µs µs DRA Rx Delay, Absolute f = 1600 Hz 280 µs DRR Rx Delay, Relative f = 500 - 600 Hz f = 600 - 800 Hz f = 800 - 1000 Hz f = 1000 - 1600 Hz f = 1600 - 2600 Hz f = 2600 - 2800 Hz f = 2800 - 3000 Hz 200 110 100 220 µs µs µs µs µs µs µs NOISE Symbol Parameter Test Condition Min. Typ. Max. Unit NXP Tx Noise, P weighted (up to 35dB) VMIC = 0V, DE = 0 -75 -70 dBm0p NRP Rx Noise, A weighted (max. gain) Receive PCM code = Positive Zero SI = 0 and RTE = 0 120 150 µVrms (*) NRS Noise, Single Frequency MIC = 0V, Loop-around measurament from f = 0 Hz to 100 kHz -50 dBm0 PPSRx PSRR, Tx MIC = 0V, VCC = 3.3 VDC +5 0m Vrms; f = 0Hz to 50KHz 30 60 dB PPSRp PSRR, Rx PCM Code equals Positive Zero, VCC = 3.3 VDC + 50 mVrms, f=0H z-4k H z f = 4 kHz - 50 kHz dB dB SOS Spurious Out-Band signal at the output DR input set to -6 dBm0 PCM code 300 - 3400 Hz Input PCM Code applied at DR

4600 Hz - 5600 Hz

5600 Hz - 7600 Hz

7600 Hz - 8400 Hz

-40 -50 -50 dB dB dB (*) A Weighted ST5090

Symbol Parameter Test Condition Min. Typ. Max. Unit STDX (*) Signal to Total Distortion (up to 35dB gain) Typical values are measured with 30.5dB gain Sinusoidal Test Method (measured using linear 300 to 3400 weighting) Level = 0 dBm0 Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 37.5 28.5 dB dB dB dB dB dB dB dB S DFx Single Frequency Distortion transmit 0 dBm0 input signal -80 -56 dB STDRE (*) Signal to Total Distortion (VFr) ( up to 20dB attenuation) Typical values are measured with 20dB attenuation. Sinusoidal Test Method (measured using linear 300 to 3400 weighting) Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 dB dB dB dB dB dB dB S DFr Single Frequency Distortion receive (VFr) -6 dBm0 input signal -80 -50 dB STDRL (*) Signal to Total Distortion (VLr) (up to 20dB attenuation) Typical values are measured with 20dB attenuation Sinusoidal Test Method (measured using linear 300 to 3400 weighting) Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -40 dBm0 Level = -45 dBm0 Level = -55 dBm0 dB dB dB dB dB dB dB S DLr Single Frequency Distortion receive (VLr) -6 dBm0 input signal -80 -50 dB IMD Intermodulation Loop-around measurement Voltage at MIC = -10 dBm0 to -27 dBm0, 2 Frequencies in the range 300 - 3400 Hz -75 -46 dB (*) The limit curve shall be determined by straight lines joining successive coordinates given in the table. (#) Lower limits used during the automatic testing to avoid unrealistic yield loss due to±2dB imprecision of time-limited noise measurements. CROSSTALK Symbol Parameter Test Condition Min. Typ. Max. Unit C Tx-r Transmit to Receive Transmit Level = 0 dBm0, f = 300 - 3400 Hz DR = Quiet PCM Code -100 -65 dB C Tr-x Receive to Transmit Receive Level = -6 dBm0, f = 300 - 3400 Hz MIC = 0V -80 -65 dB ST5090

APPLICATIONS

Application Note for Microphone Connections VFr+ VFr- VLr+ VLr- ST5090 VFr+ VFr- VLr+ VLr- ST5090 R R VFr+ VFr- VLr+ VLr- ST5090 R D93TL078A R must be greater than 30Ω For higher capacitive transducers, lower R values can be used. DYNAMIC RECEIVERS (32Ω ) CERAMIC RECEIVERS (50nF) DYNAMIC/CERAMIC RECEIVERS (REVERSIBLE) Application Note for VFr and VLr Connections POWER SUPPLIES While pins of ST5090 device are well protected against electrical misuse, it is recommended that the standard CMOS practise of applying GND be- fore any other connections are made should al- ways be followed. In applications where the printed circuit card may be plugged into a hot socket with power and clocks already present, an extra long ground pin on the connector should be used. To minimize noise sources, all ground connec- tions to each device should meet at a common point as close as possible to the GND pin in order to prevent the interaction of ground return cur- rents flowing through a common bus impedance. A power supply decoupling capacitor of 0.1µF should be connected from this common point to V CC as close as possible to the device pins. ST5090 ST5090 ST5090 ST5090

TQFP44 (10 x 10) PACKAGE MECHANICAL DATA DIM. mm inch A 1.60 0.063 A1 0.05 0.15 0.002 0.006 C 0.09 0.20 0.004 0.008 D 12.00 0.472 D1 10.00 0.394 D3 8.00 0.315 e 0.80 0.031 E 12.00 0.472 E1 10.00 0.394 E3 8.00 0.315 L1 1.00 0.039 K 0°(min.), 3.5°(typ.), 7°(max.) A A1B Seating Plane C 2333 E D e K B L 0.10mm .004 ST5090

SO28 PACKAGE AND MECHANICAL DATA DIM. mm inch A 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45 ° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S8 ° (max.) ST5090

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications men- tioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of SGS-THOMSON Microelectronics.  1996 SGS-THOMSON Microelectronics All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. ST5090