SSTVN16857

SSTV16857 FAIRCHILD | Alldatasheet

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I Compliant with DDR-I registered module specifications I Operates at 2.5V /c114 0.2V VDD I SSTL-2 compatible input and output structure I Differential SSTL-2 compatible clock inputs I Low power mode when device is reset I Industry standard 48 pin TSSOP package Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Truth Table L /c32 Logic LOW H /c32 Logic HIGH X /c32 Don’t Care, but not floating unless noted /c110 /c32 LOW-to-HIGH Clock Transition /c112 /c32 HIGH-to-LOW Clock Transition Order Number Package Number Package Description SSTV16857MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide SSTVN16857MTD (Preliminary) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Pin Name Description Q 1-Q14 SSTL-2 Compatible Output D 1-D14 SSTL-2 Compatible Inputs RESET Asynchronous LVCMOS Reset Input CK Positive Master Clock Input CK Negative Master Clock Input VREF Voltage Reference Pin for SSTL Level Inputs VDDQ Power Supply Voltage for Output Signals VDD Power Supply Voltage for Inputs RESET D n CK CK Q n LX o r Floating X or Floating X or Floating L HL /c110/c112 L HH /c110/c112 H HXLH Q n HXHL Q n

www.fairchildsemi.com 2 SSTV16857  SSTVN16857 Functional Description The SSTV16857 and SSTVN16587 are 14-bit registers with SSTL-2 compatible inputs and outputs. Input data is captured by the register on the positive edge crossing of the differential clock pair. When the LV-CMOS RESET signal is asserted LOW, all outputs and internal registers are asynchronously placed into the LOW logic state. In addition, the clock and data dif- ferential comparators are disabled for power savings. Out- put glitches are prevented by disabling the internal registers more quickly than the input comparators. When RESET is removed, the system designer must insure the clock and data inputs to the device are stable during the rising transition of the RESET signal. The SSTL-2 data inputs transition based on the value of VREF . VREF is a stable system reference used for setting the trip point of the input buffers of the SSTV16857/ SSTVN16857 and other SSTL-2 compatible devices. The RESET signal is a standard CMOS compatible input and is not referenced to the VREF signal. Logic Diagram

3 www.fairchildsemi.com SSTV16857  SSTVN16857 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 3) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. Note 3: The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is asserted LOW. Supply Voltage (VDDQ ) /c16 0.5V to /c14 3.6V Supply Voltage (VDD ) /c16 0.5V to /c14 3.6V Reference Voltage (VREF ) /c16 0.5V to /c14 3.6V Input Voltage (VI) /c16 0.5V to VDD /c14 0.5V Output Voltage (VO ) Outputs Active (Note 2) /c16 0.5V to VDDQ /c14 0.5V DC Input Diode Current (IIK) VI /c31 0V /c16 50 mA VI /c33 VDD /c14 50 mA DC Output Diode Current (IOK ) VO /c31 0V /c16 50 mA VO /c33 VDD /c14 50 mA DC Output Source/Sink Current (IOH /IOL ) /c114 50 mA DC V DD or Ground Current per Supply Pin (IDD or Ground) /c114 100 mA Storage Temperature Range (Tstg) /c16 65/c113 C to /c14 150/c113 C Power Supply (VDDQ ) SSTV16857 2.3V to 2.7V SSTVN16857 2.5V to 2.7V Power Supply (V DD ) Operating Range V DDQ to 2.7V Reference Supply (VREF /c32 VDDQ /2) SSTV16857 1.15 to 1.35 SSTVN16857 1.25 to 1.35 Termination Voltage (VTT)V REF /c114 40 mV Input Voltage 0V to V DD Output Voltage (VO ) Output in Active States 0V to V DDQ Output Current IOH /IOL VDD /c32 2.3V to 2.7V SSTV16857 /c114 20 mA VDD /c32 2.5V to 2.7V SSTVN16857 /c114 20 mA Free Air Operating Temperature (TA)0 /c113 C to /c14 70/c113 C Symbol Parameter Conditions VDD Min Max Units (V) VIKL Input LOW Clamp Voltage I I /c32 /c16 18 mA 2.3 /c16 1.2 V VIKH Input HIGH Clamp Voltage I I /c32 /c14 18 mA 2.3 3.5 V VIH-AC AC HIGH Level Input Voltage Data Inputs V REF /c14 310mV V VIL-AC AC LOW Level Input Voltage Data Inputs V REF /c16 310mV V VIH-DC DC HIGH Level Input Voltage Data Inputs V REF /c14 150mV V VIL-DC DC LOW Level Input Voltage Data Inputs V REF /c16 150mV V VIH HIGH Level Input Voltage RESET 1.7 V VIL LOW Level Input Voltage RESET 0.7 V VICR Common Mode Input Voltage Range CLK, CLK 0.97 1.53 V VI(PP) Peak to Peak Input Voltage CLK, CLK 360 mV VOH HIGH Level Output Voltage I OH /c32 /c16 100 /c80 A 2.3 to 2.7 V DD /c16 0.2 V IOH /c32 /c16 16 mA 2.3 1.95 VOL LOW Level Output Voltage I OL /c32 100 /c80 A 2.3 to 2.7 0.2 V IOL /c32 16 mA 2.3 0.35 II Input Leakage Current V I /c32 VDD or GND 2.7 /c114 5.0 /c80 A IDD Static Standby RESET /c32 GND, IO /c32 0 2.7 10 /c80 A Static Operating RESET /c32 VDD , IO /c32 0 25 mA VI /c32 VIH(AC) or VIL(AC)

www.fairchildsemi.com 4 SSTV16857  SSTVN16857 Symbol Parameter Conditions VDD Min Max Units (V) IDDD Dynamic Operating Current RESET /c32 VDD , IO /c32 0 2.7 /c80 A/MHzClock Only V I /c32 VIH(AC) or VIL(AC) 90 CK, CK Duty Cycle 50% Dynamic Operating Current RESET /c32 VDD , IO /c32 0 /c80 A/MHz per Data Input V I /c32 VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% 15 Data Input /c32 ½ Clock Rate 50% Duty Cycle R OH Output HIGH On Resistance I OH /c32 /c16 20 mA 2.3 to 2.7 7 20 /c58 R OL Output LOW On Resistance I OL /c32 20 mA 2.3 to 2.7 7 20 /c58 R O /c39 | ROH - ROL |I O /c32 20 mA, TA /c32 25/c113 C2 . 5 4 /c58 Symbol Parameter Conditions VDD Min Max Units (V) VIKL Input LOW Clamp Voltage I I /c32 /c16 18 mA 2.5 /c16 1.2 V VIKH Input HIGH Clamp Voltage I I /c32 /c14 18 mA 2.5 3.5 V VIH-AC AC HIGH Level Input Voltage Data Inputs V REF /c14 310mV V VIL-AC AC LOW Level Input Voltage Data Inputs V REF /c16 310mV V VIH-DC DC HIGH Level Input Voltage Data Inputs V REF /c14 150mV V VIL-DC DC LOW Level Input Voltage Data Inputs V REF /c16 150mV V VIH HIGH Level Input Voltage RESET 1.7 V VIL LOW Level Input Voltage RESET 0.7 V VICR Common Mode Input Voltage Range CLK, CLK 0.97 1.53 V VI(PP) Peak to Peak Input Voltage CLK, CLK 360 mV VOH HIGH Level Output Voltage I OH /c32 /c16 100 /c80 A 2.5 to 2.7 V DD /c16 0.2 V IOH /c32 /c16 16 mA 2.5 1.95 VOL LOW Level Output Voltage I OL /c32 100 /c80 A 2.5 to 2.7 0.2 V IOL /c32 16 mA 2.5 0.35 II Input Leakage Current V I /c32 VDD or GND 2.7 /c114 5.0 /c80 A IDD Static Standby RESET /c32 GND, IO /c32 0 2.7 10 /c80 A Static Operating RESET /c32 VDD , IO /c32 0 25 mA VI /c32 VIH(AC) or VIL(AC) IDDD Dynamic Operating Current RESET /c32 VDD , IO /c32 0 2.7 /c80 A/MHzClock Only V I /c32 VIH(AC) or VIL(AC) 90 CK, CK Duty Cycle 50% Dynamic Operating Current RESET /c32 VDD , IO /c32 0 /c80 A/MHz per Data Input V I /c32 VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% 15 Data Input /c32 ½ Clock Rate 50% Duty Cycle R OH Output HIGH On Resistance I OH /c32 /c16 20 mA 2.5 to 2.7 7 20 /c58 R OL Output LOW On Resistance I OL /c32 20 mA 2.5 to 2.7 7 20 /c58 R O /c39 | ROH - ROL |I O /c32 20 mA, TA /c32 25/c113 C2 . 5 4 /c58

5 www.fairchildsemi.com SSTV16857  SSTVN16857 Note 4: Refer to Figure 1 through Figure 7. Note 5: This parameter is not production tested. Note 6: For data signal input slew rate /c116 1 V/ns. Note 7: For data signal input slew rate /c116 0.5 V/ns and /c31 1 V/ns. Note 8: For CK, CK signals input slew rates are /c116 1 V/ns. Note 9: Refer to Figure 1 through Figure 7. Note 10: This parameter is not production tested. Note 11: For data signal input slew rate /c116 1 V/ns. Note 12: For data signal input slew rate /c116 0.5 V/ns and /c31 1 V/ns. Note 13: For CK, CK signals input slew rates are /c116 1 V/ns. Note 14: Simultaneous Switching is guaranteed by characterization. Symbol Parameter TA /c32 0/c113 C to /c14 70/c113 C, CL /c32 30 pF, RL /c32 50/c58 UnitsVDD /c32 2.5V /c114 0.2V; VDDQ /c32 2.5V /c114 0.2V Min Max fMAX Maximum Clock Frequency 200 MHz tW Pulse Duration, CK, CK HIGH or LOW (Figure 2) 2.5 ns tACT Differential Inputs Activation Time, 22 ns (Note 5) data inputs must be LOW after RESET HIGH (Figure 3) tINACT Differential Inputs De-activation Time, 22 ns(Note 5) data and clock inputs must be held at valid levels (not floating) after RESET LOW tS Setup Time, Fast Slew Rate (Note 6)(Note 7) (Figure 5) 0.65 ns Setup Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5) 0.9 tH Hold Time, Fast Slew Rate (Note 6)(Note 8) (Figure 5) 0.75 ns Hold Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5) 0.9 tREM Reset Removal Time (Figure 7) 10 ns tPHL , tPLH Propagation Delay CLK, CLK to Qn (Figure 4) 1.1 2.8 ns tPHL Propagation Delay RESET to Qn (Figure 6) 5.0 ns tSK(Pn-Pn) Output to Output Skew 200 ps Symbol Parameter TA /c32 0/c113 C to /c14 70/c113 C, CL /c32 30 pF, RL /c32 50/c58 UnitsVDD /c32 2.5V /c114 0.2V; VDDQ /c32 2.5V /c114 0.2V Min Max fMAX Maximum Clock Frequency 220 MHz tW Pulse Duration, CK, CK HIGH or LOW (Figure 2) 2.5 ns tACT Differential Inputs Activation Time, 22 ns (Note 5) data inputs must be LOW after RESET HIGH (Figure 3) tINACT Differential Inputs De-activation Time, 22 ns(Note 5) Data and Clock Inputs must be held at valid levels (not floating) after RESET LOW tS Setup Time, Fast Slew Rate (Note 9)(Note 12) (Figure 5) 0.65 ns Setup Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5) 0.75 tH Hold Time, Fast Slew Rate (Note 11)(Note 13) (Figure 5) 0.75 ns Hold Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5) 0.9 tREM Reset Removal Time (Figure 7) 10 ns tPHL , tPLH Propagation Delay CLK, CLK to Qn (Figure 4) 1.1 2.4 ns tPSS Propagation Delay Simultaneous Switching CLK, CLK to Qn (Note 14) 2.7 ns tPHL Propagation Delay RESET to Qn (Figure 6) 5.0 ns tSK(Pn-Pn) Output to Output Skew 200 ps

7 www.fairchildsemi.com SSTV16857  SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com