SSTVF16859 PHILIPS | Alldatasheet
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13-bit 1:2 SSTL_2 registered buffer for DDR Product data sheet 2004 Jul 12 INTEGRATED CIRCUITS
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
22004 Jul 12
FEATURES
- Stub-series terminated logic for 2.5 V VDD (SSTL_2)
- Designed for PC1600–PC2700 (at 2.5 V) and PC3200 (at 2.6 V)
applications
- Pin and function compatible with JEDEC standard SSTV16859
- Supports SSTL_2 signal inputs as per JESD 8–9
- Flow-through architecture optimizes PCB layout
- ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114.
- Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA.
- Supports efficient low power standby operation
- Full DDR solution when used with PCKVF857
- Available in 64-pin TSSOP, 96-ball LFBGA and 56-terminal HVQFN packages
DESCRIPTION
The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V for PC1600 – PC2700 applications or between 2.5 V and 2.7 V for PC3200 applications. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD , except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTVF16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK ) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going HIGH, and CK going LOW. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device has an asynchronous input pin (RESET), which when held to the LOW state, resets all registers and all outputs to the LOW state. The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF ) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET , the register will be cleared and the outputs will be driven LOW. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the outputs will remain LOW. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL /tPLH Propagation delay; CLK to Qn C L = 30 pF; VDD = 2.5 V 1.7 ns C I Input capacitance VCC = 2.5 V 2.8 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC 2 × fi + Σ (CL × VCC 2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC 2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER 56-Terminal Plastic HVQFN 0 °C to +70 °C SSTVF16859BS SOT684-1 64-Pin Plastic TSSOP 0 °C to +70 °C SSTVF16859DGG SOT646-1 96-Ball Plastic LFBGA 0 °C to +70 °C SSTVF16859EC SOT536-1
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 3
PIN NUMBER SYMBOL NAME AND FUNCTION 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16 Q13A–Q1A Data output 17, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31, Q13B–Q1B Data output 6, 18, 27, 33, 37, 38, 46, 47, 59, 60, 64 VDD Power supply voltage 7, 15, 26, 34, 39, 43, 50, 54, 58, 63 GND Ground 35, 36, 40, 41, 42, 44, 52, 53, 55, 56, 57, 61, D1–D13 Data input: clocked in on the crossing of the rising edge of CK and the falling edge of CK
45 VREF Input reference voltage
48, 49 CK, CK Positive and negative master clock input
51 RESET
Asynchronous reset input: resets registers and disables data and clock differential input receivers
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 4
V DDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B V Q5B Q4B Q3B Q2B Q1B DDQ VDDQ VDDI VDDQ D10 GND CK VREF VDDI VDDQ Q8B Q9A V Q10A Q11A Q12A Q13A D13 D12 D11 DDQ GND VDDQ VDDI VDDQ SW01040 CK RESET TERMINAL DESCRIPTION TERMINAL NUMBER SYMBOL NAME AND FUNCTION 1, 2, 3, 4, 5, 6, 7, 50, 51, 52, 53, 54, 56 Q13A–Q1A Data output 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22 Q13B–Q1B Data output 9, 17, 23, 27, 34, 44, 49, 55 VDDQ Power supply voltage 26, 33, 45 VDDI Power supply voltage 37, 48 GND Ground 24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, D1–D13 Data input: clocked in on the crossing of the rising edge of CK and the falling edge of CK
32 VREF Input reference voltage
35, 36 CK, CK Positive and negative master clock input Asynchronous reset input: resets registers and disables data and clock differential input receivers
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 5
A B C D E F G H J K L M N P R T Q12A Q10A Q8A Q6A Q4A Q2A Q1A Q12B Q10B Q8B Q6B Q4B Q2B Q13A Q11A Q9A Q7A Q5A Q3A Q13B Q11B Q9B Q7B Q5B Q3B Q1B GND GND GND GND GND GND GND GND GND GND GND GND GND V DDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ D13 D11 D12 D10 RESET CK CK V REF SW00944 LOGIC DIAGRAM SW00750 VREF D1 35 49CK 48CK 51RESET R to 12 other channels Q1A Q1B FUNCTION TABLE (each flip-flop) INPUTS OUTPUT RESET CK CK D Q H ↑ ↓ L L H ↑ ↓ H H H L or H L or H X Q 0 L X or floating X or floating X or floating L H = HIGH voltage level L = LOW voltage level ↓ = HIGH-to-LOW transition ↑ = LOW-to-HIGH transition X = Don’t care
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 6
ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER CONDITION LIMITS UNITSYMBOL PARAMETER CONDITION MIN MAX UNIT VDD Supply voltage range –0.5 +3.6 V VI Input voltage range Notes 2 and 3 –0.5 VDD + 0.5 V VO Output voltage range Notes 2 and 3 –0.5 VDD + 0.5 V IIK Input clamp current VI < 0 V or VI > VDD — ±50 mA IOK Output clamp current VO < 0 V or VO > VDD — ±50 mA IO Continuous output current VO = 0 V to VDD — ±50 mA Continuous current through each VDD or GND — ±100 mA Tstg Storage temperature range –65 +150 °C NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 3. This value is limited to 3.6 V maximum. 4. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. RECOMMENDED OPERATING CONDITIONS 1 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT VDD Supply voltage VDD — 2.7 V V Reference voltage PC1600–PC2700 1.15 1.25 1.35 V VREF g (VREF = VDD /2) PC3200 1.25 1.3 1.35 V VTT Termination voltage VREF – 40 mV VREF VREF + 40 mV V VI Input voltage 0 — VDD V VIH AC HIGH-level input voltage Data inputs VREF + 310 mV — — V VIL AC LOW-level input voltage Data inputs — — VREF – 310 mV V VIH DC HIGH-level input voltage Data inputs VREF + 150 mV — — V VIL DC LOW-level input voltage Data inputs — — VREF – 150 mV V VIH HIGH-level input voltage RESET 1.7 — VDD V VIL LOW-level input voltage 0.0 — 0.7 V VICR Common-mode input range CK, CK 0.97 — 1.53 V VID Differential input voltage CK, CK 360 — — mV IOH HIGH-level output current — — –16 mA IOL LOW-level output current — — 16 mA Tamb Operating free-air temperature range 0 — +70 °C NOTE: 1. The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW.
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 7
DC ELECTRICAL CHARACTERISTICS—PC1600–PC2700 Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = 0 °C to +70 °C UNIT MIN TYP MAX VIK II = –18 mA; VDD = 2.3 V — — –1.2 V VO HIGH-level output IOH = –100 µA; VDD = 2.3 to 2.7 V VDD – 0.2 — — V VOH votlage IOH = –16 mA; VDD = 2.3 V 1.95 — — V VO LOW-level output IOL = 100 µA; VDD = 2.3 to 2.7 V — — 0.2 V VOL voltage IOL = 16 mA; VDD = 2.3 V — — 0.35 V II All inputs VI = VDD or GND; VDD = 2.7 V — — ±5 µA Static standby RESET = GND — — 0.01 mA IDD Static operating RESET = VDD ; VI = VIH(AC) or VIL(AC) IO = 0, VDD = 2.7 V — — 25 mA Dynamic operating – clock only RESET = VDD ; VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. — 20 — µA/ clock MHz IDDD Dynamic operating – per each data input RESET = VDD ; VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. IO = 0, VDD = 2.7 V — 9 — µA/ clock MHz/ data input Data inputs VI = VREF ± 310 mV; VDD = 2.5 V 2.5 2.8 3.5 pF RESET VI = VDD or GND; VDD = 2.5 V — 2.4 3.5 pF
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 8
DC ELECTRICAL CHARACTERISTICS—PC3200 Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = 0 °C to +70 °C UNIT MIN TYP MAX VIK II = –18 mA; VDD = 2.5 V — — –1.2 V VO HIGH-level output IOH = –100 µA; VDD = 2.5 V to 2.7 V VDD – 0.2 — — VVOH voltage IOH = –16 mA; VDD = 2.5 V 1.95 — — V VO LOW-level output IOL = 100 µA; VDD = 2.5 to 2.7 V — — 0.2 VVOL voltage IOL = 16 mA; VDD = 2.5 V — — 0.35 V II All inputs VI = VDD or GND; VDD = 2.7 V — — ±5 µA Static standby RESET = GND — — 0.01 IDD Static operating RESET = VDD ; VI = VIH(AC) or VIL(AC) IO = 0, VDD = 2.7 V — — 45 mA Dynamic operating – clock only RESET = VDD ; VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. — 15 — µA/ clock MHz IDDD Dynamic operating – per each data input RESET = VDD ; VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. IO = 0, VDD = 2.7 V — 9 — µA/ clock MHz/ data input Data inputs VI = VREF ± 310 mV; VDD = 2.6 V 2.5 2.8 3.5 RESET VI = VDD or GND; VDD = 2.6 V — 2.4 3.5
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 9
TIMING REQUIREMENTS—PC1600–PC2700 Over recommended operating conditions; Tamb = 0 °C to +70 °C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER TEST CONDITIONS VDD = 2.5 V ± 0.2 V UNIT MIN MAX fclock Clock frequency — 200 MHz tw Pulse duration, CK, CK HIGH or LOW 2.5 — ns tact Differential inputs active time Notes 1, 2 — 22 ns tinact Differential inputs inactive time Notes 1, 3 — 22 ns t Setup time, fast slew rate (see Notes 4 and 6) Data before CK↑ CK ↓ 0.65 ns tsu Setup time, slow slew rate (see Notes 5 and 6) Data before CK ↑, CK ↓ 0.75 ns t Hold time, fast slew rate (see Notes 4 and 6) Data after CK↑ CK ↓ 0.75 ns th Hold time, slow slew rate (see Notes 5 and 6) Data after CK ↑, CK ↓ 0.9 ns NOTES: 1. This parameter is not necessarily production tested. 2. Data inputs must be below a minimum time of t act max, after RESET is taken HIGH. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken LOW. 4. For data signal input slew rate ≥ 1 V/ns. 5. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. 6. CK, CK signals input slew rates are ≥ 1 V/ns. TIMING REQUIREMENTS—PC3200 Over recommended operating conditions; Tamb = 0 °C to +70 °C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER TEST CONDITIONS VDD = 2.6 V ± 0.1 V UNIT MIN MAX fclock Clock frequency — 210 MHz tw Pulse duration, CK, CK HIGH or LOW 2.5 — ns tact Differential inputs active time Notes 1, 2 — 22 ns tinact Differential inputs inactive time Notes 1, 3 — 22 ns t Setup time, fast slew rate (see Notes 4 and 6) Data before CK↑ CK ↓ 0.65 nstsu Setup time, slow slew rate (see Notes 5 and 6) Data before CK ↑, CK ↓ 0.75 ns t Hold time, fast slew rate (see Notes 4 and 6) Data after CK↑ CK ↓ 0.65 nsth Hold time, slow slew rate (see Notes 5 and 6) Data after CK ↑, CK ↓ 0.8 ns NOTES: 1. This parameter is not necessarily production tested. 2. Data inputs must be below a minimum time of tact max, after RESET is taken HIGH. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken LOW. 4. For data signal input slew rate ≥ 1 V/ns. 5. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. 6. CK, CK signals input slew rates are ≥ 1 V/ns.
2004 Jul 12 10
Over recommended operating conditions; Tamb = 0 °C to +70 °C; VDD = 2.3 V – 2.7 V. Over recommended operating conditions; Tamb = 0 °C to +70 °C; VDD = 2.5 V – 2.7 V. Figure 1. Load circuitry
- CL includes probe and jig capacitance.
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 11
10%IDD tinact VDD VDD /2 tact 90% Waveform 1. Inputs active and inactive times (see Note 1) VREF VREF VIH VIL INPUT SW00753 tW Waveform 2. Pulse duration SW00754 VICR VICR VI(PP) TIMING INPUT OUTPUT tPLH tPHL VTT VOH VOL Waveform 3. Propagation delay times Input SW00755 VIH LVCMOS RESET VDD /2 VIL VOH VOL VTT tPHL Output Waveform 4. Propagation delay times VICR VI(PP) Timing input SW00756 VREF VREF VIL Input thtsu VIH Waveform 5. Setup and hold times NOTES: 1. IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , input slew rate = 1 V/ns ± 20% (unless otherwise specified). 3. The outputs are measured one at a time with one transition per measurement. 4. VTT = VREF = VDD /2 5. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 6. VIL = VREF – 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 7. tPLH and tPHL are the same as tpd.
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 12
TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm SOT646-1
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 13
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 14
HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm SOT684-1
Philips Semiconductors Product data sheet SSTVF1685913-bit 1:2 SSTL_2 registered buffer for DDR
2004 Jul 12 15
REVISION HISTORY
_1 20040712 Product data sheet (9397 750 13077). Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Date of release: 07-04 Document order number: 9397 750 13077 Philips Semiconductors Data sheet status[1] Objective data sheet Preliminary data sheet Product data sheet Product status[2] [3] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Level I II III