SSTVF16857

SN74SSTVF16857 TI | Alldatasheet

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Technical content

/C0083/C0078/C0055/C0052/C0083/C0083/C0084/C0086/C0070/C0049/C0054/C0056/C0053/C0055 /C0049/C0052/C0262/C0066/C0073/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082/C0069/C0068 /C0066/C0085/C0070/C0070/C0069/C0082 /C0087/C0073/C0084/C0072 /C0083/C0083/C0084/C0076/C0095/C0050 /C0073/C0078/C0080/C0085/C0084/C0083 /C0065/C0078/C0068 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES411B – AUGUST 2002 – REVISED APRIL 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Member of the Texas Instruments Widebus  Family /C0068Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200 /C0068Pinout and Functionality Compatible With JEDEC Standard SSTV16857 /C0068600 ps Faster (Simultaneous Switching) Than JEDEC Standard SSTV16857 in PC2700 DIMM Applications /C0068Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated DIMM Load /C0068Outputs Meet SSTL_2 Class I Specifications /C0068Supports SSTL_2 Data Inputs /C0068Differential Clock (CLK and CLK) Inputs /C0068Supports LVCMOS Switching Levels on the RESET Input /C0068RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low /C0068Flow-Through Architecture Optimizes PCB Layout /C0068Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II /C0068ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) description/ordering information This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications. The SN74SSTVF16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING 0°C to 70°C TSSOP – DGG Tape and reel SN74SSTVF16857GR SSTVF16857 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright  2003, Texas Instruments Incorporated Widebus is a trademark of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DGG PACKAGE (TOP VIEW) GND VDDQ GND VDDQ VDDQ GND V DDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 GND V CC CLK CLK V CC GND V REF RESET D10 D11 D12 V CC GND D13 D14 /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0078/C0055/C0052/C0083/C0083/C0084/C0086/C0070/C0049/C0054/C0056/C0053/C0055 /C0049/C0052/C0262/C0066/C0073/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082/C0069/C0068 /C0066/C0085/C0070/C0070/C0069/C0082 /C0087/C0073/C0084/C0072 /C0083/C0083/C0084/C0076/C0095/C0050 /C0073/C0078/C0080/C0085/C0084/C0083 /C0065/C0078/C0068 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES411B – AUGUST 2002 – REVISED APRIL 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued) The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF ) inputs are allowed. In addition, when RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. FUNCTION TABLE INPUTS OUTPUT RESET CLK CLK D OUTPUT Q H ↑ ↓ H H H ↑↓ LL H L or H L or H X Q 0 L X, or floatingX, or floatingX, or floating L logic diagram (positive logic) R To 13 Other Channels RESET 39CLK 38CLK 35VREF 48D1 One of 14 Channels

/C0083/C0078/C0055/C0052/C0083/C0083/C0084/C0086/C0070/C0049/C0054/C0056/C0053/C0055 /C0049/C0052/C0262/C0066/C0073/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082/C0069/C0068 /C0066/C0085/C0070/C0070/C0069/C0082 /C0087/C0073/C0084/C0072 /C0083/C0083/C0084/C0076/C0095/C0050 /C0073/C0078/C0080/C0085/C0084/C0083 /C0065/C0078/C0068 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES411B – AUGUST 2002 – REVISED APRIL 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) MIN NOM MAX UNIT VCC Supply voltage VDDQ 2.7 V V O tp t s ppl oltage PC1600, PC2100, PC2700 2.3 2.7 VVDDQ Output supply voltage PC3200 2.5 2.7 V V Reference voltage (V V /2) PC1600, PC2100, PC2700 1.15 1.25 1.35 VVREF Reference voltage (VREF = VDDQ /2) PC3200 1.25 1.3 1.35 V VI Input voltage 0 VCC V VIH AC high-level input voltage Data inputs VREF +310mV V VIL AC low-level input voltage Data inputs VREF –310mV V VIH DC high-level input voltage Data inputs VREF +150mV V VIL DC low-level input voltage Data inputs VREF –150mV V VIH High-level input voltage RESET 1.7 V VIL Low-level input voltage RESET 0.7 V VICR Common-mode input voltage range CLK, CLK 0.97 1.53 V VI(PP) Peak-to-peak input voltage CLK, CLK 360 mV IOH High-level output current –16 mA IOL Low-level output current 16 mA TA Operating free-air temperature 0 70 °C NOTE 4: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

/C0083/C0078/C0055/C0052/C0083/C0083/C0084/C0086/C0070/C0049/C0054/C0056/C0053/C0055 /C0049/C0052/C0262/C0066/C0073/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082/C0069/C0068 /C0066/C0085/C0070/C0070/C0069/C0082 /C0087/C0073/C0084/C0072 /C0083/C0083/C0084/C0076/C0095/C0050 /C0073/C0078/C0080/C0085/C0084/C0083 /C0065/C0078/C0068 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES411B – AUGUST 2002 – REVISED APRIL 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics for PC1600, PC2100, and PC2700 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC AND VDDQ MIN TYP † MAX UNIT VIK II = –18 mA 2.3 V –1.2 V V IOH = –100 µA 2.3 V to 2.7 VVDDQ –0.2 VVOH IOH = –8 mA 2.3 V 1.95 V V IOL = 100 µA 2.3 V to 2.7 V 0.2 VVOL IOL = 8 mA 2.3 V 0.35 V II All inputs VI = VCC or GND 2.7 V ±5 µA I Static standby RESET = GND I0 27V 10 µA ICC Static operating RESET = VCC , VI = VIH(AC) or VIL(AC) IO = 0 2.7 V 8 25 mA Dynamic operating – clock only RESET = VCC , VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle 28 µA/ MHz ICCD Dynamic operating – per each data input RESET = VCC , VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle IO = 0 2.5 V µA/ clock MHz/ D input Data inputs VI = VREF ± 310 mV 2.5 3 3.5 C i CLK, CLK VICR = 1.25 V, VI(PP) = 360mV 2.5 V 2.5 3 3.5 pFC i RESET VI = VCC or GND 2.5 V 2.3 3 3.5 F † All typical values are at VCC = 2.5 V, TA = 25°C. electrical characteristics for PC3200 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC AND VDDQ MIN TYP † MAX UNIT VIK II = –18 mA 2.5 V –1.2 V V IOH = –100 µA 2.5 V to 2.7 VVDDQ –0.2 VVOH IOH = –8 mA 2.5 V 1.95 V V IOL = 100 µA 2.5 V to 2.7 V 0.2 VVOL IOL = 8 mA 2.5 V 0.35 V II All inputs VI = VCC or GND 2.7 V ±5 µA I Static standby RESET = GND I0 27V 10 µA ICC Static operating RESET = VCC , VI = VIH(AC) or VIL(AC) IO = 0 2.7 V 8 25 mA Dynamic operating – clock only RESET = VCC , VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle 28 µA/ MHz ICCD Dynamic operating – per each data input RESET = VCC , VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle IO = 0 2.6 V µA/ clock MHz/ D input Data inputs VI = VREF ± 310 mV 2.5 3 3.5 C i CLK, CLK VICR = 1.25 V, VI(PP) = 360mV 2.6 V 2.5 3 3.5 pFC i RESET VI = VCC or GND 2.6 V 2.3 3 3.5 F † All typical values are at VCC = 2.6 V, TA = 25°C.

/C0083/C0078/C0055/C0052/C0083/C0083/C0084/C0086/C0070/C0049/C0054/C0056/C0053/C0055 /C0049/C0052/C0262/C0066/C0073/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082/C0069/C0068 /C0066/C0085/C0070/C0070/C0069/C0082 /C0087/C0073/C0084/C0072 /C0083/C0083/C0084/C0076/C0095/C0050 /C0073/C0078/C0080/C0085/C0084/C0083 /C0065/C0078/C0068 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES411B – AUGUST 2002 – REVISED APRIL 2003 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V† VCC = 2.6 V ± 0.1 V† UNIT MIN MAX MIN MAX UNIT fclock Clock frequency 250 250 MHz tw Pulse duration, CLK, CLK high or low 2 2 ns tact Differential inputs active time (see Note 5) 22 22 ns tinact Differential inputs inactive time (see Note 6) 22 22 ns t Set p time Fast slew rate (see Notes 7 and 9) Dt bf C L K ↑ CLK ↓ 0.75 0.75 nstsu Setup time Slow slew rate (see Notes 8 and 9)Data before CLK↑, CLK↓ 0.9 0.9 ns th Hold time Fast slew rate (see Notes 7 and 9) Data after CLK↑ CLK ↓ 0.75 0.75 nsth Hold time Slow slew rate (see Notes 8 and 9) Data after CLK↑, CLK↓ 0.9 0.9 ns † For this test condition, VDDQ always is equal to VCC . NOTES: 5. V REF must be held at a valid input level and data inputs must be held low for a minimum time of tact max, after RESET is taken high. 6. VREF , data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low. 7. For data signal input slew rate ≥1 V/ns. 8. For data signal input slew rate ≥0.5 V/ns and <1 V/ns. 9. CLK, CLK signals input slew rates are ≥1 V/ns. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V† VCC = 2.6 V ± 0.1 V† UNITPARAMETER (INPUT) (OUTPUT) MIN MAX MIN MAX UNIT fmax 250 250 MHz tpd‡ CLK and CLK Q 1.1 2.6 1.1 2.6 ns tPHL RESET Q 5 5 ns † For this test condition, VDDQ always is equal to VCC . ‡ Single bit switching

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTES: A. C L includes probe and jig capacitance. B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. input slew rate = 1 V/ns ±20% (unless otherwise noted). D. The outputs are measured one at a time with one transition per measurement. F. V IH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input. G. V IL = VREF – 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) SN74SSTVF16857GR Active Production TSSOP (DGG) | 48 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 SSTVF16857 SN74SSTVF16857GR.B Active Production TSSOP (DGG) | 48 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR 0 to 70 SSTVF16857 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2017 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74SSTVF16857GR TSSOP DGG 48 2000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 12-May-2017 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 8.3

7.9 TYP

1.2 1.0 46X 0.5 48X 0.27 0.17 11.5 (0.15) TYP 0 - 8 0.15 0.05 0.25 GAGE PLANE 0.75 0.50 A 12.6 12.4 NOTE 3 B 6.2 6.0 4214859/B 11/2020 TSSOP - 1.2 mm max heightDGG0048A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 1 48

0.08 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.350

www.ti.com EXAMPLE BOARD LAYOUT (7.5)

0.05 MAX

0.05 MIN

48X (1.5) 48X (0.3) 46X (0.5) (R0.05) TYP 4214859/B 11/2020 TSSOP - 1.2 mm max heightDGG0048A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:6X 24 25 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (7.5) 46X (0.5) 48X (0.3) 48X (1.5) (R0.05) TYP 4214859/B 11/2020 TSSOP - 1.2 mm max heightDGG0048A SMALL OUTLINE PACKAGE NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SYMM SYMM 24 25 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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