SSTV16859

SSTV16859 FAIRCHILD | Alldatasheet

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I Compliant with DDR-I registered module specifications I Operates at 2.5V ± 0.2V VDD I SSTL-2 compatible input structure I SSTL-2 compliant output structure I Differential SSTL-2 compatible clock inputs I Low power mode when device is reset I Industry standard 64 pin TSSOP package I Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Ordering Code: Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Order Number Package Number Package Description SSTV16859G (Note 1)(Note 2) BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide SSTV16859MTD (Note 2) MTD64 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

www.fairchildsemi.com 2 SSTV16859 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) Pin Descriptions FBGA Pin Assignments Truth Table L = Logic LOW H = Logic HIGH X = Don’t Care but not floating unless noted ↑ = LOW-to-HIGH Clock Transition ↓ = HIGH-to-LOW Clock Transition Qn-1 = Output Remains in Previously Clocked State Pin Name Description Q1A-Q13A SSTL-2 Compatible Register Outputs Q1B-Q13B D1-D13 SSTL-2 Compatible Register Inputs RESET Asynchronous LVCMOS Reset Input CK Positive Master Clock Input CK Negative Master Clock Input VREF Voltage Reference Pin for SSTL level inputs VDDQ Power Supply Voltage for Output Signals VDD Power Supply Voltage for Inputs NC Electrically Isolated No Connect 12345 6 A NC NC NC NC NC NC B Q12A Q13A GND GND NC NC C Q10A Q11A GND GND NC NC D Q8A Q9A VDDQ VDDQ D13 D12 E Q6A Q7A VDDQ VDD D11 D10 F Q4A Q5A VDDQ VDD D9 D8 G Q2A Q3A GND GND D 7 RESET H Q1A Q13B GND GND NC CK J Q12B Q11B GND V REF NC CK K Q10B Q9B VDDQ VDD NC NC L Q8B Q7B VDDQ VDD D5 D6 M Q6B Q5B VDDQ VDDQ D3 D4 N Q4B Q3B GND GND D 1 D2 P Q2B Q1B GND GND NC NC R NC NC NC NC NC NC T NC NC NC NC NC NC RESET Dn CK CK Qn L X or Floating X or Floating X or Floating L HL ↑↓ L HH ↑↓ H HXLH Q n-1 HXHL Q n-1

3 www.fairchildsemi.com SSTV16859 Functional Description The SSTV16859 is a 13-bit dual register with SSTL-2 com- patible inputs and outputs. Input data is transferred to out- put data on the rising edge of the differential clock pair. When the RESET signal is asserted LOW all outputs are placed into the LOW logic state and all input comparators are disabled for power savings. Output glitches are pre- vented by disabling the internal registers more quickly than the input comparators. When RESET is removed, the sys- tem designer must insure the clock and data inputs to the device are stable during the rising transition of the RESET signal. The SSTL-2 data inputs transition based on the value of VREF. VREF is a stable system reference used for setting the trip point of the input buffers of the SSTV16859 and other SSTL-2 compatible devices. The RESET signal is a standard CMOS compatible input and is not referenced to the VREF signal. Logic Diagram For n = 1 to 13

www.fairchildsemi.com 4 SSTV16859 Absolute Maximum Ratings(Note 3) Recommended Operating Conditions (Note 5) Note 3: The “Absolute Maximum Ratings ” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions ” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: The RESET input of the device must be held at V DD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is asserted LOW. Supply Voltage (VDDQ) −0.5V to +3.6V Supply Voltage (VDD) −0.5V to +3.6V Reference Voltage (VREF) −0.5V to +3.6V Input Voltage (VI) −0.5V to VDD +0.5V Output Voltage (VO) Outputs Active (Note 4) −0.5V to VDDQ + 0.5V DC Input Diode Current (IIK) VI < 0V −50 mA VI > VDD +50 mA DC Output Diode Current (IOK) VO < 0V −50 mA VO > VDDQ +50 mA DC Output Source/Sink Current (IOH/IOL) ±50 mA DC VDD or Ground Current per Supply Pin (IDD or Ground) ±100 mA Storage Temperature Range (Tstg) −65°C to +150°C ESD (Human Body Model) ≥ 7000V Power Supply (VDDQ) 2.3V to 2.7V Power Supply (VDD) Operating Range V DDQ to 2.7V Reference Supply (VREF = VDDQ/2) 1.15 to 1.35 Termination Voltage (VTT)V REF ± 40 mV Input Voltage 0 to V DD Output Voltage (VO) Output in Active States 0V to V DDQ Output Current IOH/IOL VDD = 2.3V to 2.7V ±20 mA Free Air Operating Temperature (TA)0 °C to +70°C Symbol Parameter Conditions VDD Min Typ Max Units (V) VIKL Input LOW Clamp Voltage I I = −18 mA 2.3 −1.2 V VIKH Input HIGH Clamp Voltage I I = +18 mA 2.3 3.5 V VIH-AC AC HIGH Level Input Voltage Data Inputs V REF+310mV V VIL-AC AC LOW Level Input Voltage Data Inputs V REF−310mV V VIH-DC DC HIGH Level Input Voltage Data Inputs V REF+150mV V VIL-DC DC LOW Level Input Voltage Data Inputs V REF−150mV V VIH HIGH Level Input Voltage RESET 1.7 V VIL LOW Level Input Voltage RESET 0.7 V VICR Common Mode Input Voltage Range CK, CK 0.97 1.53 V VI(PP) Peak to Peak Input Voltage CK, CK 360 mV VOH HIGH Level Output Voltage I OH = −100 µA 2.3 to 2.7 V DD − 0.2 V IOH = −16 mA 2.3 1.95 VOL LOW Level Output Voltage I OL = 100 µA 2.3 to 2.7 0.2 V IOL = 16 mA 2.3 0.35 II Input Leakage Current V I = VDD or GND 2.7 ±5.0 µA IDD Static Standby RESET = GND, IO = 0 2.7 10 µA Static Operating RESET = VDD, IO = 0 25 mA VI = VIH(AC) or VIL(AC) IDDD Dynamic Operating Current RESET = VDD, IO = 0 2.7 µA/MHzClock Only V I = VIH(AC) or VIL(AC) 120 CK, CK Duty Cycle 50% Dynamic Operating Current RESET = VDD, IO = 0 µA/MHz per Data Input V I = VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% 15 Data Input = ½ Clock Rate 50% Duty Cycle

5 www.fairchildsemi.com SSTV16859 Note 6: Refer to Figure 1 through Figure 7. Note 7: This parameter is not production tested. Note 8: For data signal input slew rate ≥ 1 V/ns. Note 9: For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. Note 10: For CK, CK signals input slew rates are ≥ 1 V/ns. Capacitance (Note 11) Note 11: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested. Symbol Parameter Conditions VDD Min Typ Max Units (V) ROH Output HIGH On Resistance I OH = −20 mA 2.3 to 2.7 7 20 Ω ROL Output LOW On Resistance I OL = 20 mA 2.3 to 2.7 7 20 Ω RO∆ | ROH - ROL |I O = 20 mA, TA = 25°C2 . 5 4 Ω Symbol Parameter TA = 0°C to +70°C, CL = 30 pF, RL = 50Ω UnitsVDD = 2.5V ± 0.2V; VDDQ = 2.5V ± 0.2V Min Typ Max fMAX Maximum Clock Frequency 200 MHz tW Pulse Duration, CK, CK HIGH or LOW (Figure 2) 2.5 ns tACT Differential Inputs Activation Time, 22 ns (Note 7) data inputs must be LOW after RESET HIGH (Figure 3) tINACT Differential Inputs De-activation Time, 22 ns(Note 7) data and clock inputs must be held at valid levels (not floating) after RESET LOW tS Setup Time, Fast Slew Rate (Note 8)(Note 9) (Figure 5) 0.75 ns Setup Time, Slow Slew Rate (Note 9)(Note 10) (Figure 5) 0.9 tH Hold Time, Fast Slew Rate (Note 8)(Note 10) (Figure 5) 0.75 ns Hold Time, Slow Slew Rate (Note 9)(Note 10) (Figure 5) 0.9 tREM Reset Removal Time (Figure 7) 10 ns tPHL, tPLH Propagation Delay CK, CK to Qn (Figure 4) 1.1 2.8 ns tPHL Propagation Delay RESET to Qn (Figure 6) 5.0 ns Symbol Parameter Min Typ Max Units Conditions CIN Data Pin Input Capacitance 2.2 3.2 pF V DD = 2.5V, VI = VREF ± 310 mV CK, CK - Input Capacitance 2.2 3.2 pF V DD = 2.5V, VICR = 1.25, VI(PP) = 360 mV RESET 2.3 3.3 pF V DD = 2.5V, VI = VDD or GND

7 www.fairchildsemi.com SSTV16859 Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

www.fairchildsemi.com 8 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com