SSTV16857 PHILIPS | Alldatasheet
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Technical content
/C0080 /C0115 /C0111/C0110/C0111 /C0115 SSTV16857 14-bit SSTL_2 registered driver with differential clock inputs Product data Supersedes data of 2002 Jun 05
2002 Sep 27
Philips Semiconductors Product data SSTV1685714-bit SSTL_2 registered driver with differential clock inputs
22002 Sep 27
FEATURES
- Stub-series terminated logic for 2.5 V VDDQ (SSTL_2)
- Optimized for DDR (Double Data Rate) SDRAM applications
- Inputs compatible with JESD8–9 SSTL_2 specifications.
- Flow-through architecture optimizes PCB layout
- ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114.
- Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA.
- Same form, fit, and function as SSTL16877
- Full DDR 200/266 solution @ 2.5 V when used with PCKV857
- See SSTV16856 for driver/buffer version with mode select.
- Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages
DESCRIPTION
The SSTV16857 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC . Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ . The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET ) asynchronously resets all registers to zero. The SSTV16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTV16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well. PIN CONFIGURATION 20 29 V DDQ Q10 D12 D11 D10 RESET VREF GND VCC CLK+ CLK– V CC GND 24 25 28V DDQ Q14 D14 D13 GND VCC GND GND VDDQ VDDQ GND VDDQ GND Q11 Q12 GND Q13 SW00685 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf /C01182.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL /tPLH Propagation delay; CLK to Qn C L = 30 pF; VDDQ = 2.5 V 2.4 ns C I Input capacitance VCC = 2.5 V 2.9 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER 48-Pin Plastic TSSOP 0 to +70 °C SSTV16857DGG SOT362-1 48-Pin Plastic TSSOP (TVSOP) 0 to +70 °C SSTV16857DGV SOT480-1 56-Ball Plastic VFBGA 0 to +70 °C SSTV16857EV SOT702-1
Philips Semiconductors Product data SSTV1685714-bit SSTL_2 registered driver with differential clock inputs
2002 Sep 27 3
PIN NUMBER SYMBOL NAME AND FUNCTION
34 RESET
(Active LOW) 48, 47, 44, 43, 42, 41, 40, 33, 32, 31, 30, 29, 26, 25 D1 – D14 SSTL_2 data inputs 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 Q1 – Q14 SSTL_2 data outputs
35 VREF SSTL_2 input reference level
3, 8, 13, 17, 22, 27, 36, 46 GND Ground (0 V) 28, 37, 45 VCC Positive supply voltage 4, 9, 12, 16, 21VDDQ Output supply voltage CLK+ CLK– Differential clock inputs FUNCTION TABLE INPUTS OUTPUT RESET CLK CLK D Q L X X X L H ↓ ↑ H H H ↓ ↑ L L H L or H L or H X Q 0 H = High voltage level L = High voltage level ↓ = High-to-Low transition ↑ = Low-to-High transition X = Don’t care LOGIC DIAGRAM SW00763 REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER RESET VREF D10 D11 D12 D13 D14 CLK+ CLK– Q10 Q11 Q12 Q13 Q14
Philips Semiconductors Product data SSTV1685714-bit SSTL_2 registered driver with differential clock inputs
2002 Sep 27 4
A B C D E F G H J K SW00952 Q1 NC NC NC NC NC NC NC NC VCC VCC VCC VCC VCC VCC VCC VCCGND GND GND GND GND GND GND GNDQ2 Q3Q4 Q5 Q10Q11 Q12 Q13 Q14 D3 D4D5 D6 D7 D8D9 D10 D11 D12 D13 D14 RESET CLK+ CLK– VREF ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER CONDITION LIMITS UNITSYMBOL PARAMETER CONDITION MIN MAX UNIT VCC DC supply voltage –0.5 +4.6 V IIK DC input diode current VI < 0 — –50 mA VI DC input voltage3 –0.5 VDDQ + 0.5 V IOK DC output diode current VO < 0 — –50 mA VOUT DC output voltage3 –0.5 VDDQ + 0.5 V IO DC output current VO = 0 to VDDQ — ±50 mAIOUT Continuous current4 VCC , VDDQ , or GND — ±100 mA Tstg Storage temperature range2 –65 +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. The continuous current at VCC , VDDQ , or GND should not exceed ±100 mA.
Philips Semiconductors Product data SSTV1685714-bit SSTL_2 registered driver with differential clock inputs
2002 Sep 27 5
RECOMMENDED OPERATING CONDITIONS 1 SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC Supply voltage 2.3 2.5 2.7 V VDDQ Output supply voltage 2.3 2.5 2.7 V VREF Reference voltage (VREF = 0.5 x VDDQ ) 1.15 1.25 1.35 V VTT Termination voltage VREF – 40 mV VREF VREF + 40 mV V VI Input voltage 0 — VCC V VIH AC HIGH-level input voltage All inputs VREF + 350 mV — — V VIL AC LOW-level input voltage All inputs — — VREF – 350 mV V VIH DC HIGH-level input voltage All inputs VREF + 180 mV — VDDQ + 0.5 V V VIL DC LOW-level input voltage All inputs VSS – 0.5 V — VREF – 180 mV V IOH HIGH-level output current — — –20 mA IOL LOW-level output current — — 20 mA Tamb Operating free-air temperature range 0 — 70 °C NOTE: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = 0 to +70 °C UNIT MIN TYP 2 MAX VIK I/O supply voltage VCC = 2.3 V; II = –18 mA — — –1.2 V HIGH level output voltage VCC = 2.3 V to 2.7 V; IOH = –100 µA VCC – 0.2 — — V VOH HIGH level output voltage V =23V ;I =1 6 m A 19 5VCC = 2.3 V; IOH = –16 mA 1.95 — — VO LOW level output voltage VCC = 2.3 V to 2.7 V; IOL = 100 µA — — 0.2 VVOL LOW level output voltage VCC = 2.3 V; IOL = 16 mA — — 0.35 V VCMR CLK, CLK Common mode range for reliable performance 0.97 — 1.53 V VPP CLK, CLK Minimum peak-to-peak input to ensure logic state 360 — — mV Data inputs RESET VCC = 2.7 V; VI = 1.7 V or 0.8 V V =11 5Vo r13 5V — 0.01 ±5 µAData inputs, RESET VCC = 2.7 V; VI = 2.7 V or 0 V VREF = 1.15 V or 1.35 V — 0.01 ±5 µA II CLK CLK VCC = 2.7 V; VI = 1.7 V or 0.8 V V =11 5Vo r13 5V — 0.05 ±5 µACLK , CLK VCC = 2.7 V; VI = 2.7 V or 0 V VREF = 1.15 V or 1.35 V — 0.05 ±5 µA VREF VCC = 2.7 V VREF = 1.15 V or 1.35 V — 0.05 ±5 µA ICC Quiescent supply current CLK and CLK in opposite VCC = 2.7 V; VI = 1.7 V or 0.8 VRESET = GND — 0.5 10 µA ICC CLK and CLK in opposite state1 VCC = 2.7 V; VI = 2.7 V or 0 V RESET = VCC — 10 25 mA NOTES: 1. When CLK and CLK are HIGH, typical ICC = 25 mA. 2. All typical values are at VCC = 2.5 V and Tamb = 25 °C (unless otherwise specified).
Philips Semiconductors Product data SSTV1685714-bit SSTL_2 registered driver with differential clock inputs
2002 Sep 27 6
Over recommended operating conditions; Tamb = 0 to +70 °C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER TEST CONDITIONS VCC = 2.5 V ±0.2 V UNIT MIN MAX fclock Clock frequency — 200 MHz tw Pulse duration, CLK, CLK HIGH or LOW 1.0 — ns t Setup time Data before CLK↑, CLK↓ 0.2 — nstsu Setup time RESET HIGH before CLK↑, CLK↓ 0.8 — ns th Hold time 0.75 — ns SWITCHING CHARACTERISTICS Over recommended operating conditions; Tamb = 0 to +70 °C; VDDQ = 2.3 – 2.7 V and VDDQ does not exceed VCC. Class I, VREF = VTT = VDDQ × 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS SYMBOL FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ±0.2 V UNIT(INPUT) (OUTPUT) MIN MAX fmax Maximum clock frequency 200 — MHz tPLH /tPHL CLK and CLK Q 1.0 2.8 ns tPHL RESET Q 2.0 4.0 ns 184/200-pin DDR SDRAM DIMM The PLL clock distribution device and SSTV registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SW00686 SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SSTV16857 PCKV857SSTV16857 FRONT SIDE
2002 Sep 27 7
Waveform 2. Propagation delay RESET to output. The outputs are measured one at a time with one transition per measurement. Figure 1. Load circuitry
Philips Semiconductors Product data SSTV1685714-bit SSTL_2 registered driver with differential clock inputs
2002 Sep 27 8
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
Philips Semiconductors Product data SSTV1685714-bit SSTL_2 registered driver with differential clock inputs
2002 Sep 27 9
UNIT A 1 A 2 A 3 b p D (1) E (2) H E L pce L Q Z (1)ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE 97–03–20 99–12–27 IEC JEDEC EIAJ mm 0.15 0.05 0.95 0.85 0.23 0.13 0.20 0.09 9.80 9.60 4.50 4.30 6.60 6.20 0.40 0.40 0.30 o o0.07 0.080.201.00 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.70 0.50 SOT480–1 MO–153 0.25 0.40 0.10 w M b pe 1 24 48 25 Z pin 1 index θ A A 1 A 2 L p Q detail X L (A )3 H E E c v M A X A D y 0 2.5 5 mm scale A max. 1.10 TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm SOT480-1
Philips Semiconductors Product data SSTV1685714-bit SSTL_2 registered driver with differential clock inputs
2002 Sep 27 10
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm SOT702-1
Philips Semiconductors Product data SSTV1685714-bit SSTL_2 registered driver with differential clock inputs
2002 Sep 27 11
REVISION HISTORY
_6 2002 Sep 27 Product data (9397 750 10412); sixth version supersedes Product data fifth version, 2002 Jun 05. Engineering Change Notice: 853 2224 28989 (2002 Sep 26). Modifications: _5 2002 Jun 05 Product data (9397 750 09942); fifth version.
Philips Semiconductors Product data SSTV1685714-bit SSTL_2 registered driver with differential clock inputs
2002 Sep 27 12
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 09-02 Document order number: 9397 750 10412 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status[1] Objective data Preliminary data Product data Product status[2] Development Qualification Production Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Data sheet status [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.