SSTV16857

SN74SSTV16857_13 TI1 | Alldatasheet

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Technical content

/C0083/C0078/C0055/C0052/C0083/C0083/C0084/C0086/C0049/C0054/C0056/C0053/C0055 /C0049/C0052/C0262/C0066/C0073/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082/C0069/C0068 /C0066/C0085/C0070/C0070/C0069/C0082 /C0087/C0073/C0084/C0072 /C0083/C0083/C0084/C0076/C0095/C0050 /C0073/C0078/C0080/C0085/C0084/C0083 /C0065/C0078/C0068 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Member of the Texas Instruments Widebus  Family /C0068Supports SSTL_2 Data Inputs /C0068Outputs Meet SSTL_2 Class II Specifications /C0068Differential Clock (CLK and CLK) Inputs /C0068Supports LVCMOS Switching Levels on the RESET Input /C0068RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low /C0068Flow-Through Architecture Optimizes PCB Layout /C0068Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II /C0068ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

description

This 14-bit registered buffer is designed for 2.3-V to 2.7-V V CC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET ) input. All outputs are SSTL_2, Class II compatible. The SN74SSTV16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled and undriven (floating) data, clock, and reference voltage (VREF ) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING 0°C to 70°C TSSOP – DGG Tape and reel SN74SSTV16857DGGR SSTV16857 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright  2002, Texas Instruments Incorporated Widebus is a trademark of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DGG PACKAGE (TOP VIEW) GND VDDQ GND VDDQ VDDQ GND VDDQ GND Q10 Q11 Q12 VDDQ GND Q13 Q14 GND V CC CLK CLK V CC GND V REF RESET D10 D11 D12 V CC GND D13 D14 /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Not Recommended for New Designs

/C0083/C0078/C0055/C0052/C0083/C0083/C0084/C0086/C0049/C0054/C0056/C0053/C0055 /C0049/C0052/C0262/C0066/C0073/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082/C0069/C0068 /C0066/C0085/C0070/C0070/C0069/C0082 /C0087/C0073/C0084/C0072 /C0083/C0083/C0084/C0076/C0095/C0050 /C0073/C0078/C0080/C0085/C0084/C0083 /C0065/C0078/C0068 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Q H ↑ ↓ H H H ↑↓ LL H L or H L or H X Q 0 L X, or floatingX, or floatingX, or floating L logic diagram (positive logic) R To 13 Other Channels RESET 39CLK 38CLK 35VREF 48D1 One of 14 Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. Not Recommended for New Designs

/C0083/C0078/C0055/C0052/C0083/C0083/C0084/C0086/C0049/C0054/C0056/C0053/C0055 /C0049/C0052/C0262/C0066/C0073/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082/C0069/C0068 /C0066/C0085/C0070/C0070/C0069/C0082 /C0087/C0073/C0084/C0072 /C0083/C0083/C0084/C0076/C0095/C0050 /C0073/C0078/C0080/C0085/C0084/C0083 /C0065/C0078/C0068 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 4) MIN NOM MAX UNIT VCC Supply voltage VDDQ 2.7 V VDDQ Output supply voltage 2.3 2.7 V VREF Reference voltage (VREF = VDDQ /2) 1.15 1.25 1.35 V VTT Termination voltage VREF –40mV VREF VREF +40mV V VI Input voltage 0 VCC V VIH AC high-level input voltage Data inputs VREF +310mV V VIL AC low-level input voltage Data inputs VREF –310mV V VIH DC high-level input voltage Data inputs VREF +150mV V VIL DC low-level input voltage Data inputs VREF –150mV V VIH High-level input voltage RESET 1.7 V VIL Low-level input voltage RESET 0.7 V VICR Common-mode input voltage range CLK, CLK 0.97 1.53 V VI(PP) Peak-to-peak input voltage CLK, CLK 360 mV IOH High-level output current –20 mAIOL Low-level output current 20 mA TA Operating free-air temperature 0 70 /C0095C NOTE 4: The RESET input of the device must be held at a valid logic level (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC AND VDDQ MIN TYP † MAX UNIT VIK II = –18 mA 2.3 V –1.2 V V IOH = –100 µA 2.3 V to 2.7 VVDDQ –0.2 VVOH IOH = –16 mA 2.3 V 1.95 V V IOL = 100 µA 2.3 V to 2.7 V 0.2 VVOL IOL = 16 mA 2.3 V 0.35 V II All inputs VI = VCC or GND 2.7 V ±5 µA I Static standby RESET = GND I0 27V 10 µA ICC Static operating RESET = VCC , VI = VIH(AC) or VIL(AC) IO = 0 2.7 V 8 56 mA Dynamic operating – clock only RESET = VCC , VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle 28 µA/ MHz ICCD Dynamic operating – per each data input RESET = VCC , VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle IO = 0 2.5 V µA/ clock MHz/ D input rOH Output high IOH = –20 mA 2.3 V to 2.7 V 7 20 Ω rOL Output low IOL = 20 mA 2.3 V to 2.7 V 7 20 Ω rO(∆) rOH – rOL  IO = 20 mA, TA = 25°C 2.5 V 6 Ω Data inputs VI = VREF ± 310 mV 2.5 3 3.5 C i CLK, CLK VICR = 1.25 V, VI(PP) = 360 mV 2.5 V 2.5 3 3.5 pFC i RESET VI = VCC or GND 2.5 V 2.5 3 3.5 F † All typical values are at VCC = 2.5 V, TA = 25°C. Not Recommended for New Designs

/C0083/C0078/C0055/C0052/C0083/C0083/C0084/C0086/C0049/C0054/C0056/C0053/C0055 /C0049/C0052/C0262/C0066/C0073/C0084 /C0082/C0069/C0071/C0073/C0083/C0084/C0069/C0082/C0069/C0068 /C0066/C0085/C0070/C0070/C0069/C0082 /C0087/C0073/C0084/C0072 /C0083/C0083/C0084/C0076/C0095/C0050 /C0073/C0078/C0080/C0085/C0084/C0083 /C0065/C0078/C0068 /C0079/C0085/C0084/C0080/C0085/C0084/C0083 SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V ± 0.2 V† UNIT MIN MAX UNIT fclock Clock frequency 200 MHz tw Pulse duration CLK, CLK high or low 2.5 ns tact Differential inputs active time (see Note 5) 22 ns tinact Differential inputs inactive time (see Note 6) 22 ns t Set p time Fast slew rate (see Notes 7 and 9) Dt bf C L K ↑ CLK ↓ 0.75 nstsu Setup time Slow slew rate (see Notes 8 and 9) Data before CLK↑, CLK↓ 0.9 ns t Hold time Fast slew rate (see Notes 7 and 9) D t ft CLK↑ CLK ↓ 0.75 nsth Hold time Slow slew rate (see Notes 8 and 9) Data after CLK↑, CLK↓ 0.9 ns † For this test condition, VDDQ always is equal to VCC . NOTES: 5. Data inputs must be held low for a minimum time of tact min, after RESET is taken high. 6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tinact min, after RESET is taken low. 7. Data signal input slew rate ≥1 V/ns 8. Data signal input slew rate ≥0.5 V/ns and <1 V/ns 9. CLK, CLK input slew rates are ≥1 V/ns. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V† UNITPARAMETER (INPUT) (OUTPUT) MIN MAX UNIT fmax 200 MHz tpd CLK and CLK Q 1.1 2.8 ns tPHL RESET Q 5 ns † For this test condition, VDDQ always is equal to VCC . Not Recommended for New Designs

NOTES: A. C L includes probe and jig capacitance. B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. input slew rate = 1 V/ns ±20% (unless otherwise noted). D. The outputs are measured one at a time with one transition per measurement. F. V IH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input. G. V IL = VREF – 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples SN74SSTV16857DGGR NRND TSSOP DGG 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 SSTV16857 SN74SSTV16857DGVR NRND TVSOP DGV 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SS857 SN74SSTV16857DGVRG NRND TVSOP DGV 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 SS857 SN74STV16857DGGRG4 NRND TSSOP DGG 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 0 to 70 SSTV16857 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 11-Apr-2013 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74SSTV16857DGGR TSSOP DGG 48 0 367.0 367.0 45.0 SN74SSTV16857DGVR TVSOP DGV 48 0 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 2

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97

48 PINS SHOWN

0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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