SSTUM32866EC/S

SSTUM32866 NXP | Alldatasheet

Document overview

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Technical content

General description The SSTUM32866 is a 1.8 V conﬁgurable register speciﬁcally designed for use on DDR2 memory modules requiring a parity checking function. It is deﬁned in accordance with the JEDEC standard for the SSTUM32866 registered buffer. The register is conﬁgurable (using conﬁguration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter conﬁguration can be designated as Register A or Register B on the DIMM. The SSTUM32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is deﬁned as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. The SSTUM32866 is the high-output drive version of SSTUG32866. The SSTUM32866 is packaged in a 96-ball, 6× 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm× 5.5 mm). 2. Features n Conﬁgurable register supporting DDR2 up to 800 MT/s Registered DIMM applications n Conﬁgurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode n Controlled output impedance drivers enable optimal signal integrity and speed n Meets or exceeds SSTUM32866 JEDEC standard speed performance n High output drive n Supports up to 550 MHz clock frequency of operation n Optimized pinout for high-density DDR2 module design n Chip-selects minimize power consumption by gating data outputs from changing state n Supports SSTL_18 data inputs n Checks parity on the DIMM-independent data inputs n Partial parity output and input allows cascading of two SSTUM32866s for correct parity error processing n Differential clock (CK andCK) inputs n Supports LVCMOS switching levels on the control andRESET inputs n Single 1.8 V supply operation (1.7 V to 2.0 V) n Available in 96-ball, 13.5 mm× 5.5 mm, 0.8 mm ball pitch LFBGA package SSTUM32866

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer

with parity for DDR2-1G RDIMM applications Rev. 01 — 29 June 2007 Product data sheet

1.8 V DDR2-1G conﬁgurable registered buffer with parity

4.1 Ordering options

Table 1. Ordering information Table 2. Ordering options

Functional diagram (1) Disabled in 1 : 1 conﬁguration. Fig 1. Functional diagram of SSTUM32866; 1 : 2 Register A conﬁguration with C0 = 0 and C1 = 1 (positive logic) 002aad083 R R R QCKEA QCKEB (1) QODTA QODTB (1) QCSA QCSB (1) CSR DCS DODT DCKE D2 0 R Q2A Q2B (1) to 10 other channels (D3, D5, D6, D8 to D14) CK VREF CK RESET SSTUM32866

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 June 2007 4 of 28 NXP Semiconductors SSTUM32866 Fig 2. Parity logic diagram for 1 : 2 Register A conﬁguration (positive logic); C0 = 0, C1 = 1 002aaa650 D R Q2A, Q3A, Q5A, Q6A, Q8A to Q14A Q2B, Q3B, Q5B, Q6B, Q8B to Q14B CLK PAR_IN D2, D3, D5, D6, D8 to D14 CK CK RESET LPS0 (internal node) CE VREF PARITY CHECK R CLK D R CLK CE D R CLK R CLK D R CLK LPS1 (internal node) 2-BIT COUNTER QERR PPO D2, D3, D5, D6, D8 to D14 D2, D3, D5, D6, D8 to D14

Pinning information

6.1 Pinning

Fig 3. Pin conﬁguration for LFBGA96 Fig 4. Ball mapping, 1 : 1 register (C0 = 0, C1 = 0) 002aad084 Transparent top view T R P N M L J G K H F E D C B A 246135 ball A1 index area SSTUM32866EC/G SSTUM32866EC/S DCKE PPO VREF VDD QCKE DNU 123456 D2 D15 GND GND Q2 Q15 A B D3 D16 VDD VDD Q3 Q16C DODT GND GND QODT DNUD D5 D17 VDD VDD Q5 Q17E D6 D18 GND GND Q6 Q18F PAR_IN RESET VDD VDD C1 C0G CK DCS GND GND QCS DNUH CK CSR VDD VDD n.c. n.c.J D8 D19 GND GND Q8 Q19K D9 D20 VDD VDD Q9 Q20L D10 D21 GND GND Q10 Q21M D11 D22 VDD VDD Q11 Q22N D12 D23 GND GND Q12 Q23P D13 D24 VDD VDD Q13 Q24R D14 D25 VREF VDD Q14 Q25T 002aab108 QERR

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 June 2007 6 of 28 NXP Semiconductors SSTUM32866 Fig 5. Ball mapping, 1 : 2 Register A (C0 = 0, C1 = 1) Fig 6. Ball mapping, 1 : 2 Register B (C0 = 1, C1 = 1) DCKE PPO VREF VDD QCKEA QCKEB 123456 D2 DNU GND GND Q2A Q2B A B D3 DNU VDD VDD Q3A Q3BC DODT QERR GND GND QODTA QODTBD D5 n.c. VDD VDD Q5A Q5BE D6 n.c. GND GND Q6A Q6BF PAR_IN RESET VDD VDD C1 C0G CK DCS GND GND QCSAH CK CSR VDD VDD n.c. n.c.J D8 DNU GND GND Q8A Q8BK D9 DNU VDD VDD Q9A Q9BL D10 DNU GND GND Q10A Q10BM D11 DNU VDD VDD Q11A Q11BN D12 DNU GND GND Q12A Q12BP D13 DNU VDD VDD Q13A Q13BR D14 DNU VREF VDD Q14A Q14BT 002aab109 QCSB D1 PPO VREF VDD Q1A Q1B 123456 D2 DNU GND GND Q2A Q2B A B D3 DNU VDD VDD Q3A Q3BC D4 GND GND Q4A Q4BD D5 DNU VDD VDD Q5A Q5BE D6 DNU GND GND Q6A Q6BF PAR_IN RESET VDD VDD C1 C0G CK DCS GND GND QCSAH CK CSR VDD VDD n.c. n.c.J D8 DNU GND GND Q8A Q8BK D9 DNU VDD VDD Q9A Q9BL D10 DNU GND GND Q10A Q10BM DODT DNU VDD VDD QODTA QODTBN D12 DNU GND GND Q12A Q12BP D13 DNU VDD VDD Q13A Q13BR DCKE DNU VREF VDD QCKEA QCKEBT 002aab110 QCSB QERR

6.2 Pin description

Figure4,Figure5, andFigure6 for ball number. Table 3. Pin description

1.8 V nominal power supply voltage

disables VREF data and clock. CK and the falling edge ofCK. after the corresponding data output.

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 June 2007 8 of 28 NXP Semiconductors SSTUM32866 [3] Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0. Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1. Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1. 7. Functional description The SSTUM32866 is a 25-bit 1 : 1 or 14-bit 1 : 2 conﬁgurable registered buffer with parity, designed for 1.7 V to 2.0 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18 speciﬁcations. The error ( QERR) output is 1.8 V open-drain driver. The SSTUM32866 operates from a differential clock (CK andCK). Data are registered at the crossing of CK going HIGH, andCK going LOW. The C0 input controls the pinout conﬁguration for the 1 : 2 pinout from A conﬁguration (when LOW) to B conﬁguration (when HIGH). The C1 input controls the pinout conﬁguration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH). The SSTUM32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is deﬁned as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. When used as a single device, the C0 and C1 inputs are tied LOW. In this conﬁguration, parity is checked on the PAR_IN input which arrives one cycle after the input data to which it applies. The Partial-Parity-Out (PPO) and QERR signals are produced three cycles after the corresponding data inputs. When used in pairs, the C0 input of the ﬁrst register is tied LOW and the C0 input of the second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the ﬁrst device. The PPO and QERR signals are produced on the second device three clock cycles after the corresponding data inputs. The PPO output of the ﬁrst register is cascaded to the PAR_IN of the second register. The QERR output of the ﬁrst register is left ﬂoating and the valid error information is latched on theQERR output of the second register. If an error occurs and theQERR output is driven LOW, it stays latched LOW for two clock cycles or untilRESET is driven LOW. The DIMM-dependent signals (DCKE,DCS, DODT, and CSR) are not included in the parity check computation. The device supports low-power standby operation. WhenRESET is LOW, the differential input receivers are disabled, and undriven (ﬂoating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all outputs are forced LOW. The LVCMOSRESET input must always be held at a valid logic HIGH or LOW level.

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. theCSR input should be pulled up to VDD through a pull-up resistor. RESET must be held in the LOW state during power-up. LOW, thus ensuring no glitches on the output.

7.1 Function table

[1] Q 0 is the previous state of the associated output. Table 4. Function table (each ﬂip-ﬂop) L = LOW voltage level; H = HIGH voltage level; X = don’t care;↑ = LOW-to-HIGH transition;↓ = HIGH-to-LOW transition.

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. [1] PPO 0 is the previous state of output PPO;QERR 0 is the previous state of outputQERR. [3] PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies. two clock cycles or untilRESET is driven LOW. [1] The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed. [2] This value is limited to 2.5 V maximum. Table 5. Parity and standby function table L = LOW voltage level; H = HIGH voltage level; X = don’t care;↑ = LOW-to-HIGH transition;↓ = HIGH-to-LOW transition. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).

Recommended operating conditions

[1] The RESET and Cn inputs of the device must be held at valid levels (not ﬂoating) to ensure proper device operation. [2] The differential inputs must not be ﬂoating, unlessRESET is LOW. Table 7. Recommended operating conditions

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. [1] Instantaneous is deﬁned as within < 2 ns following the output data transition edge. Table 8. Characteristics At recommended operating conditions (seeTable7); unless otherwise speciﬁed.

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. [1] This parameter is not necessarily production tested. [3] VREF , data and clock inputs must be held at valid levels (not ﬂoating) a minimum time of tINACT(max) afterRESET is taken LOW. [1] Includes 350 ps of test load transmission line delay. [2] This parameter is not necessarily production tested. Table 9. Timing requirements At recommended operating conditions (seeTable7), unless otherwise speciﬁed. SeeSection11.1. Table 10. Switching characteristics At recommended operating conditions (seeTable7), unless otherwise speciﬁed. SeeSection11.1. Table 11. Data output edge rates At recommended operating conditions (seeTable7), unless otherwise speciﬁed. SeeSection11.2.

10.1 Timing diagrams

Fig 7. Timing diagram for SSTUM32866 used as a single device; C0 = 0, C1 = 0 RESET DCS CSR CK CK to D25 to Q25 PAR_IN PPO QERR tsu th m m + 1 m + 2 m + 3 m + 4 tPD CK to Q tsu th tPD CK to PPO tPD CK to QERR 002aaa655 tPD CK to QERR

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 June 2007 15 of 28 NXP Semiconductors SSTUM32866 Fig 8. Timing diagram for the ﬁrst SSTUM32866 (1 : 2 Register A conﬁguration) device used in pair; C0 = 0, C 1=1 RESET DCS CSR CK CK to D14 to Q14 PAR_IN PPO QERR (not used) tsu th m m + 1 m + 2 m + 3 m + 4 tPD CK to Q tsu th tPD CK to PPO tPD CK to QERR 002aaa656 tPD CK to QERR

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 June 2007 16 of 28 NXP Semiconductors SSTUM32866 (1) PAR_IN is driven from PPO of the ﬁrst SSTUM32866 device. Fig 9. Timing diagram for the second SSTUM32866 (1 : 2 Register B conﬁguration) device used in pair; C 0=1 ,C 1=1 RESET DCS CSR CK CK to D14 to Q14 PAR_IN (1) PPO (not used) QERR tsu th m m + 1 m + 2 m + 3 m + 4 tPD CK to Q tsu th tPD CK to PPO tPD CK to QERR 002aaa657 tPD CK to QERR

Test information

11.1 Parameter measurement information for data output load circuit

VDD = 1.8 V± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo =5 0Ω ; input slew rate = 1 V/ns± 20 %, unless otherwise speciﬁed. The outputs are measured one at a time with one transition per measurement. (1) CL includes probe and jig capacitance. Fig 10. Load circuit, data output measurements (1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. Fig 11. Voltage and current waveforms; inputs active and inactive times VID = 600 mV. VIH =V ref+ 250 mV (AC voltage levels) for differential inputs. VIH =V DD for LVCMOS inputs. VIL=V ref− 250 mV (AC voltage levels) for differential inputs. VIL= GND for LVCMOS inputs. Fig 12. Voltage waveforms; pulse duration R L = 100 W R L = 1000 W VDD 50 W CK inputs CK CK OUT DUT test point 002aaa371test point delay = 350 ps Zo = 50 W R L = 1000 WC L = 30 pF(1) LVCMOS RESET 10 % IDD (1) tINACT VDD 0.5VDD tACT 90 % 0 V 002aaa372 0.5VDD VICR VICR VIH VIL input tW VID 002aaa373

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 June 2007 18 of 28 NXP Semiconductors SSTUM32866 VID = 600 mV. Vref= 0.5VDD . VIH =V ref+ 250 mV (AC voltage levels) for differential inputs. VIH =V DD for LVCMOS inputs. VIL=V ref− 250 mV (AC voltage levels) for differential inputs. VIL= GND for LVCMOS inputs. Fig 13. Voltage waveforms; setup and hold times tPLH and tPHL are the same as tPD . Fig 14. Voltage waveforms; propagation delay times (clock to output) tPLH and tPHL are the same as tPD . VIH =V ref+ 250 mV (AC voltage levels) for differential inputs. VIH =V DD for LVCMOS inputs. VIL=V ref− 250 mV (AC voltage levels) for differential inputs. VIL= GND for LVCMOS inputs. Fig 15. Voltage waveforms; propagation delay times (reset to output) tsu VIH VIL VID th CK CK input V ref Vref VICR 002aaa374 VOH VOL output tPLH 002aaa375 VT VICR VICR tPHL CK CK Vi(p-p) tPHL 002aaa376 LVCMOS RESET output VT 0.5VDD VIH VIL VOH VOL

11.2 Data output slew rate measurement information

VDD = 1.8 V± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo =5 0Ω ; input slew rate = 1 V/ns± 20 %, unless otherwise speciﬁed. (1) CL includes probe and jig capacitance. Fig 16. Load circuit, HIGH-to-LOW slew measurement Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement (1) CL includes probe and jig capacitance. Fig 18. Load circuit, LOW-to-HIGH slew measurement Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement C L = 10 pF(1) VDD OUT DUT test point R L = 50 Ω 002aaa377 VOH VOL output 80 % 20 % dv_f dt_f 002aaa378 C L = 10 pF(1) OUT DUT test point R L = 50 Ω 002aaa379 VOH VOL 80 % 20 % dv_r dt_r output 002aaa380

11.3 Error output load circuit and voltage measurement information

VDD = 1.8 V± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo =5 0Ω ; input slew rate = 1 V/ns± 20 %, unless otherwise speciﬁed. (1) CL includes probe and jig capacitance. Fig 20. Load circuit, error output measurements Fig 21. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET input. Fig 22. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock inputs C L = 10 pF(1) VDD OUT DUT test point R L = 1 kΩ 002aaa500 0.5VDD tPLH VDD 0 V 0.15 V VOH 0 V output waveform 2 RESET 002aaa501 LVCMOS VICR tHL 0.5VDD VDD VOL timing inputs output waveform 1 Vi(p-p)VICR 002aaa502

11.4 Partial parity out load circuit and voltage measurement information

VDD = 1.8 V± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo =5 0Ω ; input slew rate = 1 V/ns± 20 %, unless otherwise speciﬁed. Fig 23. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock inputs VICR tLH VOH 0 V timing inputs output waveform 2 Vi(p-p)VICR 0.15 V 002aaa503 (1) CL includes probe and jig capacitance. Fig 24. Partial parity out load circuit VT = 0.5VDD . tPLH and tPHL are the same as tPD . Vi(p-p)= 600 mV. Fig 25. Partial parity out voltage waveforms; propagation delay times with respect to clock inputs C L = 5 pF(1) OUT DUT test point R L = 1 kΩ 002aaa654 VOH VOL output tPLH 002aaa375 VT VICR VICR tPHL CK CK Vi(p-p)

SSTUM32866_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 29 June 2007 22 of 28 NXP Semiconductors SSTUM32866 VT = 0.5VDD . tPLH and tPHL are the same as tPD . VIH =V ref+ 250 mV (AC voltage levels) for differential inputs. VIH =V DD for LVCMOS inputs. VIL=V ref− 250 mV (AC voltage levels) for differential inputs. VIL= GND for LVCMOS inputs. Fig 26. Partial parity out voltage waveforms; propagation delay times with respect to RESET input tPHL 002aaa376 LVCMOS RESET output VT 0.5VDD VIH VIL VOH VOL

Package outline Fig 27. Package outline SOT536-1 (LFBGA96) 0.8 A 1 bA 2UNIT D ye REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE 00-03-04 03-02-05 IEC JEDEC JEITA mm 1.5 0.41 0.31 1.2 0.9 5.6 5.4 13.6 13.4 0.51 0.41 0.1 0.2 DIMENSIONS (mm are the original dimensions) SOT536-1 E 0.15 v 0.1 w 0 5 10 mm scale SOT536-1LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm A max. A detail X e e X D E A B C D E F H G J K L M P N R T 246135 B A ball A1 index area ball A1 index area yy1 C b C AC C B˘ v M ˘ w M 1/2 e 1/2 e

Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application NoteAN10365 “Surface mount reﬂow soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reﬂow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature proﬁle. Leaded packages, packages with solder balls, and leadless packages are all reﬂow solderable. Key characteristics in both wave and reﬂow soldering are:
Board speciﬁcations, including the board ﬁnish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

Process issues, such as application of adhesive and ﬂux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
Solder bath speciﬁcations, including temperature and impurities

13.4 Reﬂow soldering

Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to higher minimum peak temperatures (seeFigure28) than a PbSn process, thus reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classiﬁed in accordance with Table12 and13 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reﬂow soldering, seeFigure28.

Table 12. SnPb eutectic process (from J-STD-020C) Table 13. Lead-free process (from J-STD-020C)

Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit:http://www.nxp.com For sales ofﬁce addresses, send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors SSTUM32866 © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 29 June 2007 Document identifier: SSTUM32866_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 18. Contents

11.1 Parameter measurement information for

11.2 Data output slew rate measurement

11.3 Error output load circuit and voltage

11.4 Partial parity out load circuit and voltage

Summary

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications Rev. 01-29 June 2007

Description