SSTL16857 PHILIPS | Alldatasheet

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/C0080 /C0115 /C0111/C0110/C0111 /C0115 SSTL16857 14-bit SSTL_2 registered driver with differential clock inputs Product specification Supersedes data of 1999 Apr 29

1999 Sep 30

Philips Semiconductors Product specification SSTL1685714-bit SSTL_2 registered driver with differential clock inputs

21999 Sep 30 853-2155 22448

FEATURES

  • Stub-series terminated logic for 2.5V VDDQ (SSTL_2)
  • Optimized for DDR (Double Data Rate) SDRAM applications
  • Supports SSTL_2 signal inputs and outputs
  • Flow-through architecture optimizes PCB layout
  • Meets SSTL_2 class I and class II specifications
  • Latch-up protection exceeds 500mA per JEDEC Std 17
  • ESD protection exceeds 2000 V per MIL STD 833 Method 3015 and 200 V per Machine Model
  • Full DDR solution provided when used with PCK857 and CBT3857

DESCRIPTION

The SSTL16857 is a 14-bit SSTL_2 registered driver with differential clock inputs. Both VCC and VDDQ support 2.5V and 3.3V operation however. VDDQ must not exceed VCC . Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ . The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTL16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 100 MHz will have a burst rate of 200 MHz. The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTL16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well. PIN CONFIGURATION 20 29 VDDQ Q10 D12 D11 D10 RESET VREF GND VCC CLK+ CLK– VCC GND 24 25 28VDDQ Q14 D14 D13 GND VCC GND GND VDDQ VDDQ GND VDDQ GND Q11 Q12 GND Q13 SW00311 QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL /tPLH Propagation delay; CLK to Qn C L = 30 pF; VDDQ = 2.5 V 1.8 ns C I Input capacitance VCC = 2.5V 2.9 pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD /C0032 VCC 2 x fi (CL /C0032 VCC 2 /C0032 fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL /C0032 VCC 2 /C0032 fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER 48-Pin Plastic TSSOP Type I 0°C to +70°C SSTL16857 DGG SOT362-1

Philips Semiconductors Product specification SSTL1685714-bit SSTL_2 registered driver with differential clock inputs

1999 Sep 30 3

PIN NUMBER SYMBOL NAME AND FUNCTION

34 RESET

LVCMOS asynchronous master reset (Active LOW) 48, 47, 44, 43, 42, 41, 40, 33, 32, 31, 30, 29, 26, 25 D1 – D14 SSTL_2 data inputs 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 Q1 – Q14 SSTL_2 data outputs

35 VREF SSTL_2 input reference level

3, 8, 13, 17, 22, 27, 36, 46 GND Ground (0 V) 28, 37, 45 VCC Positive supply voltage 4, 9, 12, 16, 21VDDQ Output supply voltage CLK+ CLK– Differential clock inputs FUNCTION TABLE INPUTS OUTPUT RESET CLK CLK D Q L X X X L H ↓ ↑ H H H ↓ ↑ L L H L or H L or H X Q 0 H = High voltage level L = High voltage level ↓ = High-to-Low transition ↑ = Low-to-High transition X = Don’t care LOGIC DIAGRAM SW00312 REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER REGISTER RESET VREF AD D10 D11 D12 D13 D14 CLK+ CLK– Q10 Q11 Q12 Q13 Q14 ABSOLUTE MAXIMUM RATINGS 1, 2 SYMBOL PARAMETER CONDITION LIMITS UNITSYMBOL PARAMETER CONDITION MIN MAX UNIT VCC DC supply voltage –0.5 +4.6 V IIK DC input diode current VI < 0 –50 mA VI DC input voltage3 –0.5 VDDQ + 0.5 V IOK DC output diode current VO < 0 –50 mA VOUT DC output voltage3 Note 3 –0.5 VDDQ + 0.5 V IO DC output current VO = 0 to VDDQ ±50 mAIOUT Continuous current4 VCC , VDDQ , or GND ±100 mA TSTG Storage temperature range –65 +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. The continuous current at VCC , VDDQ , or GND should not exceed ±100 mA.

Philips Semiconductors Product specification SSTL1685714-bit SSTL_2 registered driver with differential clock inputs

1999 Sep 30 4

RECOMMENDED OPERATING CONDITIONS 1 SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC Supply voltage VDDQ 3.6 V VDDQ Output supply voltage 2.3 2.7 V VREF Reference voltage (VREF = 0.5 x VDDQ ) 1.15 1.25 1.35 V VTT Termination voltage VREF – 40mV VREF VREF + 40mV V VI Input voltage 0 VCC V VIH AC HIGH-level input voltage All inputs VREF + 350mV V VIL AC LOW-level input voltage All inputs VREF – 350mV V VIH DC HIGH-level input voltage All inputs VREF + 180mV VDDQ + 0.5V V VIL DC LOW-level input voltage All inputs VSS – 0.5V VREF – 180mV V IOH HIGH-level output current –20 mA IOL LOW-level output current 20 mA Tamb Operating free-air temperature range 0 70 °C NOTE: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = 0°C to +70°C UNIT MIN TYP 2 MAX VIK I/O supply voltage VCC = 2.3V; II = –18mA –1.2 VCC = 2.3V to 2.7V; IOH = –100µA VCC – 0.2 2.3 V VOH HIGH level output voltageVCC = 2.3V; IOH = –8mA 1.95 2.2 V VCC = 2.3V; IOH = –16mA 1.95 2.1 VCC = 2.3V to 2.7V; IOL = –100µA 0.002 0.2 VOL LOW level output voltageVCC = 2.3V; IOL = –8mA 0.14 0.35 V VCC = 2.3V; IOL = –16mA 0.30 0.35 VCMR CLK, CLK Common mode range for reliable performance 0.97 1.53 V VPP CLK, CLK Minimum peak-to-peak input to ensure logic state 360 mV VCC = 2.7V ; VI = 1.7V or 0.8V 0.01 ±5 Data inputs RESET VCC = 2.7V ; VI = 2.7V or 0V V = 1 15V or 1 35V 0.01 ±5 µAData inputs, RESET VCC = 3.6V ; VI = 1.7V or 0.8V VREF = 1.15V or 1.35V 0.01 ±5 µA VCC = 3.6V ; VI = 2.7V or 0V 0.01 ±5 I VCC = 2.7V ; VI = 1.7V or 0.8V 0.05 ±5 II CLK CLK VCC = 2.7V ; VI = 2.7V or 0V V = 1 15V or 1 35V 0.05 ±5 µA CLK , CLK VCC = 3.6V ; VI = 1.7V or 0.8V VREF = 1.15V or 1.35V 0.05 ±5 VCC = 3.6V ; VI = 2.7V or 0V 0.05 ±5 mA V VCC = 2.7V V = 1 15V or 1 35V 0.05 ±5 µAVREF VCC = 3.6V VREF = 1.15V or 1.35V 0.05 ±5 µA VCC = 2.7V ; VI = 1.7V or 0.8V 12 25 ICC Quiescent supply current CLK and CLK in opposite VCC = 2.7V ; VI = 2.7V or 0V 10 25 mAICC CLK and CLK in o osite state1 VCC = 3.6V ; VI = 1.7V or 0.8V 12 25 mA VCC = 3.6V ; VI = 2.7V or 0V 10 25 NOTES: 1. When CLK and CLK are HIGH, typical ICC = 25mA. 2. All typical values are at VCC = 3.3V and Tamb = 25°C (unless otherwise specified).

Philips Semiconductors Product specification SSTL1685714-bit SSTL_2 registered driver with differential clock inputs

1999 Sep 30 5

Over recommended operating conditions; Tamb = 0/C0095C to +70/C0095C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER TEST CONDITIONS VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V UNIT MIN MAX MIN MAX fclock Clock frequency 200 200 MHz tw Pulse duration, CLK, CLK HIGH or LOW 1.0 1.0 ns t Setup time Data before CLK↑, CLK↓ 0.8 0.9 nstsu Setup time RESET HIGH before CLK↑, CLK↓ 0.8 1.0 ns th Hold time 0.5 0.5 ns SWITCHING CHARACTERISTICS Over recommended operating conditions; Tamb = 0/C0095C to +70/C0095C; VDDQ = 2.3 – 2.7V and VDDQ does not exceed VCC. Class I, VREF = VTT = VDDQ x 0.5 and CL = 10pF (unless otherwise noted) (see Figure 1) LIMITS LIMITS SYMBOL FROM (INPUT) TO (OUTPUT) VCC = 2.5V ±0.2V VCC = 3.3V ±0.3V UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX fmax Maximum clock frequency 200 200 MHz tPLH /tPHL CLK and CLK Q 1.0 3.1 0.7 2.6 ns tPHL RESET Q 2.0 5.0 1.4 4.0 ns 184/200-pin DDR SDRAM DIMM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM The PLL clock distribution device and SSTL registered drivers reduce signal loads on the memory controller and prevent timing delays and waveform distortions that would cause unreliable operation SW00393 CBT3857 (9)CBT CBT CBT CBT CBT CBT CBT CBT CBT SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SSTL16857 PCK857SSTL16857 BACK SIDE FRONT SIDE

1999 Sep 30 6

Waveform 2. Propagation delay RESET to output. The outputs are measured one at a time with one transition per measurement. Figure 1. Load circuitry

Philips Semiconductors Product specification SSTL1685714-bit SSTL_2 registered driver with differential clock inputs

1999 Sep 30 7

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1

Philips Semiconductors Product specification SSTL1685714-bit SSTL_2 registered driver with differential clock inputs

1999 Sep 30 8

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 09–99 Document order number: 9397–750–06455 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.