SSTE32882KB1

SSTE32882KB1 RENESAS | Alldatasheet

Document overview

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Technical content

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 1 SSTE32882KB1 7326/3 DATASHEET 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT SSTE32882KB1

Description

This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.25V , 1.35V and 1.5V VDD operation. All inputs are 1.25,1.35V and 1.5V CMOS compatible, except the reset (RESET) and MIRROR inputs which are LVCMOS. All outputs are 1.25V ,1.35V and 1.5V CMOS edge-controlled drivers optimized to drive single terminated 25 to 50 traces in DDR3 RDIMM applications, except the open-drain error (ERROUT) output. The clock outputs (Yn and Yn) and control net outputs QnCKEn, QnCSn and QnODTn are designed with a different strength and skew to compensate for different loading and equalize signal travel speed. The SSTE32882KB1 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the "QuadCS disabled" mode. When the QCSEN input pin is pulled low, the component has four chip select inputs DCS[3:0], and four chip select outputs, QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0] will indicate all of the chip select outputs. The SSTE32882KB1 includes a high-performance, low-jitter, low-skew buffer that distributes a differential clock input (CK and CK ) to four differential pairs of clock outputs (Yn and Yn), and to one differential pair of feedback clock outputs (FBOUT and FBOUT ). The clock outputs are controlled by the input clocks (CK and CK), the feedback clocks (FBIN and FBIN), and the analog power inputs (A VDD and A VSS). When A VDD is grounded, the PLL is turned off and bypassed for test purposes. The SSTE32882KB1 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going high, and CK going low. The data is either driven to the corresponding device outputs if exactly one of the DCS[n:0] input signals is driven low. Based on the control register settings, the device can change its output characterisitics to match different DIMM net topologies. The timing can be changed to compensate for different flight time of signals within the target application. By disabling unused outputs the power consumption is reduced. The SSTE32882KB1 accepts a parity bit from the memory controller on the parity (PAR_IN) input, compares it with the data received on the DIMM-independent data inputs (DAn, DBAn, DRAS , DCAS, and DWE), and indicates whether a parity error has occurred on the open-drain ERROUT pin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state. The DIMM-dependent signals (DCKEn, DODTn, and DCSn ) are not included in the parity check computation. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power-up. The SSTE32882KB1 is available in a 176-ball BGA with 0.65mm ball pitch in a 11 x 20 grid. The device pinout supports outputs on the outer two left and right columns to support easy DIMM signal routing. Corresponding inputs are placed in a-way that two devices can be placed back-to-back for four Rank modules while the data inputs share the same vias. Each input and output is located close to an associated no ball position or on the outer two rows to allow low cost via technology combined with the small 0.65mm ball pitch.

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 2 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE

Features

• Pinout optimizes DDR3 RDIMM PCB layout
• DDR3-800/1066/1333/1600/1866/2133 rate
• 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs support stacked DDR3 RDIMMs
• Phase Lock Loop clock driver for buffering one differential clock pair (CK and CK) and distributing to four differential outputs
• Supports LVCMOS switching levels on the RESET and MIRROR inputs
• Checks priority on DIMM-independent data inputs
• Supports dynamic 1T/3T timing transaction and output inversion feature for improved timing performance during normal operations and MRS command pass-through
• Supports CKE Power Down operation modes
• Supports Quad Chip Select operation features
• RESET input disables differential input recievers, resets all registers, and disables all output drivers except ERROUT and QnCKEn
• Provides access to internal control words for configuring the device features and adapting in different RDIMM and system

applications

• Latch-up performance exceeds 100mA
• ESD > 2000V per MIL-STD883, Method 3015; ESD > 200V using machine model (c = 200pF, R = 0)
• Available in 176 Ball Grid Array package

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 3 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Block Diagram - Register and PLL Logic Diagram (Positive Logic) 1 DCS[n:0] indicates all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0] indicates all of the chip select outputs. DA3..DA9, DA10, DA12, DA0..DA2, DBA2 DA3, DA4, DBA0, DBA1 Control Word State Machine and Control Logic DCS[n:0] DCKE0, DODT0, DCKE1 DODT1 PLL R D Q CE R D Q CE R D Q R D Q R D Q Pre- Launch CMR Access DA11, DA13..DA15, DBA0..DBA2 DRAS , DCAS, DWE Output Inversion A-Enable B-Enable Y0..Y3- Enable VREF QxA3..QxA9, QxA11, QxA13..QxA15, QxBA0..QxBA2 QxA10, QxCAS QxWE QxA12, QxRAS QACKEn QAODTn QBCKEn QBODTn Y0Y2 FBOUT FBOUT CK CK FBIN FBIN RESET 1/4 CK delay 1/4 CK delay 1/4 CK delay 10K~100K OE0 OE1 OE2 OE3 1/4 CK 1delay QxCS[n:0] DA0-DA2, QxA0-QxA2, DRAS DCAS DWE (1) (1) CS Logic

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 4 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Block Diagram - Parity Logic Diagram (Positive Logic) 1 DCS[n:0] indicates all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS[n:0] indicates all of the chip select outputs. Internal Logic DCKE0, DCKE1 DODT0, DODT1 RESET CK CK FBIN FBIN PLL D R Q D R Q FBOUT FBOUT Internal Logic Internal Logic QACKEn QBCKEn QAODTn QBODTn 10K - 100K VREF DA0..DA15, DBA0..DBA2, DRAS, DCAS, DWE PAR_IN DCS[n:0] D R Q D R Q D R Q Internal Logic Internal Logic QA0..QA15, QBA0..QBA2, QRAS, QCAS, QWE ERROUT QxCS[n:0] CE CE Parity Generator and Error Check DRAS DCAS DWE Output Inversion Disabled 3T Timing Enabled CS Logic (1) (1)

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 5 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Pinout Configuration Package options include a 176-ball Thin-Profile Fine-Pitch BGA (TFBGA) with 0.65mm ball pitch, 11 x 20 grid, 8.0mm x 13.5mm. It uses the mechanical outline MO-246 variation F. The device pinout supports outputs on the outer two left and right columns to support easy DIMM signal routing. Corresponding inputs are placed in a way that two devices can be placed back to back for 4 Rank modules while the data inputs share the same vias. Each input and output is located close to an associated no-ball position or on the outer two rows to allow low cost via technology combined with the small 0.65mm ball pitch. 176-ball Thin Profile Fine Pitch BGA (TFBGA) 11x20 Grid Top View A B C D E F G H J K L M N P R T U V W Y 123 4 5 67 8 91 0 1 1

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 6 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Pin Descriptions The device has symmetric pinout with the inputs on the south side and the outputs on the east and west sides. This allows back-to-back mounting on both sides of the PCB if more than one device is needed. Ball Assignment: MIRROR = LOW, QCSEN = HIGH or float This table specifies the pinout for the SSTE32882KB1 in the front configuration (QuadCS mode disabled). Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and connecting pad on the module are required in these locations. Also, balls Y2 and R6 are “do not use” balls reserved for DCS2 and DCS3 in the QuadCS mode, and must not be connected on the system. The device is designed to tolerate floating on these pins. Blank spaces indicate no ball is populated at that gridpoint, and vias on the module may be located in these areas. 12 345 6 7 8 91 0 1 1 A QAA13 QAA8 QCSEN VSS RESET MIRROR ERROUT VSS RSVD QBA8 QBA13 B QAA14 QAA7 QBA7 QBA14 C QAA9 QAA6 V DD VDD VDD VDD VDD QBA6 QBA9 D QAA11 QAA5 V SS VSS VSS VSS VSS QBA5 QBA11 E QAA2 QAA4 V DD VDD VDD VDD VDD QBA4 QBA2 F QAA1 QAA3 V SS VSS VSS VSS VSS QBA3 QBA1 G QAA0 QABA1 V DD VDD VDD VDD VDD QBBA1 QBA0 H QAA12 QABA0 V SS VSS VSS VSS VSS QBBA0 QBA12 J QABA2 QACS1 VDD VDD VDD VDD VDD QBCS1 QBBA2 K QAA15 QACKE0 V SS VSS VSS VSS VSS QBCKE0 QBA15 LQ A W E QACS0 VDD VDD VDD VDD VDD QBCS0 QBWE M QAA10 QACKE1 V SS VSS VSS VSS VSS QBCKE1 QBA10 N QACAS QAODT0 V DD VDD VDD VDD VDD QBODT0 QBCAS P QARAS QAODT1 DA3 V SS VSS VSS DA4 QBODT1 QBRAS R DCKE1 DA14 DA15 DA5 RSVD DA2 DA1 DA10 DODT1 TD C K E 0 D C S 0 DCS1 DODT0 U DA12 DBA2 Y1 PVSS VDD PVDD Y0 DA13 DCAS V DA9 DA11 Y1 PV SS VSS PVDD Y0 DRAS DWE W DA8 DA6 FBIN Y3 AVSS CK RSVD Y2 FBOUT DA0 DBA0 Y DA7 RSVD FBIN Y3 A V DD CK VREFCA Y2 FBOUT PAR_IN DBA1

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 7 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Ball Assignment: MIRROR = HIGH, QCSEN = HIGH or float This table specifies the pinout for the SSTE32882KB1 in the back configuration (QuadCS mode disabled). Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and connecting pad on the module are required in these locations. Also, balls Y10 and R6 are “do not use” balls reserved for DCS2 and DCS3 in the QuadCS mode, and must not be connected on the system. The device is designed to tolerate floating on these pins. Blank spaces indicate no ball is populated at that gridpoint, and vias on the module may be located in these areas. 12 3 4 5 6 7 8 9 1 0 1 1 A QAA13 QAA8 QCSEN VSS RESET MIRROR ERROUT VSS RSVD QBA8 QBA13 B QAA14 QAA7 QBA7 QBA14 C QAA9 QAA6 V DD VDD VDD VDD VDD QBA6 QBA9 D QAA11 QAA5 V SS VSS VSS VSS VSS QBA5 QBA11 E QAA2 QAA4 V DD VDD VDD VDD VDD QBA4 QBA2 F QAA1 QAA3 V SS VSS VSS VSS VSS QBA3 QBA1 G QAA0 QABA1 V DD VDD VDD VDD VDD QBBA1 QBA0 H QAA12 QABA0 V SS VSS VSS VSS VSS QBBA0 QBA12 J QABA2 QACS1 VDD VDD VDD VDD VDD QBCS1 QBBA2 K QAA15 QACKE0 V SS VSS VSS VSS VSS QBCKE0 QBA15 LQ A W E QACS0 VDD VDD VDD VDD VDD QBCS0 QBWE M QAA10 QACKE1 V SS VSS VSS VSS VSS QBCKE1 QBA10 N QACAS QAODT0 V DD VDD VDD VDD VDD QBODT0 QBCAS P QARAS QAODT1 DA4 V SS VSS VSS DA3 QBODT1 QBRAS R DODT1 DA10 DA1 DA2 RSVD DA5 DA15 DA14 DCKE1 T DODT0 DCS1 DCS0 DCKE0 UD C A S DA13 Y1 PVSS VDD PVDD Y0 DBA2 DA12 VD W E DRAS Y1 PV SS VSS PVDD Y0 DA11 DA9 W DBA0 DA0 FBIN Y3 AVSS CK RSVD Y2 FBOUT DA6 DA8 Y DBA1 PAR_IN FBIN Y3 A V DD CK VREFCA Y2 FBOUT RSVD DA7

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 8 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Ball Assignment: MIRROR = LOW, QCSEN = LOW This table specifies the pinout for the SSTE32882KB1 in the front configuration (QuadCS mode enabled). Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and connecting pad on the module are required in these locations. Blank spaces indicate no ball is populated at that gridpoint, and vias on the module may be located in these areas. 12 345 6 7 8 91 0 1 1 A QAA13 QAA8 QCSEN VSS RESET MIRROR ERROUT VSS RSVD QBA8 QBA13 B QAA14 QAA7 QBA7 QBA14 C QAA9 QAA6 V DD VDD VDD VDD VDD QBA6 QBA9 D QAA11 QAA5 V SS VSS VSS VSS VSS QBA5 QBA11 E QAA2 QAA4 V DD VDD VDD VDD VDD QBA4 QBA2 F QAA1 QAA3 V SS VSS VSS VSS VSS QBA3 QBA1 G QAA0 QABA1 V DD VDD VDD VDD VDD QBBA1 QBA0 H QAA12 QABA0 V SS VSS VSS VSS VSS QBBA0 QBA12 J QABA2 QCS1 VDD VDD VDD VDD VDD QCS3 QBBA2 K QAA15 QACKE0 V SS VSS VSS VSS VSS QBCKE0 QBA15 LQ A W E QCS0 VDD VDD VDD VDD VDD QCS2 QBWE M QAA10 QACKE1 V SS VSS VSS VSS VSS QBCKE1 QBA10 N QACAS QAODT0 V DD VDD VDD VDD VDD QBODT0 QBCAS P QARAS QAODT1 DA3 V SS VSS VSS DA4 QBODT1 QBRAS R DCKE1 DA14 DA15 DA5 DCS3 DA2 DA1 DA10 DODT1 TD C K E 0 D C S 0 DCS1 DODT0 U DA12 DBA2 Y1 PVSS VDD PVDD Y0 DA13 DCAS V DA9 DA11 Y1 PV SS VSS PVDD Y0 DRAS DWE W DA8 DA6 FBIN Y3 AVSS CK RSVD Y2 FBOUT DA0 DBA0 Y DA7 DCS2 FBIN Y3 A V DD CK VREFCA Y2 FBOUT PAR_IN DBA1

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 9 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Ball Assignment: MIRROR = HIGH, QCSEN = LOW This table specifies the pinout for the SSTE32882KB1 in the back configuration (QuadCS mode enabled). Balls A9 and W7 are reserved for future functions and must not be connected on the system. However, a ball on the device and connecting pad on the module are required in these locations. Blank spaces indicate no ball is populated at that gridpoint, and vias on the module may be located in these areas. 12 3 4 5 6 7 8 9 1 0 1 1 A QAA13 QAA8 QCSEN VSS RESET MIRROR ERROUT VSS RSVD QBA8 QBA13 B QAA14 QAA7 QBA7 QBA14 C QAA9 QAA6 V DD VDD VDD VDD VDD QBA6 QBA9 D QAA11 QAA5 V SS VSS VSS VSS VSS QBA5 QBA11 E QAA2 QAA4 V DD VDD VDD VDD VDD QBA4 QBA2 F QAA1 QAA3 V SS VSS VSS VSS VSS QBA3 QBA1 G QAA0 QABA1 V DD VDD VDD VDD VDD QBBA1 QBA0 H QAA12 QABA0 V SS VSS VSS VSS VSS QBBA0 QBA12 J QABA2 QCS1 VDD VDD VDD VDD VDD QCS3 QBBA2 K QAA15 QACKE0 V SS VSS VSS VSS VSS QBCKE0 QBA15 LQ A W E QCS0 VDD VDD VDD VDD VDD QCS2 QBWE M QAA10 QACKE1 V SS VSS VSS VSS VSS QBCKE1 QBA10 N QACAS QAODT0 V DD VDD VDD VDD VDD QBODT0 QBCAS P QARAS QAODT1 DA4 V SS VSS VSS DA3 QBODT1 QBRAS R DODT1 DA10 DA1 DA2 DCS3 DA5 DA15 DA14 DCKE1 T DODT0 DCS1 DCS0 DCKE0 UD C A S DA13 Y1 PVSS VDD PVDD Y0 DBA2 DA12 VD W E DRAS Y1 PV SS VSS PVDD Y0 DA11 DA9 W DBA0 DA0 FBIN Y3 AVSS CK RSVD Y2 FBOUT DA6 DA8 Y DBA1 PAR_IN FBIN Y3 A V DD CK VREFCA Y2 FBOUT DCS2 DA7

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 10 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Terminal Functions Signal Group Signal Name Type Description Ungated inputs DCKEn, DODTn 1.25V/1.35V/1.5V CMOS Inputs1 DRAM corresponding register function pins not associated with Chip Select. Chip Select gated inputs DAn, DBAn, DRAS DCAS, DWE 1.25V/1.35V/1.5V CMOS Inputs DRAM corresponding register inputs, re-driven only when either chip select is LOW. If both chip selects are low the register maintains the state of the previous input clock cycle at its outputs Chip Select inputs DCS0 , DCS1 1.25V/1.35V/1.5V CMOS Inputs1 DRAM corresponding register Chip Select signals. These pins initiate DRAM address/command decodes, and as such exactly one will be low when a valid address/command is present which should be re-driven. DCS2 , DCS3 1.25V/1.35V/1.5V CMOS Inputs1 DRAM corresponding register Chip Select signals when QuadCS mode is enabled. DCS2 and DCS3 inputs are disabled when QuadCS mode is disabled. Re-driven outputs QxAn, QxBAn, QxCSn, QxCKEn, QxODTn, QxRAS, QxCAS, QxWE 1.25V/1.35V/1.5V CMOS Outputs Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock. x is A or B; outputs are grouped as A or B and may be enabled or disabled via RC0. Parity input PAR_IN 1.25V/1.35V/1.5V CMOS Inputs Input parity is received on pin PAR_IN and should maintain parity across the Chip Select Gated inputs (see above), at the rising edge of the input clock, one input clock cycle after corresponding data and one or both chip selects are LOW. Parity error output ERROUT Open drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. ERROUT will be active for two clock cycles, and delayed by 3 clock cycles to the corresponding input data Clock inputs CK, CK 1.25V/1.35V/1.5V CMOS Inputs1 Differential master clock input pair to the PLL; has weak internal pull-down resistors (10K~100K. Feedback FBIN, FBIN 1.25V/1.35V/1.5V CMOS Inputs1 Feedback clock input Clock FBOUT, FBOUT 1.25V/1.35V/1.5V CMOS Outputs2 Feedback clock output Clock Outputs Yn, Yn 1.25V/1.35V/1.5V CMOS Outputs2 Re-driven Clock Miscellaneous inputs RESET CMOS3 Active low asynchronous reset input. When LOW, it causes a reset of the internal latches and disables the outputs, thereby forcing the outputs to float. Once RESET becomes high the Q outputs get enabled and are driven LOW (ERROUT is driven high) until the first access has been performed. RESET also resets the ERROUT signal. MIRROR CMOS 3 Selects between two different ballouts for front or back operation. When the MIRROR input is high, the device Input Bus Termination (IBT) is turned off on all inputs, except the DCSn and DODTn inputs. QSCEN CMOS3 Enables the QuadCS mode. The QSCEN input has a weak internal pullup resistor (10K - 100K).

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 11 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Function Table (Each Flip Flop) with QuadCS Mode Disabled Power Vrefca 1 Reference V oltage Input reference voltag e for the differential data inputs, VDD/2 (0.75V) nominal. Vdd Register Power Power supply voltage (Register) Vss Register Ground Ground (Register) A Vdd Analog Power Analog supply voltage (PLL) A Vss Analog Ground Analog ground (PLL) PVdd PLL Power Clock logic and clock output driver power supply (PLL) PVss PLL Ground Clock logic and clock output driver ground (PLL) RSVD I/O Reserved pins, must be left floating (PLL) 1 1.25V/1.35V/1.5V CMOS inputs use V REFCA as the switching point reference for these receivers. 2 These outputs are optimized for memo ry applications to drive DRAM inputs to 1.25V/1.35V/1.5V signaling levels. 3 Voltage levels according standard JESD 8-11A, wide range, non terminated logic. Inputs Outputs 1 1 Q 0 means the output does not change state. RESET DCS0 DCS1 CK2 2 It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels (LOW and HIGH) when RESET is driven HIGH. CK2 ADDR3

3 ADDR = DA[15:0], DBA[2:0]

4 CMD = DRAS , DCAS, DWE. CTRL5 5 CTRL = DODTn, DCKEn. Qn6 6 Qn = QxAn, QxRAS , QxCAS, QxWE, and QxBAn. QxCS0 QxCS1 QxODTn QxCKEn HL L  Control Word Control Word Control Word Q0 HH Q 0 Q0 H X X L or H H or L X X X Q 0 Q0 Q0 Q0 Q0 HL H  XXX Follows Input LH Follows Input Follows Input H X X L L X X X float float float float L HH L  XXX Follows Input HL Follows Input Follows Input HH H  X or float X or float X Q0 or float7 7 Depending on Control Word RC0 Bit DA4. If RC0 DA4 is cleared, previous state (Q 0) is maintained. Address floating is disabled independent of control word RC0 once 3T timing is activated. HH Follows Input Follows Input L X or float X or float X or float X or float X or float X or float X or float float float float float L Signal Group Signal Name Type Description

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 12 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Function Table (Each Flip Flop) with QuadCS Mode Enabled Inputs Outputs RESET DCS[3:0] CK 1 1 It is illegal to hold both the CK and CK inputs at static logic high levels or static complementary logic levels (low and high) when RESET is driven high. CK1 A/C/E2 2 A/C/E = DA0..DA15, DBA0..DBA2, DRAS , DCAS, DWE, DODTn, DCKEn Qn QCS[3:0] QxODTn QxCKEn H LLHH   Control Word No change HHHH No change No changeHH H L L HL L L L H XXXX L or H H or L X No change No change No change No change H LHHH  Dn Dn LHHH DODTn DCKEn HH L H H  Dn Dn HLHH DODTn DCKEn HH H L H  Dn Dn HHLH DODTn DCKEn HH H H L  Dn Dn HHHL DODTn DCKEn HL H L H  Dn Dn LHLH DODTn DCKEn HH L L H  Dn Dn HLLH DODTn DCKEn HL H H L  Dn Dn LHHL DODTn DCKEn HH L H L  Dn Dn HLHL DODTn DCKEn H XXXX LL X float float float L H HHHH  X No change or float3 3 Depending on Control Word RC0 Bit DA4. If RC0 DA4 is cleared, previous state is maintained. Address floating is disabled independent of control word RC0 once 3T timing is activated HHHH DODTn DCKEn H LLLH  X Ilegal Input StatesH LLHL HL H L L HH L L L L X or float X or float X or float X or float float float float L

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 13 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Parity, Low Power and Standby with QuadCS Mode Disabled Inputs Output RESET DCS0 DCS1 CK 1 1 It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels (LOW and HIGH) when RESET is driven HIGH. CK1  of C/A2 2 C/A= DAn, DBAn, DRAS, DCAS, DWE. Inputs DCKEn, DODTn, and DCSn are not included in this range. This column represents the sum of the number of C/A signals that are electrically HIGH. PAR_IN3 3 PAR_IN arrives one clock cycle after the data to which it applies, ERROUT is issued three clock cycles after the failing data. ERROUT4 4 This transition assumes ERROUT is high at the crossing of CK going high and CK going low. If ERROUT is low, it stays latched low for exactly two clock cycles or until RESET is driven low. HLX  Even L H HLX  Odd L L HLX  Even H L HLX  Odd H H HXL  Even L H HXL  Odd L L HXL  Even H L HXL  Odd H H HHH  XX H 5

5 Same three cycle delay for ERROUT is valid for the de-select phase (see diagram)

H X X L or H H or L X X ERROUT 0 HXXLL X X H 6 6 The system is not allowed to pull CK and CK low while ERROUT is asserted. L X or floating X or floating X or floating X or floating X or floating X or floating H

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 14 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Parity, Low Power and Standby with QuadCS Mode Enabled Inputs Output RESET DCS[3:0] CK 1 1 It is illegal to hold both the CK and CK inputs at static logic high levels or static complementary logic levels (low and high) when RESET is driven high. CK1  of A/C2 and DCS1 are not included in this range. This column represents the sum of the number of A/C signals that are elec- trically high. PAR_IN3 3 PAR_IN arrivesone clock cycle af terdata to which it applies, ERROUT is issued three clock cycles after the fail- ing data. ERROUT4 4 This transition assumes ERROUT is high at the crossing of CK going high and CK going low. If ERROUT is low, it stays latched low for exactly two clock cycles or until RESET is driven low. HL X X X XLXX XXLX XXXL  Even L H HL X X X XLXX XXLX XXXL  Odd L L HL X X X XLXX XXLX XXXL  Even H L HL X X X XLXX XXLX XXXL  Odd H H H HHHH  XX H

5 Same three-cycle delay for ERROUT is valid for the de-select phase (see diagram)

H XXXX L or H H or L X X ERROUT n0 H XXXX L L X X H 6 6 The system is not allo wed to pull CK and CK low while ERROUT is asserted. L X or floating X or floating X or floating X or floating X or floating H

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 15 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE PLL Function Table Inputs Outputs PLL RESET AVDD OEn1 1 The Output Enable (OEn) to disable the output buffer is not an input signal to the SSTE32882KB1, but an internal signal from the PLL powerdown control and test logic. It is controlled by setting or clearing the corresponding bit in the Clock Driver mode register. CK2 2 It is illegal to hold both the CK and CK inputs at static logic HIGH levels or static complementary logic levels (LOW and HIGH) when RESET is driven HIGH. CK2 Yn Yn FBOUT FBOUT L X X X X Float Float Float Float Off H VDD nominal L L H L HL HO n H VDD nominal L H L H L H L On H VDD nominal H L H Float Float L HO n H VDD nominal H H L Float Float H LO n H VDD nominal X L L Float Float Float Float Off H GND 3 This is a device test mode and all regi ster timing parameters are not guaranteed. LL H L HL H Bypassed/Off H GND3 LH L H LH L Bypassed/Off H GND3 H L H Float Float L H Bypassed/Off H GND3 H H L Float Float H L Bypassed/Off H GND3 X L L Float Float Float Float Bypassed/Off H X X H H Reserved

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 16 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability DC and AC Specifications The SSTE32882KB1 parametric values are specified for the device default control word settings, unless otherwise stated. Note that RC10 setting does not affect any of the paramteric values. Symbol Parameter Conditions Min Max Unit AVDD, PVDD, VDD Supply voltage –0.4 +1.975 V VI Receiver input voltage1 1 The input and output negative-voltage ratings may be ex ceeded if the input and outpu t clamp-current ratings are observed. This value is limited to 1.975 V maximum. –0.4 V DD +0 . 5 V VREF Reference voltage –0.4 V DD +0 . 5 V VO Driver output voltage1 –0.4 V DD +0 . 5 V IIK Input clamp current V I < 0 or VI > VDD -50 mA IOK Output clamp current V O < 0 or VO > VDD ±50 mA IO Continuous output current 0 < V O < VDD ±50 mA ICCC Continuous current through each VDD or GND pin ±100 mA TSTG Storage temperature –65 +150 C RJA Package Thermal Impedance, Junction-to-Ambient2 2 The package thermal impedance is calculated in accordance with JESD51-2. 0m/s Airflow 43.8 C/W1m/s Airflow 35.5 RJB Package Thermal Impedance, Junction-to-Board2 22 C/W RJC Package Thermal Impedance, Junction-to-Case2 16.2 C/W

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 17 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE DC Specifications - Voltage The SSTE32882KB1 parametric values are specified for the device default control word settings, unless otherwise stated. Note that the RC10 setting does not affect any of the parametric values. Symbol Parameter Signals Min Nom Max Unit VDD DC Supply voltage (1.5V Operation) 1.425 1.5 1.575 V DC Supply voltage (1.35V Operation) 1.282 1.35 1.451 V VREF DC Reference voltage 0.49 x V DD 0.50 x VDD 0.51 x VDD V VTT DC Termination voltage V REF – 40 mV V REF VREF + 40 mV V VIH(AC) AC HIGH-level input voltage (1.5V Operation, DDR3-800/1066/1333) Data inputs1 VREF + 175 mV – VDD + 0.4 V AC HIGH-level input voltage (1.5V Operation, DDR3-1600) Data inputs1 VREF + 150 mV – VDD + 0.4 V AC HIGH-level input voltage (1.5V Operation, DDR3-1866) Data inputs1 VREF + 135 mV – VDD + 0.4 V AC HIGH-level input voltage (1.35V Operation, DDR3L-800/1066/1333) Data inputs1 VREF + 150 mV – VDD + 0.2 V AC HIGH-level input voltage (1.35V Operation, DDR3L-1600) Data inputs1 VREF + 135 mV – VDD + 0.2 V VIL(AC) AC LOW-level input voltage (1.5V Operation, DDR3-800/1066/1333) Data inputs1 –0.4 – VREF – 175 mV V AC LOW-level input voltage (1.5V Operation, DDR3-1600) Data inputs1 –0.4 – VREF – 150 mV V AC LOW-level input voltage (1.5V Operation, DDR3-1866) Data inputs1 –0.4 – VREF – 135 mV V AC LOW-level input voltage(1.35V Operation, DDR3L-800/1066/1333) Data inputs1 –0.2 – VREF – 150 mV V AC LOW-level input voltage (1.35V Operation, DDR3L-1600) Data inputs1 –0.2 – VREF – 135 mV V VIH(DC) DC HIGH-level input voltage(1.5V Operation) Data inputs1 VREF + 100 mV – VDD + 0.4 V DC HIGH-level input voltage(1.35V Operation) Data inputs1 VREF + 90 mV – VDD + 0.2 V VIL(DC) DC LOW-level input voltage(1.5V Operation) Data inputs1 –0.4 – VREF – 100 mV V DC LOW-level input voltage(1.35V Operation) Data inputs1 –0.2 – VREF – 90 mV V VIH(CMOS) HIGH-level input voltage CMOS inputs2 0.65 x VDD – VDD V VIL(CMOS) LOW-level input voltage CMOS inputs2 0– 0 . 3 5 x V D D V VIL (Static) Static LOW-level input voltage3 CK, CK, -– 0 . 3 5 x V D D V VIX(AC) Differential input crosspoint voltage range(1.5V Operation, DDR3-800/1066/1333/1600) CK, CK, FBIN, FBIN 0.5xVDD - 175 mV 0.5 x V DD 0.5xVDD + 175 mV V 0.5xVDD - 200 mV4 0.5 x VDD 0.5xVDD + 200 mV4 V Differential input crosspoint voltage range(1.5V Operation, DDR3-1866) CK, CK , FBIN, FBIN 0.5xVDD - 150 mV 0.5 x V DD 0.5xVDD + 150 mV V 0.5xVDD - 180mV5 0.5 x VDD 0.5xVDD + 180mV4 V Differential input crosspoint voltage range(1.35V Operation, DDR3L-800/1066/1333/1600) CK, CK, FBIN, FBIN 0.5xVDD - 150 mV 0.5 x V DD 0.5xVDD + 150 mV V 0.5xVDD - 180 mV6 0.5 x VDD 0.5xVDD + 180 mV5 V VID(AC) Differential input voltage7 (1.5V Operation, DDR3-800/1066/1333) CK, CK 350 – VDD mV Differential input voltage6(1.5V Operation, DDR3-1600) CK, CK 300 – VDD mV Differential input voltage6(1.5V Operation, DDR3-1866) CK, CK 270 – VDD mV Differential input voltage6(1.35V Operation, DDR3-800/1066/1333) CK, CK 300 – VDD mV Differential input voltage6 (1.35V Operation, DDR3-1600) CK, CK 270 – VDD mV IOH HIGH-level output current8 All outputs except ERROUT -11 – – mA IOL LOW-level output current8 All outputs except ERROUT 11 – –- mA IOL LOW-level output current ERROUT 25 – – mA VOD Differential re-driven clock swing (1.5V Operation) Yn, Yn 500 – VDD mV Differential re-driven clock swing (1.35V Operation) Yn, Yn 450 – VDD mV

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 18 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE VOX Differential Output Crosspoint Voltage (1.5V Operation) Yn, Yn 0.5xVDD – 100 mV – 0.5xVDD + 100 mV V Differential Output Crosspoint Voltage (1.35V Operation) Yn, Yn 0.5xVDD – 90 mV – 0.5xVDD + 90 mV V

2 RESET, MIRROR

3 This spec applies only when both CK and CK are actively driven LOW. It does not apply when CK/CK are floating. 4 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-275 mV, and when the differential slew rate of CK - CK is larger than 4 V/ns. 5 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-243 mV, and when the differential slew rate of CK - CK is larger than 4 V/ns. 6 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-243 mV, and when the differential slew rate of CK - CK is larger than 3.6 V/ns 7 VID is the magnitude of the difference between the input level on CK and the input level on CK See Diagram (Voltage waveforms; input clock)

8 Default settings

Symbol Parameter Signals Min Nom Max Unit

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 19 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE DC Specifications - Voltage (DDR3U 1.25V) Voltage waveforms; input clock Symbol Parameter Signals Min Nom Max Unit VDD DC Supply voltage (1.25V Operation) 1.19 1.25 1.31 V VREF DC Reference voltage 0.49 x V DD 0.50 x VDD 0.51 x VDD V VTT DC Termination voltage V REF – 40 mV V REF VREF + 40 mV V VIH(AC) AC HIGH-level input voltage (1.25V Operation, DDR3U-800/1066/1333/1600) Data inputs1 VREF + 125 mV – VDD + 0.2 V VIL(AC) AC LOW-level input voltage (1.25V Operation, DDR3U-800/1066/1333/1600) Data inputs1 –0.2 – VREF – 125 mV V VIH(DC) DC HIGH-level input voltage(1.25V Operation) Data inputs1 VREF + 90 mV – VDD + 0.2 V VIL(DC) DC LOW-level input voltage(1.25V Operation) Data inputs1 –0.2 – VREF – 90 mV V VIH(CMOS) HIGH-level input voltage CMOS inputs2 0.65 x VDD – VDD V VIL(CMOS) LOW-level input voltage CMOS inputs2 0– 0 . 3 5 x V D D V VIL (Static) Static LOW-level input voltage3 3 This spec applies only when both CK and CK are actively driven LOW. It does not apply when CK/CK are floating. CK, CK, -– 0 . 3 5 x V D D V VIX(AC) Differential input crosspoint voltage range(1.25V Operation, DDR3U-800/1066/1333/1600) CK, CK, FBIN, FBIN 0.5xVDD - 150 mV 0.5 x V DD 0.5xVDD + 150 mV V 0.5xVDD - 180mV4 4 Extended range for Vix is only allowed for clock (CK and CK) and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-243 mV, and when the differential slew rate of CK - CK is larger than 3.6 V/ns. 0.5 x VDD 0.5xVDD + 180 mV4 V VID(AC) Differential input voltage5 (1.25V Operation, DDR3U-800/1066/1333/1600) 5 VID is the magnitude of the difference between the input level on CK and the input level on CK See Diagram (Voltage waveforms; input clock) CK, CK 250 – VDD mV IOH HIGH-level output current6

6 Default settings

All outputs except ERROUT -11 – – mA IOL LOW-level output current6 All outputs except ERROUT 11 – –- mA IOL LOW-level output current ERROUT 25 – – mA VOD Differential re-driven clock swing (1.25V Operation) Yn, Yn 400 – VDD mV VOX Differential Output Crosspoint Voltage (1.25V Operation) Yn, Yn 0.5xVDD – 90 mV – 0.5xVDD + 90 mV V VIX(AC) VIX(AC) VID

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 20 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Thermal DC Current Specifications Operating Electrical Characteristics Symbol Parameter DDR3/DDR3L/ DDR3U -800 DDR3/DDR3L /DDR3U -1066 DDR3/DDR3L/ DDR3U-1333 DDR3/DDR3L /DDR3U -1600 DDR3-1866 Tcase (max) Case temperature1

1 Measurement procedure JESD51-2

2 This spec is meant to guarantee a Tj of 125C by the SSTE32882KB1 device. Since Tj cannot be measured or observed by users, Tcase is specified instead. Under all thermal condition, the Tj of a SSTE32882KB1 device shall not be higher than 125 oC. 1012o C Symbol Parameter 1 1 The RESET and MIRROR inputs of the device must be held at valid voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is LOW. Conditions Min Typ 2 2 All typical values are at V DD = 1.5V, TA = 25°C. Max Unit II Input current RESET , MIRROR, VI =V DD or GND ±5 QCSEN input current QCSEN , VI =V DD or GND -150 5 IID Input current Data inputs3, VI =V DD or GND 3 DCKEn, DODTn, DAn, DBAn, DRAS , DCAS, DWE, DCSn, PAR_IN are measured while RESET is pulled LOW. ±5 A CK, CK4; VI =V DD or GND 4 The CK and CK inputs have pull-down resistors in the range of 10K to 100K. -5 150 A IOH HIGH-level output current Qn5 5 Qn = QxAn, QxCSn , QxCKEn, QxODTn, QxRAS, QxCAS, QxWE, and QxBAn. -11 mA Yn, Yn, FBOUT, FBOUT -11 mA IOL LOW-level output current Qn5 11 mA Yn, Yn, FBOUT, FBOUT 11 mA ERROUT 25 mA IDD6 6 The supply current is measured as the total current consumptoion on the AVDD, PVDD, and VDD supply current pins. Io= 0. Static standby current RESET = GND and CK = CK = VIL(AC)5 m A Low-Power Static Operating RESET =V DD and CK = CK = VIL(AC), MIRROR = VDD, RC8=X111,IBT OFF 15 mA ICCD Dynamic operating -- input clock only; active outputs RESET =V DD, MIRROR = VDD, VI = VIH(AC) or VIL(AC), RC0[DBA0]=0, RC0[DBA1]=0, CK and CK switching 50% duty cycle, IO = 0, DCS0 = L, DCS1 = H. VDD = VDDMAX -- A/MHz Dynamic operating -- per each data input RESET =V DD, MIRROR = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at one half clock frequency, 50% duty cycle; RC0[DBA0]=0, RC0[DBA1]=0, IO = 0, DCS0 = L, DCS1 = H. VDD = VDDMAX A/Clock MHz/ D Input

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 21 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Capacitance Values Symbol Parameter Conditions DDR3/DDR3L/DDR3U 800/1066/1333/1600 DDR3-1866 Unit Min Typ Max Min Typ Max CI Input capacitance, Data inputs see footnote1,2 1 This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is measured according to JEP147 ("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK AN ALYZER (VNA)") with VDD, VSS, AVDD, AVSS, PVDD, PVSS, V REF applied and all other pins (except the pin under test) floating. Input capacitance are measured with the device default settings when MIRROR=Low. Input capacitance, CK, CK, FBIN, FBIN‘ see footnote1 1.5 - 2.5 1.5 - 2.2 pF CO Output capacitance, Re-driven and Clock Outputs QxA0..QxA15, QxBA0..QxBA2, QxCS0/1, QxCKE0/1, QxODT0/1, QxRAS, QxCAS, QxWE, Y0, Y0.. Y3, Y3 1- 2 p F CI Delta capacitance over all inputs -- 0 . 5 - 0 . 5 p F CIR Input capacitance, RESET, MIRROR, QCSEN VI =V DD or GND; VDD = 1.5 V -- 3 - 3 p F

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 22 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Timing Requirements Symbol Parameter Conditions DDR3/DDR3L- 800/ 1066/1333 DDR3/DDR3L -1600 DDR3-1866 Unit Min Max Min Max Min Max fCLOCK Input Clock Frequency Application Frequency 1 1 All specified timing parameters apply. 300 670 300 810 300 945 MHz fTEST Input Clock Frequency Test Frequency 2 2 Timing parameters specified for frequency band 2 apply. 70 300 70 300 70 300 MHz tCH/tCL Pulse Duration, CK, CK HIGH or LOW 0.4 0.4 0.4 tCK3 3 Clock cycle time. tACT Inputs active time before RESET is taken HIGH4 4 This parameter is not necessarily production tested (see the “Voltage Waveforms for Setup and Hold Times–Hold Time Calculation”figure below). DCKE0/1 = LOW and DCS[n:0] = HIGH 88 8 tCK3 tMRD Command word to command word programming delay Number of clock cycles between two command programming accesses 88 8 tCK3 tINDIS Input Buffers disable time after DCKE[1:0] is LOW DCKE[1:0] = LOW; RESET = HIGH; CK/CK = Toggling; RC9[DBA1] = 1 and RC9[DBA0] = 0 or 1 1 41414 tCK3 tQDIS Output Buffers Hi-Z after QxCKEn is driven LOW DCKE[1:0] = LOW; RESET = HIGH; CK/CK = Toggling; RC9[DBA1] = 1 and RC9[DBA0] = 0 or 1 tCKOFF Number of tCK required for both DCKE0 and DCKE1 to remain LOW before both CK/CK are driven low DCKE[1:0] = LOW; RESET = HIGH; CK/CK = Toggling 55 5 tCK tCKEV Input buffers (DCKE0 and DCKE1) disable time after CK/CK = LOW DCKE[1:0] = LOW; RESET = HIGH; CK/CK = LOW 22 2 tCK tFixedout puts Static Register Output after DCKE0 or DCKE1 is HIGH at the input (exit from Power Saving state) RC9[DBA1] = 1 and RC9[DBA0] = 0 or 1 1 31414 tCK3 tSU Setup Time5 Input valid before CK/CK 100 50 40 ps tH Hold Time6 Input to remain valid after CK/CK 175 125 75 ps

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 23 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE 5 Setup (t SU) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and first crossing of VIH(AC) min. Setup (tSU) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(DC) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value .

6 Hold (t

H) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)MAX and the first crossing of V REF(DC). Hold (tH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between shaded ‘dc level to VREF(DC) region’ use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(DC) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value.

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 24 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Timing Requirements (DDR3U 1.25V) Symbol Parameter Conditions DDR3U-800/ DDR3U-1600 Unit Min Max Min Max fCLOCK Input Clock Frequency Application Frequency 1 1 All specified timing parameters apply. 300 670 300 810 MHz fTEST Input Clock Frequency Test Frequency 2 2 Timing parameters specified for frequency band 2 apply. 70 300 70 300 MHz tCH/tCL Pulse Duration, CK, CK HIGH or LOW 0.4 0.4 tCK3 3 Clock cycle time. tACT Inputs active time before RESET is taken HIGH4

4 This parameter is not necessarily production test ed (see the “Voltage Waveforms for Setup and Hold

Times–Hold Time Calculation” figure below). DCKE0/1 = LOW and DCS[n:0] = HIGH 88 tCK3 tMRD Command word to command word programming delay Number of clock cycles between two command programming accesses 88 tCK3 tINDIS Input Buffers disable time after DCKE[1:0] is LOW DCKE[1:0] = LOW; RESET = HIGH; CK/CK = Toggling; RC9[DBA1] = 1 and RC9[DBA0] = 0 or 1 14 1 4 tCK3 tQDIS Output Buffers Hi-Z after QxCKEn is driven LOW DCKE[1:0] = LOW; RESET = HIGH; CK/CK = Toggling; RC9[DBA1] = 1 and RC9[DBA0] = 0 or 1 1.5 1.5 1.5 1.5 tCK3 tCKOFF Number of tCK required for both DCKE0 and DCKE1 to remain LOW before both CK/CK are driven low DCKE[1:0] = LOW; RESET = HIGH; CK/CK = Toggling 55 tCK tCKEV Input buffers (DCKE0 and DCKE1) disable time after CK/CK = LOW DCKE[1:0] = LOW; RESET = HIGH; CK/CK = LOW 22 tCK tFixedout puts Static Register Output after DCKE0 or DCKE1 is HIGH at the input (exit from Power Saving state) RC9[DBA1] = 1 and RC9[DBA0] = 0 or 1 13 1 3 tCK3 tSU Setup Time5 Input valid before CK/CK 100 50 ps tH Hold Time6 Input to remain valid after CK/CK 175 125 ps

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 25 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE 5 Setup (t SU) nominal slew rate for a rising signal is defi ned as the slew rate between the last crossing of VREF(DC) and first crossing of VIH(AC) min. Setup (tSU) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC) max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(DC) to ac region’, use nom- inal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere be- tween shaded ‘V REF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value . H) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)MAX and the first crossing of VREF(DC). Hold (tH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)MIN and the first crossing of VREF(DC). If the actual signal is always later than the nominal slew rate line between shaded ‘dc level to V REF(DC) region’ use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(DC) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value.

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 26 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Voltage Waveforms for Setup and Hold Times–Hold Time Calculation VSS Hold Slew RateHold Slew Rate Falling SignalRising Signal TR TF VREF(DC) - VIL(DC) MAX TR = VIH(DC) MIN - VREF(DC) TF VDDQ VIH(AC) MIN VIH(DC) MIN VREF(DC) VIL(DC) MAX VIL(AC) MAX nominal slew rate nominal slew rate DC to VREF region DC to VREF region CK CK tSU tH tSU tH

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 27 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Voltage Waveforms for Setup and Hold Times–Setup Time Calculation VSS Setup Slew RateSetup Slew Rate Rising SignalFalling Signal TRTF VREF(dc) - VIL(ac)max TF= VIH(ac)min - VREF(dc) TR= VDDQ VIH(ac) min VIH(dc) min VREF(dc) VIL(dc) max VIL(ac) max nominal slew rate nominal slew rate VREF to ac region CK CK tSU tH tSU tH VREF to ac region

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 28 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE AC Specifications - Output Timing Requirements Symbol Parameter 1 1 See “Qn and Yn Load Circuit” diagram. Conditions DDR3/DDR3L -800/ 1066/1333 DDR3/DDR3L -1600 DDR3-1866 Unit Min Max Min Max Min Max tPDM Propagation delay, single-bit switching (1.5V operation) CKCK to output2 2 See “Propagation Delay Timing” diagram below. 3t PDM range (tPDM_max - tPDM_min) must remain as 350 ps. For example, if tPDM_min for a device is 0.65 ns, it’s tPDM_max cannot be more than 1.0 ns, If tPDM_max for a device is 1.2 ns, it’s tPDM_min cannot be less than 0.85 ns. 4 See “Voltage Waveforms Address Floating” diagram. nsPropagation delay, single-bit switching (1.35V operation) 0.65 1.2 0.65 1.2 tDIS Output disable time (1/2-Clock pre-launch) Yn/Yn (falling edge) to output float 0.5+ tQSK1(min) 0.5+ tQSK1(min) 0.5+ tQSK1(min) psOutput disable time (3/4-Clock pre-launch) 0.25+ tQSK2(min) 0.25+ tQSK2(min) 0.25+ tQSK2(min) tEN Output enable time (1/2-Clock pre-launch) Yn/Yn (falling edge) output driving 0.5- tQSK1(max) 0.5- tQSK1(max) 0.5- tQSK1(max) psOutput enable time (3/4-Clock pre-launch) 0.75- tQSK2(max) 0.75- tQSK2(max) 0.75- tQSK2(max)

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 29 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE AC Specifications - Output Timing Requirements (DDR3U 1.25V) Propagation Delay Timing 1 CK and Yn left out for better visibility. 2 RCA0 is re-driven command address signal based on input CA0. Symbol Parameter 1 1 See “Qn and Yn Load Circuit” diagram. Conditions DDR3U-800/ 1066 DDR3U -1333/1600 Unit Min Max Min Max tPDM Propagation delay, single-bit switching (1.25V operation) CKCK to output2 2 See “Propagation Delay Timing” diagram below. 3 See “Voltage Waveforms Address Floating” diagram. 0.65 1.35 0.65 1.35 ns tDIS Output disable time (1/2-Clock pre-launch) Yn/Yn (falling edge) to output float 0.5+ tQSK1(min) 0.5+ tQSK1(min) ps tEN Output enable time (1/2-Clock pre-launch) Yn/Yn (falling edge) output driving 0.5- tQSK1(max) 0.5- tQSK1(max) ps CK(1) DCS C/A QxCSx Qn(C/A) Qn(C/A) Input Standard C/A Yn(1) QxCKEx, QxODTx QxCSx, QxCKEx, QxODTx nn + 1n + 2n + 3n + 4n + 5n + 6 pre- launch CA0 3/4 Clock Qn(C/A) pre-launch time RCA0(2) RCA0 Yn(1) tPDM

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 30 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Output Buffer Characteristics - edge rates over specified operating free-air temperature range Symbol Parameter Conditions DDR3DDR3L- 800/1066/1333 DDR3/DDR3L-

1600 DDR3-1866 Unit

dV/dt_r rising edge slew rate 1 (1.5V operation) 1 Measured into test load at default register setting except RC3, RC4 and RC5 which are set according to the drive strength to be measured. 2 7 2.0 5.5 2.0 5.0 V/ns V/ns dV/dt_D2 2 Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). absolute difference between dV/dt_r and dV/dt_f 1  1  1-1 V / n s

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 31 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Clock Driver Characteristics at Application Frequency (frequency band 1) Symbol Parameter Conditions DDR3/ DDR3-800 DDR3/ DDR3L-1066 DDR3/ DDR3L-1333 DDR3/ DDR3L-1600 DDR3-1866 Unit M i nM a xM i nM a xM i nM a xM i nM a xM i nM a x tJIT(CC+) Cycle-to-cycle period jitter 04 004 004 003 002 5 p s tJIT(CC-) Cycle-to-cycle period jitter - 4 00- 4 00- 4 00- 3 00- 2 50p s tSTAB Stabilization time - 6 - 6 - 6 - 6 - 5 µs tFDYN Dynamic phase offset -50 50 -50 50 -50 50 -40 40 -30 30 ps tCKSK Fractional Clock Output skew1 - 15 - 15 - 15 - 10 - 10 ps tJIT(PER) Yn Clock Period jitter -40 40 -40 40 -40 40 -30 30 -25 25 ps tJIT(HPER) Half period jitter -50 50 -50 50 -50 50 -40 40 -35 35 ps tPWH/PWL Yn pulse width HIG/LOW duration3 tPW = 1/2tCK - ItJIT(hper)minI to 1/2tCK - ItJIT(hper)maxI tQSK12 Qn Output to Yn clock tolerance (Standard 1/2-Clock Pre-Launch) Output Inversion enabled -150 250 -150 250 -150 250 -140 140 -135 125 psOutput Inversion disabled -150 350 -150 350 -150 350 -140 240 -135 225 t QSK24 Qn Output to Yn clock tolerance (3/4 Clock Pre-Launch) Output Inversion enabled -150 250 -150 250 -150 250 -140 140 -135 125 psOutput Inversion disabled -150 350 -150 350 -150 350 -140 240 -135 225 tSTAOFF Average delay through the register beween the input clock and output clock over “n” cycles5. (1.5V operation) Standard 1/2-Clock Pre-Launch t STAOFF = tPDM + 1/2 tCK 3/4 Clock Pre-Launch t STAOFF = tPDM + 3/4 tCK Average delay through the register beween the input clock and output clock (1.35V operation) Standard 1/2-Clock Pre-Launch t STAOFF = tPDM + 1/2 tCK 3/4 Clock Pre-Launch tSTAOFF = tPDM + 3/4 tCK

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 32 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE 1. This skew represents the absolute output clock skew and contains the pad skew and package skew (See “Clock Output (Yn) Skew”). This parameter is specified for the clock pairs on each side of the register independently. The skew is applicable to left side clock pairs between Y0/Y0 and Y2/Y2, as well as right side of the clock pairs between Y1/Y1 and Y3/Y3. This is not a tested parameter and has to be considered as a design goal only. 2. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package routing skew (See “Qn Output Skew for Standard 1/2-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related to simultaneous switching noise (SSO). 3. The parameter is a measure of the output clock pulse width HIGH/LOW. The output clock duty cycle can be calculated based on tPW. 4. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package routing skew (See “Qn Output Skew for Standard 3/4-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related to simultaneous switching noise (SSO). 5. This parameter measures the delay from the rising differential input clock which samples incoming C/A to the rising differential output clock that will be used to sample the same C/A data. tSTAOFF may vary by the amount of tDYNOFF based on voltage and temperature drift as well as tracking error and jitter. Including this variation tSTAOFF may not exceed the limits set by tSTAOFF(MIN) and tSTAOFF(MAX). 6. See “Measurement Requirement for tSTAOFF and tDYNOFF“. 7. Implies a -3 dB bandwidth and jitter peaking of 3 dB. tDYNOFF6 Maximum variation in delay between the input & output clock - 160 - 130 - 110 - 90 - 70 ps SSC modulation frequency 30 33 30 33 30 33 30 33 30 33 kHz SSC clock input frequency deviation t BAND PLL Loop bandwidth (-3 dB from unity gain) 257 307 357 407 -4 5 7 -M H z Symbol Parameter Conditions DDR3/ DDR3-800 DDR3/ DDR3L-1066 DDR3/ DDR3L-1333 DDR3/ DDR3L-1600 DDR3-1866 Unit

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 33 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Clock Driver Characteristics at Application Frequency (frequency band 1)(DDR3U 1.25V) 1. This skew represents the absolute output clock skew and contains the pad skew and package skew (See “Clock Output (Yn) Skew”). This parameter is specified for the clock pairs on each side of the register independently. The skew is applicable to left side clock pairs between Y0/Y0 and Y2/Y2, as well as right side of the clock pairs between Y1/Y1 and Y3/Y3. This is not a tested parameter and has to be considered as a design goal only. 2. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package routing skew (See “Qn Output Skew for Standard 1/2-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related to simultaneous switching noise (SSO). 3. The parameter is a measure of the output clock pulse width HIGH/LOW. The output clock duty cycle can be calculated based on tPW. Symbol Parameter Conditions DDR3U-800 DDR3U-1066 DDR3U-1333 DDR3U-1600 Unit M i nM a xM i nM a xM i nM a xM i nM a x tJIT(CC+) Cycle-to-cycle period jitter 04 004 004 003 0 p s tJIT(CC-) Cycle-to-cycle period jitter - 4 00- 4 00- 4 00- 3 00p s tSTAB Stabilization time - 6 - 6 - 6 - 6 µs tFDYN Dynamic phase offset -50 50 -50 50 -50 50 -40 40 ps tCKSK Fractional Clock Output skew1 - 15 - 15 - 15 - 10 ps tJIT(PER) Yn Clock Period jitter -40 40 -40 40 -40 40 -30 30 ps tJIT(HPER) Half period jitter -50 50 -50 50 -50 50 -40 40 ps tPWH/PWL Yn pulse width HIG/LOW duration2 tPW = 1/2tCK - ItJIT(hper)minI to 1/2tCK - ItJIT(hper)maxI tQSK12 Qn Output to Yn clock tolerance (Standard 1/2-Clock Pre-Launch) Output Inversion enabled -100 200 -100 200 -100 200 -100 100 psOutput Inversion disabled -100 300 -100 300 -100 300 -100 200 t STAOFF Average delay through the register beween the input clock and output clock. 5. (1.25V operation) Standard 1/2-Clock Pre-Launch t STAOFF = tPDM + 1/2 tCK tDYNOFF6 Maximum variation in delay between the input & output clock - 160 - 130 - 110 - 90 ps SSC modulation frequency 30 33 30 33 30 333 30 33 kHz SSC clock input frequency deviation tBAND PLL Loop bandwidth (-3 dB from unity gain) 257 307 357 407 -M H z

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 34 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE 4. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock skew and package routing skew (See “Qn Output Skew for Standard 3/4-Clock Pre-Launch”). The output clock jitter is not included in this skew. The Qn output can either be early or late. This parameter applies to each side of the register independently. The parameter includes the skew related to simultaneous switching noise (SSO). 5. This parameter measures the delay from the rising differential input clock which samples incoming C/A to the rising differential output clock that will be used to sample the same C/A data. tSTAOFF may vary by the amount of tDYNOFF based on voltage and temperature drift as well as tracking error and jitter. Including this variation tSTAOFF may not exceed the limits set by tSTAOFF(MIN) and tSTAOFF(MAX). 6. See “Measurement Requirement for tSTAOFF and tDYNOFF“. 7. Implies a -3 dB bandwidth and jitter peaking of 3 dB. Clock Output (Yn) Skew tCK tCKSK tCKSK

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 35 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Qn Output Skew for Standard 1/2-Clock Pre-Launch Qn Output Skew for 3/4-Clock Pre-Launch Yn Yn tCK tCK/2 tQSK1 max tCK/2 Qn(C/A) Ideal Qn(C/A) Late Qn(C/A) Early tQSK1 min Yn Yn tCK Qn(C/A) Ideal Qn(C/A) Late tQSK2 max tCK/4 3/4*tCK Qn(C/A) Early tQSK2 min

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 36 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Clock Driver Characteristics at Test Frequency (frequency band 2) Symbol Parameter Conditions Min. Max. Unit tJIT(CC) Cycle-to-cycle period jitter 0 160 ps tSTAB Stabilization time  15 us tCKSK Total Clock Output skew1 1 This skew represents the absolu te output clock skew and contains the pad skew and package skew. 100 ps Fractional Clock Output skew2 2 This skew represents the absolute out put clock skew and contains the pad skew and package skew (see “Clock Output (Yn) Skew”). This parameter is specified for the clock pairs on each side of the register in dependently. The skew is applicable to the left side of the clock pair between Y0/Y0 and Y2/Y2, as well as the right side of the clock pair between Y1/Y1 and Y3/Y3. TBD tJIT(PER) Yn Clock Period jitter -160 160 ps tJIT(HPER) Half period jitter -200 200 ps tQSK13 3 This skew represents the absolute Qn sk ew compared to the output clock Yn, and contains the register pad skew, clock skew, and package routing skew (see “Qn Output Skew for Standard 1/2 Clock Pre-Launch”). The output clock jitter is not included in this skew. This parameter applies to each side of the register independently. The Qn output can either be early or late. Qn Output to clock tolerance (Standard 1/2-Clock Pre-Launch) Output Inversion Enabled -100 TBD ps tQSK1SSO4 4 This skew represents the absolute Qn sk ew compared to the output clock Yn, and contains the register pad skew, clock skew, and package routing skew. The output clock jitter is not included in this skew. This parameter applies to each side of the register independently. This parameter includes the skew related to Simultaneous Switching No ise (SSO). The Qn output can either be early or late. Output Inversion Disabled -100 TBD tQSK25 5 This skew represents the absolute Qn sk ew compared to the output clock Yn, and contains the register pad skew, clock skew, and package routing skew (see “Qn Output Skew for Standard 3/4 Clock Pre-Launch”). The output clock jitter is not included in this skew. This parameter applies to each side of the register independently. The Qn output can either be early or late. Output clock tolerance (3/4 Clock Pre-Launch) Output Inversion Enabled -100 TBD ps tQSK2SSO6 6 This skew represents the absolute Qn sk ew compared to the output clock Yn, and contains the register pad skew, clock skew, and package routing skew. The output clock jitter is not included in this skew. This parameter applies to each side of the register independently. This parameter includes the skew related to Simultaneous Switching No ise (SSO). The Qn output can either be early or late. Output Inversion Disabled -100 TBD tDYNOFF Maximum re-driven dynamic clock offset7 7 The re-driven clock signal is ideally centered in the address/control signal eye. This parameter describes the dynamic deviation from this ideal position including jitter and dynamic phase offset. -500 500 ps

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 37 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Initialization The SSTE32882KB1 can be powered-on at 1.5V , 1.35V or 1.25V . After the voltage transition, stable power is provided for a minimum of 200 µs with RESET asserted. When the reset input (RESET) is low, all input receivers are disabled, and can be left floating. The RESET input is referenced to VDD/2, therefore the reference voltage (VREF) is not required to be stable during reset. In addition, when RESET is low, all control registers are restored to their default states. The QACKE0, QACKE1, QBCKE0 and QBCKE1 outputs must drive low during reset, and all other outputs must float. As long as the RESET input is pulled low the register is in low power state and input termination is not present. A certain period of time (tACT) before the RESET input is pulled high the reference voltage needs to be stable within specification, the clock input signal must be stable, the register inputs DCS[n:0] must be pulled high to prevent any accidental access to the control registers. Also, DCKE0 and DCKE1 inputs must be pulled low for the complete stabilization time (tSTAB). After reset and after the stabilization time (tSTAB), the register must meet the input setup and hold specification before accepting and transfering data from the register inputs to the register outputs. The RESET input must always be held at a valid logic level once the input clock is present. To ensure defined outputs from the register before a stable clock has been supplied, the register must enter the reset state during power-up. It may leave this state only after a low to high transition on RESET while a stable clock signal is present on CK and CK. In the DDR3 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the data outputs will float quickly (except for QACKE0, QACKE1, QBCKE0 and QBCKE1, which are driven low), relative to the time to disable the differential input receivers. The figure below shows the system timing of clock and data during the initialization sequence. Timing of clock and data during initialization sequence 1 CK is left out for better visibility. 2 DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1 are not included in this range. 3 n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.

4 QxCKEn, QxODTn, QxCSn

are not included in this range. CK(1) VDD DCKE[0:1] RESET DA/C(2) DODT[0:1] DCS0 DCSn:1 PLL lock 6 stACT = 8 cycles tINIT = 200 s Controller guarantees high logic Controller guarantees high logic Controller guarantees valid logic Controller guarantees low logic Controller guarantees valid logic Register proper function and timing starting from hereRegister drives CKE low until ready to transfer input signals QxCKE[0:1] QxODT[0:1] QxCSn:0 ERROUT Step 0,1 Step 2 Step 3 Step 5 Step 6 Step 7 Step 4 QxA/C(3) High or Low Y0:3 Register guarantees low logic Register guarantees high logic

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 38 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE From a device perspective, the initialization sequence must be as shown in the following Device Initialization table. SSTE32882KB1 Device Initialization Sequence1. 1. x=Logic low or lolgic high. Z=floating. 2. n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode. 3. The feedback clock (FBOUT and FBOUT) pins may or may not be actively driven by the device. for a minimum of 200 uS with RESET asserted. 6. This indicates the state of QxODTx after RESET switches from low-to-high and before the rising CK edge (falling CK edge). After the first rising CK edge, within (tSTAB - tACT) us, the state of QxODTx is a function of DODTx (high or low). 7. Step 7 is a typical usage example and is not a register requirement. Reset Initialization with Stable Power The timing diagram in the following diagram depicts the initialization sequence with stable power and clock. This will apply to the situation when we have a soft reset in the system. RESET will be asserted for minimum 100ns. This RESET timing is based on DDR3 DRAM Reset Initialization with Stable Power requirement, and is a minimum requirement. Actual RESET timing can vary base on specific system requirement, but it cannot be less than 100ns as required by JESD79-3 Specification. Step Power Inputs: Signals provided by the controller Outputs: Signals provided by the device VDD, AVDD, PVDD RESET Vref DCS [n:0]2 DODT [0:1] DCKE [0:1] DA/C PAR_IN CK,CK QCS [n:0]2 QODT [0:1] QCKE [0:1] QxA/C ERROUT Y[0:3] Y[0:3] FB OUT3 0 0V X or Z X or Z X or Z X or Z X or Z X or Z X or Z X or Z Z Z Z Z Z Z Z 1 0-->VDD X or Z X or Z X or Z X or Z X or Z X or Z X or Z L X or Z X or Z X or Z X or Z X or Z X or Z X or Z VDD 1.5V-->1.35V 1.35V-->1.5V L X or Z X or Z X or Z X or Z X or Z X or Z L Z Z L5 Z H5 ZZ

3 VDD L X or Z X or Z X or Z X or Z X or Z X or Z running ZZ LZ HZ Z

4 VDD L X or Z H X or Z L X or Z X or Z running Z Z LZ HZ Z

5 VDD L stable

voltage HX L XX running Z Z LZ HZ Z

6 VDD H stable

voltage HX L XX running H L6 LX H running running

77 VDD H stable

After Step 6 (Step 7 and beyond), the device outputs are as defined in the device Function Tables.

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 39 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Timing of clock and data during initialization sequence with stable power 1 CK is left out for better visibility. 2 DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1 are not included in this range. 3 QxCKEn, QxODTn, QxCSn are not included in this range. 4 n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode. CK(1) VDD DCKE[0:1] RESET DA/C(2) DODT[0:1] DCS0 DCS[n:1] PLL lock 6 stACT = 8 cycles tINIT_Power_Stable = 100 nS Controller guarantees high logic Controller guarantees high logic Controller guarantees low logic Controller guarantees valid logic Register proper function and timing starting from hereRegister drives CKE low until ready to transfer input signals QxCKE[0:1] QxCS[0:1] ERROUT Step 0,1 Step 2 Step 3 Step 5 Step 6 Step 7 Register guarantees high logic Step 4 Register guarantees low logic H or L H or L Hi-Z Y0:3 QxA/C(3) Controller guarantees valid logic H or L H or L QxODT[0:1] Hi-Z H or L H or L H or L H or L High or Low

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 40 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE SSTE32882KB1 Device Initialization Sequence1 when Power and Clock are Stable 1. x=Logic low or lolgic high. Z=floating. 2. n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode. 3. The feedback clock (FBOUT and FBOUT ) pins may or may not be actively driven by the device. 4. QxCKEn and ERROUT will be driven to these logic states by the register after RESET is driven low and VDD is nominal. 5. This indicates the state of QxODTx after RESET switches from low-to-high and before the rising CK edge (falling CK edge). After the first rising CK edge, within (tSTAB - tACT) us, the state of QxODTx is a function of DODTx (high or low) Parity The SSTE32882KB1 includes a parity checking function. The SSTE32882KB1 accepts a parity bit from the memory controller at its input pin PAR_IN one cycle after the corresponding data input, compares it with the data received on the D-inputs and indicates on its open-drain ERROUT pin (active low) whether a parity error has occurred. The computation only takes place for data which is qualified by at least one of the DCS[n:0] signals being LOW. If an error occurs, and ERROUT is driven low with the third input clock edge after the corresponding data on the D-inputs. It becomes high impedance with the 5th input clock cycle after the data corresponding with a parity error. In case of consecutive errors ERROUT becomes high impedance with the 5th input clock cycle after the last data corresponding with a parity error. The DIMM-dependent signals (DCKE0, DCKE1, DCS0, DCS1, DODT0 and DODT1) are not included in the parity check computations. Parity Timing Scheme Waveforms The PAR_IN signal arrives one input clock cycle after the corresponding data input signals. ERROUT is generated three input clock cycles after the corresponding data is registered. If ERROUTgoes low, it stays low for a minimum of two input clock cycles or until RESET is driven low. The following figure shows the parity diagram with single parity-error occurrence and assumes the occurrence of only one parity error when data is clocked in at the n input clock cycle (PAR_IN clocked in on the n+1 input clock cycle). Step Power Inputs: Signals provided by the contro ller Outputs: Signals provided by the device VDD, AVDD, PVDD RESET Vref DCS [n:1]2 DODT [0:1] DCKE [0:1] DA/C PAR_IN CK, CK QCS [0:1] QODT [0:1] QCKE [0:1] QxA/C ERROUT Y[0:3] Y[0:3] FB OUT3

0 VDD H stable

voltage X X X X X running X X X X X running running

1 VDD H stable

voltage X X X X X running X X X X X running running

2 VDD L stable

voltage X X X X X running Z Z L4 Z H4 ZZ

3 VDD L stable

voltage X X X X X running ZZ LZ HZ Z

4 VDD L stable

voltage H X L X X running Z Z LZ HZ Z voltage HX L XX running Z Z LZ HZ Z voltage HX L XX running H L5 LX H running running

7 VDD H stable

voltage H X X X X running After Step 6 (Step 7 and beyond), the device outputs are as defined in the device Function Tables.

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 41 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Timing of clock, data and parity signals 1 CK left out for better visibility. The next figure shows the parity diagram with two consecutive parity-error occurrences and assumes the occurrence of both parity errors when data is clocked in at the n and n+1 input clock cycles (PAR_IN clocked in on the n+1 and n+2 input clock cycles). Two Consecutive Parity-Error Occurrences 1 CK left out for better visibility. The next figure shows the parity diagram with two parity-error occurrences separated by a clock cycle with no error occurrence. The diagram assumes the occurrence of two parity errors when data is clocked in at the n and n+2 input clock cycles (PAR_IN clocked in on the n+1 and n+3 input clock cycles). Two Parity-Error Occurrences Separated by a Clock Cycle of no Error Occurrence 1 CK left out for better visibility. The next figure shows the parity diagram with two parity-error occurrences separated by two input clock cycles with no error occurrence. The diagram assumes the occurrence of two parity errors when data is clocked in at the n and n+3 input clock cycles (PAR_IN clocked in on the n+1 and n+4 input clock cycles). CK(1) CA Input PAR_IN CA0 CA1 CA2 ERROUT nn + 1n + 2n + 3n + 4n + 5n + 6 ERROUT resulting from CA0 - P0 CK(1) CA Input PAR_IN CA0 CA1 CA2 ERROUT nn + 1n + 2n + 3n + 4n + 5n + 6 ERROUT resulting from CA0 - P0, followed by 2nd error in CA1 - P1 CK(1) CA Input PAR_IN CA0 CA1 CA2 ERROUT n n+1 n+2 n+3 n+4 n+5 n+6 ERROUT resulting from CA0 - P0, followed by 2nd error in CA2 - P2 n+7 n+8 n+9 CA3 P3 P4 CA4 CA5

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 42 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Two Parity-Error Occurrences Separated by two Clock Cycles of no Error Occurrence 1 CK left out for better visibility. The next figure shows the parity diagram with two parity-error occurrences; during chip-select and chip-deselect modes. The diagram assumes the occurrence of both parity errors when data is clocked in at the n and n+1 input clock cycles (PAR_IN clocked in on the n+1 and n+2 input clock cycles). Parity error in the chip-select mod is detected, but parity error in the chip-deselect mode is ignored. Parity-Error Occurrence In Chip-Deselect Mode 1 CK left out for better visibility. The next figure shows the parity diagram with two parity-error occurrences; during normal operation and during control register programming. The diagram assumes the occurrence of both parity errors when data is clocked in at the n and n+3 input clock cycles (PAR_IN clocked in on the n+1 and n+4 input clock cycles). The data on the n+3 input clock pulse is intended for the control mode register. Parity error during control mode register programming is detected and the parity functionality is the same as during normal operation. If a parity error occurs, the command is ignored. CK(1) CA Input PAR_IN CA0 CA1 CA2 ERROUT n n+1 n+2 n+3 n+4 n+5 n+6 ERROUT resulting from CA0 - P0, followed by 2nd error in CA3 - P3 n+7 n+8 n+9 CA3 P3 P4 CA4 CA5 CK(1) CA Input PAR_IN CA0 CA1 CA2 ERROUT nn + 1n + 2n + 3n + 4n + 5n + 6 ERROUT resulting from CA0 - P0, subsequent parity errors during DCSx high ignored DCSx

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 43 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Parity-Error Occurrences During Control Word Programming 1 CK left out for better visibility. POWER SAVING MODES The device supports different power saving mechanisms. When both inputs CK and CK are being held low the device stops operation and enters low-power static and standby operation. It stops its PLL and floats all outputs except QACKE0, QACKE1, QBCKE0 and QBCKE1 which are kept driven low. Before the device is taken out of standby operation by applying a stable input clock signal, the register inputs DCS[n:0] must be pulled high to prevent accidential access to the control registers and DCKE0 as well as DCKE1 must be pulled low for a certain period of time (tACT). The input clock must be stable for a time (tSTAB) before any access to the device takes place. Stopping the clocks (CK = CK = low) will only put the SSTE32882KB1 in low-power mode and will not clear the content of the control words. The control words will reset only when RESET is diven low. A float feature can be enabled by setting the corresponding bit in the control register. This causes the device to monitor all the DCS[n:0] inputs and to float all outputs corresponding with the chip select gated inputs when all the DCS[n:0] inputs are high. If any one of the DCS[n:0] inputs are low, the Qn outputs will function normally. Once all the DCS[n;0] inputs are high, the gated address command inputs to the register can float to conserve input termination power. DCKE0, DCKE1, DODT0 and DODT1 need to be driven by the system all the time. The RESET input has priority over all other power saving mechanisms. When RESET is driven low, it will force the Qn outputs to float, the ERROUT output high, the QACKE0, QACKE1, QBCKE0 and QBCKE1 outputs low, and disables Input Bus Termination (IBT). REGISTER CKE POWER DOWN If RC9[DBA1] is set to “1”, the SSTE32882KB1 monitors both DCKEn input signals and enters into power saving state when it latches Low on both DCKEn inputs and at least one of the DCKEn input has transitioned from High to Low. If any input Chip Select signal (DCS[n:0]) is asserted together with DCKEn, the SSTE32882KB1 transfers the corresponding command to its outputs together with QxCKEn Low. There are two modes of CKE Power Down selected by RC9. Bit DBA0 in RC9 indicates whether the register turns off IBT or keeps IBT on. CK(1) CA Input PAR_IN CA0 CA1 CA2 ERROUT n n+1 n+2 n+3 n+4 n+5 n+6 ERROUTresulting from CA0 - P0, followed by 2nd error during control word access in CA3 - P3 n+7 n+8 n+9 CA3 P3 P4 CA4 CA5 DCS0 DCS1

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 44 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE REGISTER CKE POWER DOWN WITH IBT OFF Upon entry into CKE Power Down mode with IBT off, all register input buffers including IBT are disabled except for CK/CK, DCKEn, FBIN/FBIN, and RESET. The SSTE32882KB1 disables input buffers within tInDIS clocks after latching both DCKEn Low. In order to eliminate and false parity check error, the PAR_IN input buffer has to be kept active for 1 tCK after Address and Command input buffers disabled. After tInDIS, the register can tolerate floating input except for CK/CK, DCKEn and RESET. The SSTE32882KB1 also disables all its output buffers except for Yn/Yn, QxODTn, QxCKEn and FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid phase accurate clock signal. The QxODTn and QxCKEn outputs are driven Low. The register output buffers are Hi-Z tQDIS clock after QxCKEn is driven Low. This is shown in the next figure. Power Down Mode Entry and Exit with IBT Off (1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3. (2) QuadCS disabled: During CKE Power Down Entry/Exit, driving DCS[1,0] LOW is illegal as it will force SSTE32882KB1 into Register Control Word access mode. (3)Upon CKE Power Down exit, QxCSn will be held HIGH for maximum of 1 tCK regardless of what DCSn input level is. For all other operation QxCSn outputs will follow DCSn inputs. H or L CK RESET DAn,DBAn DRAS, DODTn DCKEn DCAS, DWE High or Low High or Low Low High tInDIS High or Low High Hi-z High Yn QxAn, QxODTn High or Low Low High High or Low High Hi-z QxRAS, QxCAS, QxWE QxCKEn High or Low Low Low Hi-z Hi-z tFixedoutput Hi-z Hi-z Hi-z tQDIS Output buffers are Hi-z nn-1 n+4 n+8 n+12 n+16 n+20 nn-1 n+4 n+8 n+12 n+16 n+20 QxBAn High or Low High Hi-z High Low High High Hi-zHigh or Low Low High or Low High or Low PAR_IN Hi-z QxCS[i,0] QxCS[j,1] DCS[i,0] DCS[j,1] H or L Either or both DCKEn inputs are driven High Either or both QxCKEn outputs are driven High tEN see Note 3 see Note 3

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 45 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE To re-enable the register from this power saving state, valid logic levels are required at all register inputs when either or both DCKEn inputs are driven high. Upon either DCKE0 or DCKE1 input going High, the register immediately starts driving High on the appropriate QxCKEn signal. The QxCSn signals are driven High and QxODTn signals are driven Low. Other output signals QxRAS, QxCAS, QxWE, and QxAddr are driven either high or low to ensure stable valid logic an all register outputs when QxCKEn goes High. The register drives output signals to these levels for tFIXEDOUTPUT to allow input receivers to be stabilized. After the input recievers are stabilized, the register output follow their corresponding input levels. When exiting CKE power down mode, either one of the Chip Select register inputs DCSn can be asserted for 1 tCK. For QuadCS capable register, when working in quad rank mode, either two of the Chip Select register inputs DCSn can be asserted for 1 tCK. The register guarantees that input receivers are stabilized within tFIXEDOUTPUT clocks after DCKEn input is driven High. This is shown in the previous diagram. REGISTER CKE POWER DOWN WITH IBT ON Upon entry into CKE Power Down Mode with IBT on, all register input buffers excluding IBT are disabled except for CK/CK, DCKEn, DODTn, FBIN/FBIN, and RESET. The SSTE32882KB1 disables input buffers within tInDIS clocks after latching both DCKEn Low. In order to eliminate any false parity check error, the PAR_IN input buffer has to be kept active for 1 tCK after the Address and Command input buffers are disabled. After tInDIS, the register can tolerate floating input except for CK/CK , DCKEn, DODTn and RESET. The SSTE32882KB1 also disables all its output buffers except for Yn/Yn, QxODTn, QxCKEn and FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid phase accurate clock signal. The QxCKEn outputs are driven Low. The register output buffers are Hi-Z tQDIS clock after QxCKEn is driven Low. This is shown below.

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 46 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Power Down Mode Entry and Exit with IBT On (1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3. (2) QuadCS disabled: During CKE Power Down Entry/Exit, driving DCS[1,0] LOW is illegal as it will force SSTE32882KB1 into Register Control Word access mode. (3) UPon CKE Power Down exit, QxCSn will be held HIGH for a maximum of 1 tCK regardless of what DCSn input level is. For all other operation, QxCSn outputs will follow DCSn inputs. To re-enable the SSTE32882KB1 from this Power Down Mode with IBT on, valid logic levels are required at all device inputs when either or both DCKEn inputs are driven High. Upon either DCKE0 or DCKE1 input going High, the SSTE32882KB1 immediately starts driving High on the appropriate QxCKEn signals. The QxCSn signals are driven high and the QxODTn signals follow the inputs. Other output signals QxRAS, QxCAS, QxWE and QxAddr are driven either high or low to ensure stable valid logic on all device outputs when QxCKEn goes High. The device drives output signals to these levels for t FIXEDOUTPUT to allow input receivers to be stablized. After the input receivers are stablized, the register output follow their corresponding input levels. When exiting CKE power down mode, either one of the Chip Select register inputs DCSn can be asserted for 1 tCK. For QuadCS capable register, when working in quad rank mode, either two of the Chip Select register inputs DCSn can be asserted for 1 tCK. The device guarantees that input receivers are stablized within tFIXEDOUTPUT clocks after DCKEn input is driven High. This is shown in the previous diagram. CK RESET DAn,DBAn DRAS, DODTn DCKEn DCAS, DWE High, Low or Toggling High or Low Low High tInDIS High Hi-z High Yn QxAn, QxODTn Follows Input (High, Low or Toggling) Low High HighHi-z QxRAS, QxCAS, QxWE QxCKEn High or Low Hi-z Hi-z tFixedoutput Hi-z Hi-z tQDIS Output buffers are Hi-z nn-1 n+4 n+8 n+12 n+16 n+20 nn-1 n+4 n+8 n+12 n+16 n+20 QxBAn DCS[j,1] High or Low High Hi-z High High Follows Input (High or Low)Hi-zHigh or Low H or L H, L or Hi-Z H, L or Hi-Z H or L Follows Input (High or Low) tFixedoutput High or Low High or Low High or Low High or Low H, L or Hi-Z H, L or Hi-Z High H or L PAR_IN Hi-z H, L or Hi-Z DCS[i,0] QxCS[j,1] QxCS[i,0] H, L or Hi-Z H or L Either or both DCKEn inputs are driven High Either or both QxCKEn outputs are driven High tEN see Note 3 see Note 3

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 47 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE CLOCK STOPPED POWER DOWN MODE To support S3 Power Management mode or any other operation that allows Yn clocks to float, the SSTE32882KB1 supports a Clock Stopped power down mode. When both inputs CK and CK are being held LOW, (VIL(static)) or float (will eventually settle at LOW because of the (10K-100K Ohm) pulldown resistor in the CK/CK input buffer, the device stops operation and enters low-power static and standby operation. The corresponding timing are shown in “Clock Stopped Power Down Entry and Exit with IBT On” and “Clock Stopped Power Down Entry and Exit with IBT Off“. The register device will stop its PLL and floats all outputs except QACKE0, QACKE1, QBCKE0 and QBCKE1, which must be kept driven LOW. The Clock Stopped power down mode can only be utilized once the DRAM received a self refresh command. In this state, the DRAM ignores all inputs except CKE. Hence, all register outputs besides QxCKE0 and QxCKE1 can be disabled. Clock Stopped Power Down Mode Entry To enter Clock Stopped Power Down mode, the register will first enter CKE power down mode. Once in CKE power down mode, the host will deasserts DCKEn for a minimum of one tCKoff before pulling CK and CK LOW. After holding CK and CK LOW (VIL(static)) for at least one tCKEV , both CK and CK can be floated (because of the (10K-100K Ohm) pulldown resistor in the CK/CK input buffer, CK/CK will stay at LOW even though they are not being driven).The register is now in Clock Stopped Power Down mode. After CK and CK are pulled LOW, the host has to keep DCKEn stable for at least one tCKEV before it can float DCKEn. At this point, all input receivers and input termination of the SSTE32882KB1 are disabled. The only active input circuits are CK and CK, which are required to detect the wake up request from the host. Clock Stopped Power Down Mode Exit To wake up the register after Clock Stopped power down, the host must drive the register inputs DCS[n:0] must be driven to HIGH (to prevent accidental access to the control registers), and DCKEn to LOW. After that, the host can apply a frequency and phase accurate input clock signal. Within tACT after CK and CK resumed normal operation, the SSTE32882KB1 outputs start becoming a function of their corresponding inputs. The state of the DCS[n:0] inputs must not be changed before the end of tSTAB. The input clock CK and CK must be stable for a time equal or greater than tSTAB before any access to the SSTE32882KB1 can takes place.

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 48 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Clock Stopped Power Down Entry and Exit with IBT On (1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3. (2) With RC9 DBA0=’0’. (3) When CK/CK inputs are floated, CK/CK inputs are pulled LOW by the (10K-100K Ohm) pulldown resistor in the CK/CK input buffer. (4) Upon CKE Power Down exit, QxCSn will be held HIGH for maximum of 1 tCK regardless of what DCSn input level is. For all other operation QxCSn outputs will follow DCSn inputs. DAn, DBAn Input n-1 QxODTn n pp + 4 QxCKEn DCS[j,1] Output DODTn tSTAB mm + 4 Hi-Z driven Low Hi-Z Hi-Z qp+7 m+8 x x tCKoff tCKEV tFixedoutput ODT8 ODT10 ODT11ODT9 ODT12 ODT14 ODT15ODT13 ODT16 ODT17 Hi-ZQxRAS, QxWE QxCAS, n+4 tInDIS DRAS DCAS DWE DCKEn High or LowHigh or Low DCS[i,0] High or LowHigh or Low H, L or Hi-Z H or L High, Low or Toggling High, Low or Toggling Either or both DCKEn inputs are driven High Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Low Low tFixedoutput H, L or Hi-Z RESET nn-1 Yn QxAn, QxBAn H or L High or Low High or Low Follows Input (High, Low or Toggling)Follows Input (High, Low or Toggling) n+4 Either or both QxCKEn outputs are driven High QxCS[i,0] Hi-Z Follows Input (H or L)High or Low QxCSn and QxODTn transfer from Hi-Z to high/low with in-accurate phase tQDIS QxCS[j,1] Follows Input (H or L)High or Low Hi-Z High PAR_IN H, L or Hi-Z H, L or Hi-Z H, L or Hi-Z Hi-Z H, L or Hi-Z Hi-Z L or Float* tEN High High High High tACT CK/CK High High High High see Note 3 see Note 3

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 49 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Clock Stopped Power Down Entry and Exit with IBT Off (1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3. (2) With RC9 DBA0=’1’. (3) When CK/CK inputs are floated, CK/CK inputs are pulled LOW by the (10K-100K Ohm) pulldown resistor in the CK/CK input buffer. (4) Upon CKE Power Down exit, QxCSn will be held HIGH for maximum of 1 tCK regardless of what DCSn input level is. For all other operation QxCSn outputs will follow DCSn inputs. DAn, DBAn Input n-1 QxODTn n pp + 4 QxCKEn DCS[j,1] Output DODTn tSTAB mm + 4 Hi-Z driven Low Hi-Z Hi-Z qp+7 m+8 x x tCKoff tCKEV tFixedoutput ODT8 ODT10 ODT11ODT9 ODT12 ODT14 ODT15ODT13 ODT16 ODT17 Hi-ZQxRAS, QxWE QxCAS, n+4 tInDIS DRAS DCAS DWE DCKEn LowHigh or Low DCS[i,0] High or Low H or L High or Low High or Low Either or both DCKEn inputs are driven High Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Low Low tFixedoutput RESET nn-1 Yn QxAn, QxBAn H or L High or Low High or Low High or Low n+4 Either or both QxCKEn outputs are driven High QxCS[i,0] Hi-Z High or Low QxCSn and QxODTn transfer from Hi-Z to high/low with in-accurate phase tQDIS QxCS[j,1] High or Low Hi-Z High High High or Low High High Low High PAR_IN Hi-Z Hi-Z tEN High High High High tACT L or Float*CK/CK see Note 3 see Note 3

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 50 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE DYNAMIC 1T/3T TIMING TRANSACTION AND OUTPUT INVERSION ENABLING/DISABLING Output Inversion is always enabled by default, after RESET is de-asserted, to conserve power and reduce simultaneous output switching current. All A-outputs will follow the equivalent inputs, however the following B-outputs will be driven to the complement of the matching A-outputs: QBA3 - QBA9, QBA11, QBA13 - QBA15, QBBA0 - QBBA2. The Output Inversion feature is not used during DRAM MRS command access. When Output Inversion is disabled, all corresponding A and B output drivers of the SSTE32882KB1 are driven to the same logic levels. Output Inversion must be disabled when the MRS and EMRS commands must be issued to the DRAMs, for example, to assure that the same programming is issued to all DRAMs in a rank. With Output Inversion disabled during MRS access, in order to allow correct DRAM accesses with the consequently increased simultaneous switching propagation delay the devices supports 3T timing. If this feature is invoked the device drives the received data on its outputs for thee cycles instead of one. The only exceptions are the QxCS[n:0] outputs, which are the QACS0, QACS1, QBCS0, and QBCS1 outputs in the QuadCS disabled mode and are QCS[3:0] in the QuadCS enabled mode. When the device decodes the MRS command (DRAS=0, DCAS=0, DWE=0 and only one DCSn=0), it will disable the Output Inversion function and pass the DRAM MRS command with an additional (one) clock delay on the appropriate QnCSx signal to the DRAM. Back-to-back MRS command via the SSTE32882KB1 must have a minimum of three clock delays. The SSTE32882KB1 will automatically enable Output Inversion if there is no DRAM MRS command three clocks after the previous MRS command. The inputs and outputs relationships for 1T timing and 3T timing are shown in the following three diagrams. Output Inversion Functional Diagram QAxxx output QBxxx output Dxxx input MRS Decoder Register

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 51 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE 1T Timing During Normal Operation 1 CK and Yn left out for better visibility. 2 n = 1 for QuadCS disabled, n = 3 for QuadCS enabled. CK(1) DCKE[1:0] DA[15:0], DBA[2:0] Input Outputs @ 1T n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 DODT[1:0] DRAS DCAS, DWE DCS0 DCSn:1 Yn(1) n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 QCKE[1:0] QAA[15:0], QABA[2:0], QODT[1:0] QRAS QCAS, QWE QCS0 QCSn:1 QBA12, QBA10, QBA[2:0] QBA[15:13], QBA11, QBA[9:13], QBBA[2:0]

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 52 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE 3T Timing During DRAM MRS Command 1 CK and Yn left out for better visibility. 2 n = 1 for QuadCS disabled, n = 3 for QuadCS enabled. CK(1) DCKE[1:0] DA[15:0], DBA[2:0] Input Outputs @ 3T n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 DODT[1:0] DRAS DCAS, DWE DCS0 DCSn:1 Yn(1) n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 QCKE[1:0] QODT[1:0] QRAS QCAS, QWE QCS0 QCSn:1 Output Inversion Disabled Output Inversion enabled QAA[15:0], QABA[2:0], QBA12, QBA10, QBA[2:0] QBA[15:13], QBA11, QBA[9:3], QBBA[2:0]

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 53 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE 3T Timing During Multiple DRAM MRS Commands 1 CK and Yn left out for better visibility. 2 n = 1 for QuadCS disabled, n = 3 for QuadCS enabled. CK(1) DCKE[1:0] DA[15:0], DBA[2:0] Input Outputs @ 3T n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 DODT[1:0] DRAS DCAS, DWE DCS0 DCSn:1 Yn(1) n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 QCKE[1:0] QODT[1:0] QRAS QCAS, QWE QCS0 QCSn:1 Output Inversion Disabled Output Inversion enabled QAA[15:0], QABA[2:0], QBA12, QBA10, QBA[2:0] QBA[15:13], QBA11, QBA[9:3], QBBA[2:0]

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 54 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE CONTROL WORDS The SSTE32882KB1 registers have internal control bits for adapting the configuration of certain device features. The control bits are accessed by the simultaneous assertion of both DCS0 and DCS1 in the QuadCS disabled mode. In the QuadCS enabled mode, the simultaneous assertion of both DCS2 and DCS3 during normal operation, and the assertion of all four DCS[3:0] inputs also results in control word access. However, assertion of any three DCS[3:0] inputs is not legal. Register Qn outputs including QxCKE0, QxCKE1, QxODT0 and QxODT1 remain in their previous state. Select signals QxCS[n:0] are set to high during control word access. The SSTE32882KB1 allocates decoding for up to 16 words of control bits, RC0 through RC15. Selection of each word of control bits is presented on inputs DA0 through DA2 and DBA2. Data to be written into the configuration registers need to be presented on DA3, DA4, DBA0 and DBA1. Bits DA[15:5] need to be low, and at least one DCKEn input must be high, for valid data access. If Power Down mode is enabled in RC9[DBA1], at least one DCKE must be high for valid control word access. The inputs on DRAS, DCAS, DWE, and DODT[1:0] can be either high or low, and are ignored by the SSTE32882KB1 during control word access. In all cases Address and command parity is checked during control word write operations. ERROUT is asserted and the command is ignored if a parity error is detected. Using this mechanism, controllers may use the SSTE32882KB1 to validate the address and command bus signal integrity to the module as long as one or more of the parity checked input signals DA3-DA15, DBA0, DBA1, DRAS, DCAS, DWE are kept high. Control word access must be possible at any defined frequency independent of the current setting of RC2[DBA1] control registers.

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 55 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Control Words The device features a set of control words, which allow the optimization of the device properties for different raw card designs. The different control words and settings are described below. Any change to these control words requires some time for the device to settle. For changes to the control word setting, except for RC2 (bits DBA1 and DA3) and RC10, the controller needs to wait t MRD after the last control word access, before further access to the DRAM can take place. For any changes to the clock timing (RC2: bits DBA1 and DA3) and RC10, this settling may take up to tSTAB time. All chip select inputs (DCS[n:0]) must be kept high during that time. The Control Words can be accessed and written to when running within any one defined frequency band. CONTROL WORD DECODING The values to be programmed into each control word are presented on signals DA3, DA4, DBA0 and DBA1 simultaneously with the assertion of the control word access through DCS0 and DCS1, or DCS2 and DCS3 in the QuadCS enabled mode, and the address of the control word on DA0, DA1, DA2 and DBA2. 7 is vendor specific. Every time the device is reset, its default state is restored. Stopping the clocks (CK = CK = low) to put the device in low-power mode will not alter the control word settings.

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 56 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Control Word Decoding with QuadCS Mode Disabled Signal Control Word Symbol DCS0 DCS1 DBA2 DA2 DA1 DA0 Meaning None n/a H X X X X X No control word access None n/a X H X X X X No control word access Control word 0 RC0 L L L L L L Global Features Control word Control word 1 RC1 L L L L L H Clock Driver Enable Control word Control word 2 RC2 L L L L H L Timing Control word Control word 3 RC3 L L L L H H CA Signals Driver Characteristics Control word Control word 4 RC4 L L L H L L Control Signals Driver Characteristics Control word Control word 5 RC5 L L L H L H CK Driver Characteristics Control word Control word 6 RC6 L L L H H L Reserved, free to use by vendor Control word 7 RC7 L L L H H H Reserved, free to use by vendor Control word 8 RC8 L L H L L L Additional IBT Setting Control Word Control word 9 RC9 L L H L L H Power Saving Settings Control word Control word 10 RC10 L L H L H L Encoding for RDIMM Operating Speed Control word 11 RC11 L L H L H H Encoding for RDIMM Operating V DD Control word 12 RC12 L L H H L L Reserved for future use Control word 13 RC13 L L H H L H Reserved for future use Control word 14 RC14 L L H H H L Reserved for future use Control word 15 RC15 L L H H H H Reserved for future use

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 57 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Control Word Decoding with QuadCS Mode Enabled Signal Control Word Symbol DCS[3:0] DBA2 DA2 DA1 DA0 Meaning None n/a HXHX X X X X No control word access None n/a HXXH X X X X None n/a XHHX X X X X None n/a XHXH X X X X None n/a HLLL X X X X Ilegal Input States None n/a LHLL X X X X None n/a LLHL X X X X None n/a LLLH X X X X Control word 0 RC0 LLHH or HHLL or LLLL L L L L Global Features Control word Control word 1 RC1 L L L H Clock Driver Enable Control word Control word 2 RC2 L L H L Timing Control word Control word 3 RC3 L L H H CA Signals Dr iver Characteristics Control word Control word 4 RC4 L H L L Control Signals Driver Characteristics Control word Control word 5 RC5 L H L H CK Driver Characteristics Control word Control word 6 RC6 L H H L Reserved, free to use by vendor Control word 7 RC7 L H H H Reserved, free to use by vendor Control word 8 RC8 H L L L Additional IBT Setting Control Word Control word 9 RC9 H L L H Power Saving Settings Control word Control word 10 RC10 H L H L Encoding for RDIMM Operating Speed Control word 11 RC11 H L H H Encoding for RDIMM Operating V DD Control word 12 RC12 H H L L Reserved for future use Control word 13 RC13 H H L H Reserved for future use Control word 14 RC14 H H H L Reserved for future use Control word 15 RC15 H H H H Reserved for future use

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 58 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE CONTROL WORD FUNCTIONS The following sections describe the contents of each control word. RC0: Global Features Control Word Output Inversion: When Output Inversion is disabled, all A and B output drivers of the SSTE32882KB1 are driven to the same levels. Output Inversion may be enabled to conserve power, reducing simultaneous switching output currents in the SSTE32882KB1. When Output Inversion is enabled, all A outputs will follow the equivalent inputs, however the following B outputs will be driven to the complement of the matching A output: QBA03-QBA9, QBA11, QBA13 - QBA15, QBBA0 - QBBA2. Output Inversion does not affect SSTE32882KB1 control word programming. Output floating refers to allowing many A/B outputs to enter a hi-Z state when they are not being used. This is to conserve power when the outputs are resistively terminated to a voltage (e.g., V DD, VTT, or VSS). When output floating is enabled, the following outputs (on both matching A and B outputs) are hi-Z when not actively driven: QxAn, QxBAn, QxRAS , QxCAS, and QxWE. Output floating is independent of Output Inversion and does not affect SSTE32882KB1 control word programming. Input Definition Encoding DBA1 DBA0 DA4 DA3 x x x 0 Output Inversion Output Inversion enabled x x x 1 Output Inversion disabled x x 0 x Float outputs Float disabled x x 1 x Float enabled x 0 x x A outputs disabled A outputs enabled x 1 x x A outputs disabled 0 x x x B outputs disabled B outputs enabled 1 x x x B outputs disabled Output Inversion Functional Diagram QAxxx output QBxxx output Dxxx input RC0-DA3 Control Bit Register

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 59 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE A or B output disable allows the use of the SSTE32882KB1 in reduced parts count applications such as DDR3 Mini-RDIMMs. When output disable is asserted, all outputs on the corresponding side of the register, including the clock drivers, remain in Hi-Z at all times. When RC0[DBA0] = 1, all A-side Q-outputs and Y1 and Y3 outputs will be disabled. When RC0[DBA1] = 1, all B-side Q-outputs and Y0 and Y2 outputs will be disabled. When RC0[DBA0] = 1 and RC0[DBA1] = 1, all A-side and B-side Q-outputs and Yn outputs will be disabled. RC1: Clock Driver Enable Control Word Output clocks may be individually turned on or off to conserve power. The system must read the module SPD to determine which clock outputs are used by the module. The PLL remains locked on CK/CK unless the system stops the clock inputs to the SSTE32882KB1 to enter the lowest power mode. RC2: Timing Control Word Input Definition Encoding DBA1 DBA0 DA4 DA3 x x x 0 Disable Y0/Y0 clock Y0/Y0 clock enabled xx x 1 Y 0 / Y 0 clock disabled x x 0 x Disable Y1/Y1 clock Y1/Y1 clock enabled xx 1 x Y 1 / Y 1 clock disabled x 0 x x Disable Y2/Y2 clock Y2/Y2 clock enabled x1 x x Y 2 / Y 2 clock disabled 0 x x x Disable Y3/Y3 clock Y3/Y3 clock enabled 1x x x Y 3 / Y 3 clock disabled Input Definition Encoding DBA1 DBA0 DA4 DA3 xx x 0 Address- and command-nets pre-launch (Control Signals QxCKE, QxCS, QxODT do not apply) Standard (1/2 Clock) x x x 1 Address and command nets pre-launch (3/4 Clock) xx 0 x 1T/3T Output timing 1T timing xx 1 x 3T timing (1) 1 There is no floating once 3T timing is activated. x0 x x Input Bus Termination(2) 2 If MIRROR is ‘HIGH’ then Input Bus Termination (IBT) is turned off, or on all inputs except the DCSn and DODTn inputs. 100  x 1 x x 150  0x x x Frequency Band Select Operation (Frequency Band 1) 1 x x x Test Mode (Frequency Band 2)

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 60 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE The IBT control is also located in this control word, with two options of 100 or 150 which can be selected to adapt to different system scenarios. At power-up, the SSTE32882KB1 IBT defaults to 100. The system controller can reprogram the termination resistance to 150 by setting this bit. Only the DAn, DBAn, DRAS, DCAS, DWE, DCSn, DODTn, DCKEn, and PAR_IN inputs have the IBT. The CK, CK, FBIN, FBIN, RESET, and MIRROR inputs do not have IBT. If MIRROR is ‘HIGH’ then it is assumed the register is located on the back side of a module where two registers are tied together on the input side. In this case, for the register on the back side, the IBT are turned off on all inputs except the DCSn and DODTn inputs. The following diagram illustrates the pre-launch feature whereby double loaded nets in a 2-rank configuration can be driven with an earlier signal compared to output clock and control in order to compensate for the slower signal travel speed. This timing applies at all supported frequencies. Effective IBT Tolerance Requirement Min Max Total Effective IBT Value Tolerance1

1 Example: for 100 Ohm IBT, Min = 90 Ohms, Max = 110 Ohms

-10% +10% Mismatch Tolerance Between R-IBT-Up and R-IBT-Down Max Mismatch Tolerance Between R-IBT-Up and R-IBT-Down1 1 (1 - R-IBT-Up/R-IBT-Down) *100% < ABS(5%) ABS(5%)

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 61 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Standard versus Address and Command-Nets pre-launch Timing 1 CK and Yn left out for better visibility. 2 RCA0 is re-driven command address signal based on input CA0. Output driver characteristics are separately controlled for outputs that are often loaded with twice as many DRAMs as the other outputs. Outputs are grouped as follows:

• CA Signals =QxA0-QxAn, QxBA0-QxBAn, QxRAS, QxCAS, QxWE
• Control Signals = QxCSn, QxCKEn, QxODTn
• CK = Yn .. Yn CK(1) DCS C/A QxCSx, Qn(C/A) Qn(C/A) Input Standard C/A Yn(1) QxCKEx, QxODTx QxCSx, QxCKEx, QxODTx nn + 1n + 2n + 3n + 4n + 5n + 6 pre- launch CA0 3/4 Clock Qn(C/A) pre-launch time RCA0(2) RCA0 Yn(1)

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 62 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE RC3: CA Signals Driver Characteristics Control Word RC4: Control Signals Driver Characteristics Control Word Input Definition Encoding DBA1 DBA0 DA4 DA3 xx 0 0 Command/Address Driver-A Outputs Light Drive (4 or 5 DRAM Loads) x x 0 1 Moderate Drive (8 or 10 DRAM Loads) x x 1 0 Strong Drive (16 or 20 DRAM Loads) xx 1 1 R e s e r v e d 00 x x Command/Address Driver-B Outputs Light Drive (4 or 5 DRAM Loads) 0 1 x x Moderate Drive (8 or 10 DRAM Loads) 1 0 x x Strong Drive (16 or 20 DRAM Loads) 11 x x R e s e r v e d Input Definition Encoding DBA1 DBA0 DA4 DA3 xx 0 0 Control Driver-A Outputs Light Drive (4 or 5 DRAM Loads) x x 0 1 Moderate Drive (8 or 10 DRAM Loads) xx 1 0 R e s e r v e d xx 1 1 R e s e r v e d 00 x x Control Driver-B Outputs Light Drive (4 or 5 DRAM Loads) 0 1 x x Moderate Drive (8 or 10 DRAM Loads) 10 x x R e s e r v e d 11 x x R e s e r v e d

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 63 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE RC5: CK Driver Characteristics Control Word RC8: Additional IBT Setting Control Word Input Definition Encoding DBA1 DBA0 DA4 DA3 xx 0 0 Clock Y1, Y1, Y3, and Y3 Output Drivers Light Drive (4 or 5 DRAM Loads) x x 0 1 Moderate Drive (8 or 10 DRAM Loads) x x 1 0 Strong Drive (16 or 20 DRAM Loads) xx 1 1 R e s e r v e d 00 x x Clock Y0, Y0 , Y2, and Y2 Output Drivers Light Drive (4 or 5 DRAM Loads) 0 1 x x Moderate Drive (8 or 10 DRAM Loads) 1 0 x x Strong Drive (16 or 20 DRAM Loads) 11 x x R e s e r v e d Input Definition Encoding DBA1 DBA0 DA4 DA3 x0 0 0 IBT Compatibility Settings IBT as defined in RC2 0x x x Mirror Mode IBT Off when MIRROR is HIGH1 1 If MIRROR is HIGH, then Input Bus Terminati on (IBT) is turned off on all inputs, except DCSn and DOD- Tn inputs. 1x x x IBT On when MIRROR is HIGH2

2 When DBA0 = 1, DA4 = 1, or DA3 = 1, IBT on all inputs is turned off no matter what the DBA1 setting

may be. x0 0 1 Input Bus Termination1 Reserved x0 1 0 200 x0 1 1 Reserved x1 0 0 300 x1 0 1 Reserved x1 1 0 Reserved x1 1 1 Off3 3 With this setting, no matter what the logic level of the MIRROR input pin may be, IBT on all inputs (in- cluding DCSn and DODTn) is turned off.

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 64 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE RC9: Power Saving Settings Control Word The SSTE32882KB1 features a weak drive mode, which is a variant of the floating mode set in RC0. If Bit DA4 of RC0 is set to ‘1’, then Bit DA3 of RC9 selects between floating mode and weak drive mode. The SSTE32882KB1 register supports different power down modes. By default, the Power Down feature is disabled (RC9[DBA1]=0). The register ignores CKE Power Down mode setting when this function is disabled. If the CKE Power Down mode is enabled (RC9[DBA1]=1), then power down is invoked once both DCKE0 and DCKE1 are low. Bit DBA0 selects how IBT and ODT behaves. Input Definition Encoding DBA1 DBA0 DA4 DA3 xx x 0 Weak Drive Mode (when DCSn=high, DA3=1 and RC0[DA4=1]) Floating as defined in RC0 [DA4] xx x 1 Typical weak drive enabled1 Weak Driver Impedance: 70 (min), 100 (nom), 120 (min) 1 When all DCS pins are HIGH (i.e. SDRAM is in deselected stat e), there is no memory access to the DRAM, and the Register output can either be in a Normal Drive Mode, floated, or driven under Weak Drive Mode. A Weak Drive Mode is a mode in which CA signal output drivers (QxA0-QxAn, QxBA0-QxBAn, QxRAS, QxCAS, QxWE) will be driven 2.5 to 3 times weaker than the Light Drive as specified in RC3, and the SDRAM VIL/VIH DC limit will be maintained. The Weak Drive Mode entry and exit timing is bounded by tDIS and tEN respectively. xx 0 x Reserved Reserved xx 1 x R e s e r v e d 10 x x CKE Power Down Mode CKE power down with IBT ON, QxODT is a function of DxODT 1 1 x x CKE power down with IBT off, QxODT held LOW 0x x x CKE Power Down Mode Enable Disabled 1x x x E n a b l e d

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 65 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE RC10: Encoding for RDIMM Operating Speed The encoding value is used to inform the register the operating speed that it is being run at in a system. It is not an indicator of how fast or slow a register can run RC11: Operating Voltage VDD and VREFCA Control Word1 RC11 is used to inform the SSTE32882KB1 under what operating voltage VDD will be used. The register can use the information to optimize functionality and performance at DDR3L conditions. antee all timings and specifications for DDR3 & DDR3L, the register must be configured accordantly. 2. Mandatory for all register supporting 1866 and beyond. Input Definition Encoding DBA1 DBA0 DA4 DA3 x000 f < 800 MTS DDR3/DDR3L/DDR3U-800 (default) x001 8 0 0 M T S < f < 1066 MTS DDR3/DDR3L/DDR3U-1066 x0101 0 6 6 M T S < f < 1333 MTS DDR3/DDR3L/DDR3U-1333 x0111 3 3 3 M T S < f < 1600 MTS DDR3/DDR3L/DDR3U-1600 x1001 6 0 0 M T S < f < 1866 MTS DDR3-1866 x1011 8 6 6 M T S < f < 2133 MTS DDR3-2133 x110 R e s e r v e d R e s e r v e d x111 R e s e r v e d R e s e r v e d Input Definition Encoding DBA1 DBA0 DA4 DA3 xx00 Register VDD Operating V oltage DDR3 1.5V mode xx01 D D R 3 L 1 . 3 5 V m o d e xx10 D D R 3 U 1 . 2 5 V m o d e xx11 R e s e r v e d x0xx R e g i s t e r V r e f C A

2 External VrefCA2

x1xx I n t e r n a l V r e f C A 2 0xxx R e s e r v e d 1xxx R e s e r v e d

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 66 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Test Circuits and Switching Waveforms Parameter Measurement Information All input pulses are supplied by generators having the following characteristics: 300MHz PRR  945 MHz; Zo = 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified. The outputs are measured one at a time with one transition per measurement. Qn and Yn Load circuit for propagation delay and slew measurement 1 CL is parasitic (probe and jig capacitance). Voltage waveforms; propagation delay times VTT = VDD/2 VICR Cross Point V oltage VI(P-P) = 500mV (1.5V operation), 450mV (1.35V operation) or 400mv (1.25V operation). tPDM1, tPDM2 the larger number of both has to be taken when performing tPDM max measurement, the smaller number of both has to be taken when performing tPDM min measurement. CL<2.5pF(1) DUT OUT Test point CK Inputs TL = 50 RL = 100 Test point Test point VTT RL=50CK CK Trace delay matched on load board VTTQ Output VTT CK CK tPDM1t PDM2 VICR VICR VI(P-P)

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 67 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Voltage waveforms address floating Refer to “Calculating the virtual VREF crossing point”. Enabling and disabling the CA outputs must not violate DRAM setup and hold time requirements. Therefore a tDIS transition may not occur earlier than the earliest (HL/LH) transition and a tEN transition may not occure later than the latest (HL/LH) transition. Regular transitions are measured between CK/CK and CA/VTT crossings however a VTT crossing is not available in the state where the outputs are Hi-Z. To allow a correct and not overly conservative measurement a virtual VTT crossing point is defined below. The calculation of the virtual VTT crossing point is shown in the Figure, “Calculating the virtual VTT crossing point”. The voltage levels for yxa and yxb are measured from VTT (VDD/2) and should be selected such that the region between t1 and t2 covers a linear range and represents a typical slope of the waveform within the transition area. They have to be used signed in the formula. Outputs Yn Yn tDIS tEN VOX VOX VOD CK CK DCSn QxCSn virtual VTT crossing*

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 68 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Calculating the virtual VTT crossing point tDIS tEN = t1a + y1a(t1a-t2a)/(y2a-y1a) VOL VOH VTTVTT y1b y2b actual waveform y1b y2b t2b t1b UCK=UCK y2a y2a y1a y1a tEN t2a t1a Yn Yn tDIS = t1b + y1b(t1b-t2b)/(y2b-y1b) VTT=VDD/2

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 69 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Voltage waveforms, HIGH-to-LOW slew rate measurement Voltage waveforms, LOW-to-HIGH slew rate measurement AC Level for Slew Rate Measurement (DDR3U 1.25V) AC Level for Slew Rate Measurement DDR3/DDR3L-800/1066/1333/1600 DDR3-1866 AC Level (1.5V) 150mV 135mv AC Level (1.35V) 135mV DDR3U-800/1066/1333/1600 AC Level (1.25V) 125mV dv_f dt_f + AC Level - AC Level VOH VOL OUTPUT Vtt dv_r dt_r + AC Level - AC Level VOH VOLOUTPUT Vtt

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 70 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Error Output Load Circuit and Voltage Measurement Information All input pulses are supplied by generators having the following characteristics: 300MHz  PRR  945 MHz; Zo = 50 ; input slew rate = 1 V/ns ± 20%, unless otherwise specified. Load circuit, ERROUT Outputs 1 CL includes probe and jig capacitance. RL=50 CL=10pF DUT OUT VDD Test point See Note (1)

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 71 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE The output driver characteristics are separately controlled for outputs that are often loaded with twice as many DRAMs as the other outputs. Outputs are grouped as follows:

• CA Signals =QxA0-QxAn, QxBA0-QxBAn, QxRAS, QxCAS, QxWE
• Control Signals = QxCSn, QxCKEn, QxODTn
• CK = Yn .. Yn Register Output Slew-Rate & R-on Targets for Each Drive Strength as shown below. Output Slew-Rate & R-on (targets) Drive Settings Output Driver R-on Targets (Ohms) Output Slew-Rate (V/ns) DDR3-800/1066/1333 DDR3-1600 DDR3L-800/1066/1333/ 1600 Min Nom Max Min Max Min Max Min Max Light 22 26 30 2 7 2 5.5 1.8 5.0 Moderate 16 19 22 2 7 2 5.5 1.8 5.0 Strong 12 14 16 2 7 2 5.5 1.8 5.0

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 72 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Measurement Requirement for tstaoff and tdynoff Voltage waveforms, Reset to ERROUT tPLH Measurement CK CK Yn Yn tstaoff(min) 1. tstaoff = propagation delay for clock signal (rising CK input clock edge to rising Yn output clock edge). tdynoff 2. tdynoff = maximum tstaoff variation over voltage and temperature. This includes all sources of jitter and drift (e.g.Thermal noise, supply noise, voltage/temperature drift, SSC tracking, SSO, etc) except reference clock noise. tstaoff tstaoff(max) 0.65V VOH VDD/2 VDD tPLH OUTPUT INPUT CMOS RESET Open Drain ERROUT

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 73 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE Voltage waveforms, CK to ERROUT tHL Measurement VTT = VDD/2 Voltage waveforms, CK to ERROUT tLH Measurement Recommended Filtering for the Analog Power Supply (A VDD) Place the 2200pF capacitor close to the PLL. Use a wide trace for the PLL analog power and ground. Connect PLL and caps to AGND trace and connect trace to one GND via (farthest from PLL). Bead is 0.8 DC max, 600 at 100MHz. Open Drain Output ERROUT VID CK CK VICR tLH VOH VOL VTT 0.65V VOH tLH Open Drain Output ERROUT VID CK CK VICR VDDQ GND VIA CARD VIA CARD BEAD 4.7uF 0.1uF 2200pF AVDD AGND SSTEF328821 SSTE32882

1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT 74 SSTE32882KB1 7326/3 SSTE32882KB1 1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE RANGE

Ordering Information

Temp. Shipping

8 Tape and Reel

Commercial (0o C to +70o C)Blank Range XX Package 32882KB1 Registering Clock Driver with Parity Test XXXX Device Low Profile, Fine Pitch, Ball Grid Array - GreenAKG Carrier SSTE Type (0.65mm ball pitch, 11 x 20 grid, 8.0mm x 13.5mm)

Integrated Device Technology, Inc.

6024 Silver Creek Valley Road

San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Discover what IDT know-how can do for you. Contact: www.IDT.com SSTE32882KB1 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE

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