DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 2
Technical content
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201135 07/25/2019 Rev#A11 ECN# 2N & SST 4117 4118 4119
FEATURES
LOW POWER IDSS<600 µA (2N4117A) MINIMUM CIRCUIT LOADING IGSS<1 pA (2N4117A Series) ABSOLUTE MAXIMUM RATINGS (NOTE 3) @ 25°C (unless otherwise noted) Gate-Source or Gate-Drain Voltage -40V Gate-Current 50mA Total Device Dissipation (Derate 2mW/ºC above 25ºC) 300mW Storage Temperature Range -55ºC to+150ºC Lead Temperature (1/16” from case for 10 seconds) 300ºC ELECTRICAL CHARACTERISTICS @ 25ºC (unless otherwise noted) SYMBOL CHARACTERISTIC 4117 4118 4119 UNITS CONDITIONS MIN MAX MIN MAX MIN MAX BVGSS Gate-Source Breakdown Voltage -40 -- -40 -- -40 -- V IG =-1µA VDS=0 VGS(off) Gate-Source Cutoff Voltage -0.6 -1.8 -1 -3 -2 -6 VDS =10V ID=1nA IDSS Saturation Drain Current IGSS Gate Reverse Current 2N4117A, 2N4118A, 2N4119A VGS =-20V VDS=0 PN4117, PN4118, PN4119 SST4117, SST4118, SST4119 VGS =-10V VDS=0 gfs Common-Source Forward Transconductance 70 450 80 650 100 700 µS VDS =10V VGS=0 f=1kHz gos Common-Source Output Conductance -- 3 -- 5 -- 10 Ciss Common-Source Input Capacitance (NOTE 4) -- 3 -- 3 -- 3 pF f=1MHz Crss Common-Source Reverse Transfer Capacitance (NOTE 4) -- 1.5 -- 1.5 -- 1.5 2N/PN/SST 4117, 4118, 4119 ULTRA-HIGH INPUT IMPEDANCE N-CHANNEL JFET AMPLIFIER 2N SERIES SST SERIES PN SERIES SOT-23 TOP VIEW D G S TO-72 TOP VIEW TO-92 TOP VIEW SOT-23 TOP VIEW 1 2 3 D S G
Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201135 07/25/2019 Rev#A11 ECN# 2N & SST 4117 4118 4119 DIMENSIONS IN MILLIMETERS 0.89 1.03 1.78 2.05 1.20 1.40 2.10 2.64 0.37 0.51 2.80 3.04 0.89 1.12 0.013 0.100 0.085 0.180 0.55 *Dimensions in inches 2N4117A, 2N4118A, 2N4119A TO-72 Four Lead PN4117, PN4118, PN4119 TO-92 SST4117, SST4118, SST4119 SOT-23 NOTES: 1. Due to symmetrical geometry, these units may be operated with source and drain leads interchanged. 2. This parameter is measured during a 2 ms interval 100 ms after power is applied. (Not a JEDEC condition.) 3. Absolute maximum ratings are limiting values above which serviceability may be impaired. 4. Not production tested, guaranteed by design. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Linear Integrated Systems. STANDARD PACKAGE DIMENSIONS: Linear Integrated Systems develops and produces the highest performance semiconductors of their kind in the industry. Linear Systems, founded in 1987, uses patented and proprietary processes and designs to create its high performance discrete semiconductors. Expertise brought to the company is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company founder John H. Hall.