SSNN6655HHVVDD3318

SN65HVD30_07 TI | Alldatasheet

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FOR: SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 3.3V FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS Each driver and receiver has separate input and output pins for full-duplex bus communication Unit-Load Option Available (Up to 256 designs. They are designed for balanced Nodes on the Bus) transmission lines and interoperation with ANSI Bus-Pin ESD Protection Exceeds kV HBM TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11 and ISO 8482:1993 standard-compliant devices. Optional Driver Output Transition Times for Signaling Rates (1) of Mbps, Mbps and The SN65HVD30, SN65HVD31, SN65HVD32, Mbps SN65HVD36 and SN65HVD37 are fully enabled with no external enabling pins. The SN65HVD36 and Low-Current Standby Mode: µ A SN65HVD37 implement receiver equalization Glitch-Free Power-Up and Power-Down technology for improved performance in long Protection for Hot-Plugging applications. 5-V Tolerant Inputs The SN65HVD33, SN65HVD34, SN65HVD35, Bus Idle, Open, and Short Circuit Failsafe SN65HVD38, and SN65HVD39 have active-high Driver Current Limiting and Thermal driver enables and active-low receiver enables. A Shutdown very low, less than µ standby current can be achieved by disabling both the driver and receiver. Meets or exceeds the requirements of ANSI The SN65HVD38 and SN65HVD39 implement TIA/EIA-485-A and RS-422 Compatible receiver equalization technology for improved 5-V Devices available, SN65HVD50-59 performance in long distance applications. (1) The signaling rate of a line is the number of voltage All devices are characterized for operation from transitions that are made per second expressed in the units C to bps (bits per second). The SN65HVD36 and SN65HVD38 implement receiver equalization technology for improved jitter Utility Meters performance on differential bus meters. Industrial, Process, and Building Automation The SN65HVD37 and SN65HVD39 implement Point-of-Sale (POS) Terminals and Networks receiver equalization technology for improved jitter performance on differential bus meters. drivers and differential-input line receivers that operate with 3.3-V power supply. Part Number Replace with xxx3491 SN65HVD33: Better ESD protection (15kV vs 2kV or not specified) Higher Signaling Rate (25Mbps vs 20Mbps) xxx3490 SN65HVD30: Fractional Unit Load (64 Nodes vs 32) MAX3491E SN65HVD33: Higher Signaling Rate (25Mbps vs 12Mbps) Fractional Unit Load (64 Nodes vs 32) MAX3490E SN65HVD30: MAX3076E SN65HVD33: Higher Signaling Rate (25Mbps vs 16Mbps) Lower Standby Current µ A vs µ MAX3077E SN65HVD30: MAX3073E SN65HVD34: Higher Signaling Rate (5Mbps vs 500kbps) Lower Standby Current µ A vs µ MAX3074E SN65HVD31: MAX3070E SN65HVD35: Higher Signaling Rate (1Mbps vs 250kbps) Lower Standby Current µ A vs µ MAX3071E SN65HVD32: Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. UNLESS OTHERWISE NOTED this document contains Copyright 2005 2006, Texas Instruments Incorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com R D B A Z Y D□P (TOP VIEW)ACKAGE R D V CC B A Z YGND NC R RE DE D GND GND V CC VCC A B Z Y NC NC□-□No□internal□connection SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36, SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38, SN65HVD37 SN65HVD39 AVAILABLE OPTIONS SIGNALING RECEIVER BASE UNIT LOADS ENABLES SOIC MARKING RATE EQUALIZATION PART NUMBER Mbps No No SN65HVD30 65HVD30 Mbps No No SN65HVD31 65HVD31 Mbps No No SN65HVD32 65HVD32 Mbps No Yes SN65HVD33 65HVD33 Mbps No Yes SN65HVD34 65HVD34 Mbps No Yes SN65HVD35 65HVD35 Mbps Yes No SN65HVD36 PREVIEW Mbps Yes No SN65HVD37 PREVIEW Mbps Yes Yes SN65HVD38 PREVIEW Mbps Yes Yes SN65HVD39 PREVIEW Submit Documentation Feedback

www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTROSTATIC DISCHARGE PROTECTION SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 over operating free-air temperature range unless otherwise noted (1) (2) UNIT V CC Supply voltage range 0.3 V to V V (A) V (B) V (Y) V (Z) Voltage range at any bus terminal (A, V to V V (TRANS) Voltage input, transient pulse through 100 Ω See Figure (A, (3) to V V I Input voltage range (D, DE, RE -0.5 V to V P D(cont) Continuous total power dissipation Internally limited (4) I O Output current (receiver output only, mA (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) This tests survivability only and the output state of the receiver is not specified. (4) The thermal shutdown protection circuit internally limits the continuous total power dissipation. Thermal shutdown typically occurs when the junction temperature reaches 165 over operating free-air temperature range unless otherwise noted MIN NOM MAX UNIT V CC Supply voltage 3.6 V V I or V IC Voltage at any bus terminal (separately or common mode) (1) SN65HVD30, SN65HVD33, SN65HVD36, SN65HVD38 1/t UI Signaling rate SN65HVD31, SN65HVD34, SN65HVD37, SN65HVD39 Mbps SN65HVD32, SN65HVD35 R L Differential load resistance Ω V IH High-level input voltage DE, RE V CC V IL Low-level input voltage DE, RE 0.8 V V ID Differential input voltage Driver I OH High-level output current mA Receiver Driver I OL Low-level output current mA Receiver T A Ambient still-air temperature C (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Human body model Bus terminals and GND Human body model (2) All pins kV Charged-device-model (3) All pins (1) All typical values at C with 3.3-V supply. (2) Tested in accordance with JEDEC Standard 22, Test Method A114-A. (3) Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback

www.ti.com DRIVER ELECTRICAL CHARACTERISTICS SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT V I(K) Input clamp voltage I I mA 1.5 V I O 2.5 V CC R L Ω See Figure (RS-485) 1.5 OD(SS) Steady-state differential output voltage V R L 100 Ω See Figure (2) (RS-422) 2.3 V test V to See Figure 1.5 Change in magnitude of steady-state Δ OD(SS) differential output voltage between R L Ω See Figure and Figure 0.2 0.2 V states Differential Output Voltage overshoot R L Ω C L pF, See Figure and V OD(RING) 10% (3) V and undershoot Figure HVD30, HVD33, 0.5 HVD36, HVD38 Peak-to-peak V OC(PP) common-mode See Figure V HVD31, HVD34, output voltage HVD37, HVD39, 0.25 HVD32, HVD35 Steady-state common-mode output V OC(SS) 1.6 2.3 voltage See Figure V Change in steady-state common-mode Δ V OC(SS) 0.05 0.05 output voltage V CC V Z or V Y HVD30, HVD31, Other input at V HVD32, HVD36, V CC V Z or V Y HVD37 Other input at V I Z(Z) or High-impedance µ A I Y(Z) state output current V CC V or DE V HVD33, HVD34, V Z or V Y V Other input HVD35, HVD38, at V V CC V or DE V HVD39 V Z or V Y V V Z or V Y V 250 250 I Z(S) or Other input Short Circuit output Current mA I Y(S) at V V Z or V Y V 250 250 I I Input current DE 100 µ A C (OD) Differential output capacitance V OD 0.4 sin (4E6 π 0.5 DE at V pF (1) All typical values are at C and with a 3.3-V supply. (2) V CC is 3.3 Vdc (3) 10% of the peak-to-peak differential output voltage swing, per TIA/EIA-485 Submit Documentation Feedback

www.ti.com DRIVER SWITCHING CHARACTERISTICS SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT HVD30, HVD33, HVD36, HVD38 Propagation delay time, t PLH HVD31, HVD34, HVD37, HVD39 ns low-to-high-level output HVD32, HVD35 120 175 305 HVD30, HVD33, HVD36, HVD38 Propagation delay time, t PHL HVD31, HVD34, HVD37, HVD39 ns high-to-low-level output HVD32, HVD35 120 175 305 HVD30, HVD33, HVD36, HVD38 2.5 Differential output signal rise R L Ω C L pF, t r HVD31, HVD34, HVD37, HVD39 ns time See Figure HVD32, HVD35 120 185 300 HVD30, HVD33, HVD36, HVD38 2.5 Differential output signal fall t f HVD31, HVD34, HVD37, HVD39 ns time HVD32, HVD35 120 180 300 HVD30, HVD33, HVD36, HVD38 0.6 t sk(p) Pulse skew (|t PHL t PLH HVD31, HVD34, HVD37, HVD39 2.0 ns HVD32, HVD35 5.1 HVD33, HVD38 Propagation delay time, t PZH1 high-impedance-to-high-level HVD34, HVD39 235 ns R L 110 Ω RE at output HVD35 490 D V and or D V and Z HVD33, HVD38 Propagation delay time, See Figure t PHZ high-level-to-high-impedance HVD34, HVD39 ns output HVD35 165 HVD33, HVD38 Propagation delay time, t PZL1 high-impedance-to-low-level HVD34, HVD39 190 ns R L 110 Ω RE at output HVD35 490 D V and or D V and Y HVD33, HVD38 Propagation delay time, See Figure t PLZ low-level-to-high-impedance HVD34, HVD39 120 ns output HVD35 290 R L 110 Ω RE at D V and or t PZH2 Propagation delay time, standby-to-high-level output 4000 ns D V and Z See Figure R L 110 Ω RE at D V and or t PZL2 Propagation delay time, standby-to-low-level output 4000 ns D V and Y See Figure (1) All typical values are at C and with a 3.3-V supply. Submit Documentation Feedback

www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Positive-going differential input threshold V IT+ I O mA 0.02 voltage V Negative-going differential input threshold V IT- I O mA 0.20 voltage V hys Hysteresis voltage IT+ V IT- mV V IK Enable-input clamp voltage I I mA 1.5 V V ID 200 mV, I O mA, See Figure 2.4 V O Output voltage V V ID 200 mV, I O mA, See Figure 0.4 I O(Z) High-impedance-state output current V O or V CC RE at V CC µ A V A or V B V 0.05 0.1 HVD31, HVD32, V A or V B V CC V 0.06 0.1 Other input HVD34, HVD35, mA at V A or V B V 0.10 0.04 HVD37, HVD39 V A or V B V CC V 0.10 0.03 I A or Bus input current I B V A or V B V 0.20 0.35 V A or V B V CC V 0.24 0.4 HVD30, HVD33, Other input mA HVD36, HVD38 at V A or V B V 0.35 0.18 V A or V B V CC V 0.25 0.13 I IH Input current, RE V IH 0.8 V or V µ A C ID Differential input capacitance V ID 0.4 sin (4E6 π 0.5 DE at V pF Supply Current HVD30 2.1 HVD31, HVD32 D at V or V CC and No Load 6.4 mA HVD36, HVD37 7.9 HVD33 1.8 RE at D at V or V CC DE at HVD34, HVD35 No load (Receiver enabled and driver 2.2 mA disabled) HVD38, HVD39 3.8 HVD33, HVD34, RE at V CC D at V CC DE at HVD35, HVD38, No load (Receiver disabled and driver 0.022 µ A HVD39 disabled) I CC Supply current HVD33 2.1 RE at D at V or V CC DE at V CC HVD34, HVD35 6.5 No load (Receiver enabled and driver HVD38 3.5 enabled) HVD39 mA HVD33 1.8 RE at V CC D at V or V CC DE at V CC HVD34, HVD35 6.2 No load (Receiver disabled and driver HVD38 2.5 enabled) HVD39 (1) All typical values are at C and with a 3.3-V supply. Submit Documentation Feedback

www.ti.com RECEIVER SWITCHING CHARACTERISTICS RECEIVER EQUALIZATION CHARACTERISTICS SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT HVD30, HVD33, HVD36, HVD38 Propagation delay time, t PLH HVD31, HVD32, HVD34, HVD35, low-to-high-level output HVD37, HVD39 HVD30, HVD33, HVD36, HVD38 Propagation delay time, t PHL HVD31, HVD32, HVD34, HVD35, high-to-low-level output V ID -1.5 V to 1.5 HVD37, HVD39 C L pF, See Figure HVD30, HVD33, HVD36, HVD37, HVD38, HVD39 t sk(p) Pulse skew (|t PHL t PLH HVD31, HVD34, HVD32, HVD35 ns t r Output signal rise time t f Output signal fall time t PHZ Output disable time from high level DE at V C L pF, t PZH1 Output enable time to high level See Figure t PZH2 Propagation delay time, standby-to-high-level output DE at V 4000 t PLZ Output disable time from low level DE at V C L pF, t PZL1 Output enable time to low level See Figure t PZL2 Propagation delay time, standby-to-low-level output DE at V 4000 (1) All typical values are at C and with a 3.3-V supply over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS DEVICE MIN TYP (1) MAX UNIT m HVD36, HVD38 PREVIEW HVD33 (2) PREVIEW 100 m HVD36, HVD38 PREVIEW Mbps HVD33 (2) PREVIEW 150 m HVD36, HVD38 PREVIEW HVD33 (2) PREVIEW 200 m HVD36, HVD38 PREVIEW HVD33 (2) PREVIEW 200 m HVD36, HVD38 PREVIEW HVD33 (2) PREVIEW Pseudo-random NRZ code Mbps 250 m Peak-to-peak t j(pp) with a bit pattern length of HVD36, HVD38 PREVIEW ns eye-pattern jitter Belden 3105A cable HVD33 (2) PREVIEW 300 m HVD36, HVD38 PREVIEW HVD34 (2) PREVIEW Mbps 500 m HVD37, HVD39 PREVIEW HVD33 (2) PREVIEW HVD34 (2) PREVIEW Mbps 500 m HVD36, HVD38 PREVIEW HVD37, HVD39 PREVIEW HVD34 (2) PREVIEW Mbps 1000 m HVD37, HVD39 PREVIEW (1) All typical values are at V CC and temperature (2) The HVD33 and the HVD34 do not have receiver equalization but are specified for comparison. Submit Documentation Feedback

www.ti.com DEVICE POWER DISSIPATION P D SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 TEST CONDITIONS DEVICE MIN TYP MAX UNIT HVD30, HVD36 (25 Mbps) 197 R L C L pF, Input to D a 50% duty cycle square wave at HVD31, HVD37 Mbps) 213 mW indicated signaling rate T A C HVD32 Mbps) 193 HVD33, HVD38 (25 Mbps) 197 R L C L pF, DE at VCC, RE at Input to D a 50% HVD34, HVD39 Mbps) 193 mW duty cycle square wave at indicated signaling rate T A C HVD35 Mbps) 248 Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION IY VOD RL0□or□3□V VYVZ IZ DE VCC II VI Y Z 60 Ω /c1771%VOD0□or□3□V DE VCC Y Z D 375 Ω /c1771% 375 Ω /c1771% VOD(RING) VOD(RING) -VOD(SS) VOD(SS) 0□V□Differential VOC 27 Ω /c1771% Input Y Z V Y VZ VOC(PP) ∆V OC(SS) VOC 27 Ω /c1771% CL =□50□pF /c17720% D Y Z DE VCC Input:□PRR□=□500□kHz,□50%□Duty□Cycle,t r<6ns,□tf<6ns,□ZO =□50 Ω CL Includes□Fixture□and Instrumentation□Capacitance SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 Figure Driver V OD Test Circuit and Voltage and Current Definitions Figure Driver V OD With Common-Mode Loading Test Circuit Figure V OD(RING) Waveform and Definitions V OD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from theV OD(H) and V OD(L) steady state values. Figure Test Circuit and Definitions for the Driver Common-Mode Output Voltage Submit Documentation Feedback

www.ti.com Y Z/c87 /c87 /c87 /c187 /c187 VI VO t PZH(1□&□2) 50 /c87 D 3□V Y Y Z VI RL =□110 /c87 ±1%CL =□50 pF ±20% VO Generator:□PRR□=□500kHz,□50%□Duty□Cycle,□tr<6□ns,□t f <□6ns,□Z 0 =□50 /c87 CL Includes□Fixture□and□Instrumentation□Capacitance 3□V 1.5□V1.5□V tPHZ 2.3□V DE Input Generator ~□0□V VOH 0.5□V 0□VS1 Input Generator 50 Ω VO VCC 3□V VCC 1.5□V 1.5□V tPZL(1&2) tPLZ 2.3□V 0.5□V 0□V V OL VI VO RL =□110 Ω /c1771% CL =□50□pF /c17720% CL Includes□Fixture and□Instrumentation Capacitance D Y ZDE VI 0□V Y VID VA VB IO A B IB VO R RE IA VICVA +□VB

2 II VI

(continued) Figure Driver Switching Test Circuit and Voltage Waveforms Figure Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms Figure Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms Figure Receiver Voltage and Current Definitions Submit Documentation Feedback

www.ti.com Input Generator 50 Ω VO 1.5□V 0□V 1.5□V 1.5□V 3□V V OH VOL 1.5□V 10% 1.5□V tPLH tPHL tr tf 90% VI VO CL =□15□pF /c17720% C Includes□Fixture□and□Instrumentation□CapacitanceL A B RE VI R 0□V 90% 10% B A R VO 50 /c87VI Input Generator CL =□15 pF ±20% CL Includes□Fixture□and Instrumentation□Capacitance Generator:□PRR□=□500kHz,□50%,□Duty□Cycle,□tr<6□ns,□t f <□6ns,□Z0 =□50 /c87 RE S11□k/c87 ±1% A B VCC V I tPZH(1□&□2) 3□V 1.5V1.5V tPHZ VO 1.5□V ~0□V VOH 0.5V 1.5□V 0□V B A R VO 50 /c87VI Input Generator CL =□15 pF ±20% CL Includes□Fixture and□Instrumentation Capacitance RE S11□k /c87 ±1% A B VCC VI VO 3□V 1.5V1.5V VCC VOL 0.5V 1.5□V tPZL(1□&□2) tPLZ 0□V 1.5□V B A R 100 /c87 ±1% Pulse□Generator 15 /c109s□duration 1%□Duty□Cycle t ,□t 100□nsr f /c163 Z Y D 100 /c87 ±1% DE 0□V□or□3□V 0□V□or□3□V RE SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION (continued) Figure Receiver Switching Test Circuit and Voltage Waveforms Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms Figure 11. Receiver Enable Time From Standby (Driver Disabled) Figure 12. Test Circuit, Transient Over Voltage Test Submit Documentation Feedback

www.ti.com DEVICE INFORMATION LOW-POWER STANDBY MODE Y Z D DE A B 1 1 R 3RE Low-Power Standby SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the enable inputs are in this state for less than ns, the device does not enter standby mode. This guards against inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the supply current is typically less than nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. Figure 13. Low-Power Standby Logic Diagram If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after the enable times given by t PZH2 and t PZL2 in the driver switching characteristics. If the D input is open when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature. If only the receiver is re-enabled RE transitions to low) the receiver output is driven according to the state of the bus inputs and after the enable times given by t PZH2 and t PZL2 in the receiver switching characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation section. If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus inputs and and the driver output is driven according to the D input. Note that the state of the active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid. Submit Documentation Feedback

www.ti.com FUNCTION TABLES SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 DEVICE INFORMATION (continued) SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38, SN65HVD39 DRIVER INPUTS OUTPUTS D DE Y Z H H H L L H L H X L or open Z Z Open H L H SN65HVD33, SN65HVD34, SN65HVD35, SN65HVD38, SN65HVD39 RECEIVER DIFFERENTIAL INPUTS ENABLE OUTPUT V ID V (A) V (B) RE R V ID 0.2 V L L 0.2 V V ID 0.02 V L 0.02 V V ID L H X H or open Z Open Circuit L H Idle circuit L H Short Circuit, V (A) V (B) L H SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36, SN65HVD37 DRIVER OUTPUTS INPUT Y Z D H H L L L H Open L H SN65HVD30, SN65HVD31, SN65HVD32, SN65HVD36, SN65HVD37 RECEIVER DIFFERENTIAL INPUTS OUTPUT V ID V (A) V (B) R V ID 0.2 V L 0.2 V V ID 0.02 V 0.02 V V ID H Open Circuit H Idle circuit H Short Circuit, V (A) V (B) H Submit Documentation Feedback

www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC Input 470 /c87 130 k/c87 VCC 5 /c87 Output R□Output 9 V 9 V 22 V 22 V Input VCC A Input 22 V 22 V Input VCC B□Input 16 V 16 V Y and□Z□Outputs Output VCC RE Input VCC Input 470 /c87 125 k/c87 9 V D□and□DE□Input SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 R1/R2 SN65HVD30, SN65HVD33, SN65HVD36, SN65HVD38 k Ω k Ω SN65HVD31, SN65HVD32, SN65HVD34, SN65HVD35 SN65HVD37, k Ω 180 k Ω SN65HVD38, SN65HVD39 Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS 0 5 10 15 20 25 Signaling□Rate□-□Mbps I -□RMS□Supply□Current□-□mACC =□V C =□50□pF DE□=□V A L CC L CC /c87 RE V =□3.3□VCC 0 1 2 3 4 5 Signaling□Rate□-□Mbps I -□RMS□Supply□Current□-□mACC =□V C =□50□pF DE□=□V A L CC L CC /c87 RE V =□3.3□VCC 0 0.2 0.4 0.6 0.8 1 Signaling□Rate□-□Mbps I -□RMS□Supply□Current□-□mACC =□V C =□50□pF DE□=□V A L CC L CC /c87 RE V =□3.3□VCC SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 HD30, HD33 RMS SUPPLY CURRENT HD31, HD34 RMS SUPPLY CURRENT vs vs SIGNALING RATE SIGNALING RATE Figure 14. Figure 15. HD32, HD35 RMS SUPPLY CURRENT vs SIGNALING RATE Figure 16. Submit Documentation Feedback

www.ti.com -60 -40 -20 -7 -4 -1 2 5 8 11 14 V -□Bus□Input□Voltage□-□VI I-□Bus□Input□Current□-□uAI T =□25°C =□0□V DE□=□0□V A RE V =□3.3□VCC -200 -150 -100 -50 100 150 200 250 -7 -4 -1 2 5 8 11 14 V -□Bus□Input□Voltage□-□VI I-□Bus□Input□Current□-□uAI T =□25°C =□0□V DE□=□0□V A RE V =□3.3□VCC -0.02 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0 0.5 1 1.5 2 2.5 3 3.5 V -□Low-Level□Output□Voltage□-□VOL I -□Low-level□Output□Current□- AOL V =□3.3□V DE□=□V D□=□0□V CC CC -0.13 -0.11 -0.09 -0.07 -0.05 -0.03 -0.01 0.01 0 0.5 1 1.5 2 2.5 3 3.5 V -□High-Level□Output□Voltage□-□VOH I -□High-level□Output□Current□- AOH V =□3.3□V DE□=□V D□=□0□V CC CC SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 TYPICAL CHARACTERISTICS (continued) HVD30, HVD33 HVD31, HVD32, HVD34, HVD35 BUS INPUT CURRENT BUS INPUT CURRENT vs vs INPUT VOLTAGE INPUT VOLTAGE Figure 17. Figure 18. DRIVER LOW-LEVEL OUTPUT CURRENT DRIVER HIGH-LEVEL OUTPUT CURRENT vs vs LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE Figure 19. Figure 20. Submit Documentation Feedback

www.ti.com 1.8 1.9 2.0 2.1 2.2 -40 -15 10 35 60 85 T -□Free Air□Temperature□-□°CA V -□Driver□Differential□V oltage□-□V OD V =□3.3□V DE□=□V D□= CC CC VCC 0 0.5 1 1.5 2 2.5 3 3.5 V Supply□Voltage□-□VCC I -□Driver□Output□Current□-□mA O T =□25°C R =□54 D□=□V DE□=□V A L CC CC /c87 HVD35 HVD34 100 600 700 800 -7 -2 3 8 13 HVD33 Enable□Time − ns V −(TEST) Common-Mode□Voltage − V 200 300 400 500 SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 TYPICAL CHARACTERISTICS (continued) DRIVER DIFFERENTIAL OUTPUT VOLTAGE DRIVER OUTPUT CURRENT vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE Figure 21. Figure 22. ENABLE TIME vs COMMON-MODE VOLTAGE (SEE Figure Figure 23. Submit Documentation Feedback

www.ti.com 60 /c87 1%/c177 50 /c87 375 /c87 1%/c177 VOD V (low)OD t (diff)pZL t (diff)pZH V 0□or□3□V 375 /c87 1%/c177 50% 0□V 1.5□V D Z DE Y -1.5□V V (high)OD Input Generator SN65HVD30 SN65HVD39 SLLS665C SEPTEMBER 2005 REVISED JULY 2006 TYPICAL CHARACTERISTICS (continued) Figure 24. Driver Enable Time From DE to V OD The time t pZL (x) is the measure from DE to V OD (x). V OD is valid when it is greater than 1.5 Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN65HVD30D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD30DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD30DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD30DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD31DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD32DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD33DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD34DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD35DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2007 Addendum-Page 1

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2007 Addendum-Page 2

TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN65HVD30DR D 8 SITE 41 330 12 6.9 5.4 2.0 8 12 Q1 SN65HVD31DR D 8 SITE 41 330 12 6.9 5.4 2.0 8 12 Q1 SN65HVD32DR D 8 SITE 41 330 12 6.9 5.4 2.0 8 12 Q1 SN65HVD34DR D 14 SITE 60 330 16 6.5 9.0 2.1 8 16 Q1 SN65HVD35DR D 14 SITE 60 330 16 6.5 9.0 2.1 8 16 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2007 Pack Materials-Page 1

Device Package Pins Site Length (mm) Width (mm) Height (mm) SN65HVD30DR D 8 SITE 41 342.9 336.6 0.0 SN65HVD31DR D 8 SITE 41 346.0 346.0 0.0 SN65HVD32DR D 8 SITE 41 346.0 346.0 0.0 SN65HVD34DR D 14 SITE 60 346.0 346.0 0.0 SN65HVD35DR D 14 SITE 60 346.0 346.0 0.0 PACKAGE MATERIALS INFORMATION www.ti.com 22-Sep-2007 Pack Materials-Page 2

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