SSM9962M SSC | Alldatasheet
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www.SiliconStandard.com 1 of 5 DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Simple drive requirement BV DSS 40V Lower gate charge R DS(ON) 25mΩ Fast switching characteristics ID 7A
Description
ID @ TA=25°C ID @ TA=100°C IDM A PD @ TA=25°C W/°C TSTG TJ Symbol Value Unit Rthj-a Thermal Resistance Junction-ambient3 Max. 62.5 °C/W Rating 7 A Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current3 5.5 A Pulsed Drain Current1 20 2 W -55 to 150 °C Operating Junction Temperature Range -55 to 150 °C Linear Derating Factor 0.016 Storage Temperature Range Thermal Data Parameter Total Power Dissipation ± 20 Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SSM9962M is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. SO-8 SSM9962 M/GM 8/21/2004 Rev.2.01 This device is available with Pb-free lead finish (second-level interconnect) as SSM9962GM.
www.SiliconStandard.com 2 of 5 SSM9962 M/GM 8/21/2004 Rev.2.01 Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage V GS=0V, ID=250uA 40 - - V Δ BVDSS/Δ Tj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA - 0.1 - V/°C RDS(ON) Static Drain-Source On-Resistance2 VGS=10V, ID=7A - - 25 mΩ VGS=4.5V, ID=5A - - 40 mΩ VGS(th) Gate Threshold Voltage VDS=VGS, ID=250uA 1 - 3 V gfs Forward Transconductance VDS=10V, ID=7A - 11 - S IDSS Drain-Source Leakage Current (Tj=25oC) VDS=40V, VGS=0V - - 1 uA Drain-Source Leakage Current (Tj=70oC) VDS=32V ,VGS=0V - - 25 uA IGSS Gate-Source Leakage VGS= ± 20V - - ±100 nA Qg Total Gate Charge2 ID=7A - 25.8 - nC Qgs Gate-Source Charge VDS=32V - 4.4 - nC Qgd Gate-Drain ("Miller") Charge VGS=4.5V - 9.1 - nC td(on) Turn-on Delay Time2 VDS=20V - 10.6 - ns tr Rise Time ID=1A - 6.8 - ns td(off) Turn-off Delay Time RG=5.7Ω ,VGS=10V - 26.3 - ns tf Fall Time RD=20Ω - 12 - ns Ciss Input Capacitance VGS=0V - 1165 - pF Coss Output Capacitance VDS=25V - 205 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 142 - pF Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 i n2 copper pad of FR4 board ; 135°C/W when mounted on min. copper pad. Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Units VSD Forward On Voltage2 IS=1.7A, VGS=0V - - 1.2 V trr Reverse Recovery Time Is=1.7A, VGS=0V, - 21.2 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 16 - nC
www.SiliconStandard.com 3 of 5 SSM9962 M/GM 8/21/2004 Rev.2.01 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 34567891 01 1 V GS (V) RDS(ON) (mΩ ) I D =7A T C =25 o C 012345 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T C =150 o C 8.0V V G =3.0V 5.0V 10V 4.0V 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) I D =7A VG=10V 0123456 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T C =25 o C 10V 8.0V 5.0V 4.0V V G =3.0V Fig 5. Forward Characteristic of Fig 6. Gate Threshold Voltage vs. Reverse Diode Junction Temperature 1.2 1.4 1.6 1.8 2.2 2.4 2.6 2.8 -50 0 50 100 150 Junction Temperature ( o C ) VGS (th) 0.01 0.1 100 0 0.4 0.8 1.2 1.6 V SD (V) IS(A) T j =25 o CT j =150 o C
www.SiliconStandard.com 4 of 5 SSM9962 M/GM 8/21/2004 Rev.2.01 Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1000 10000 1 5 9 13 17 21 25 29 VDS (V) C (pF) f=1.0MHz Ciss Crss Coss 0 5 10 15 20 25 30 35 Q G , Total Gate Charge (nC) VGS , Gate to Source Voltage (V) V DS =20V V DS =25V V DS =32V I D =7A Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance 0.01 0.1 100 0.1 1 10 100 V DS (V) ID (A) T c =25 o C Single Pulse 1ms 10ms 100ms DC 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Normalized Thermal Response (Rthja) 0.01 0.05 0.1 0.2 DUTY=0.5 Single Pulse PDM Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 135°C/W t T 0.02
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. www.SiliconStandard.com 5 of 5 SSM9962 M/GM 8/21/2004 Rev.2.01 Fig 11. Switching Time Circuit Fig 12. Switching Time Waveform Fig 13 . Gate Charge Circuit Fig 14. Gate Charge Waveform td(on) tr td(off) tf VDS VGS 10% 90% Q VG 4.5V QGS QGD QG Charge 0.5 x RATED VDS TO THE OSCILLOSCOPE D G S VDS VGS I D I G 1~ 3 mA 0.5 x RATED VDS TO THE OSCILLOSCOPE 10 v D G S VDS VGS RG RD