SSM9934GM

SSM9934GM SSC | Alldatasheet

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2N AND 2P-CHANNEL ENHANCEMENT MODE POWER MOSFET 09/13/2007 Rev.1.00 www.SiliconStandard.com 1 SSM9934GM PRODUCT SUMMARY Simple Drive Requirement Low On-resistance Full Bridge Application on LCD Monitor Inverter

DESCRIPTION

The advanced power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SO-8 package is universally preferred for all commercial- industrial surface mount applications and suited for low voltage applications such as DC/DC converters. ABSOLUTE MAXIMUM RATINGS N-CH BVDSS 35V RDS(ON) 48mΩ ID 4.3A P-CH BVDSS -35V RDS(ON) 72mΩ ID -3.6A N1G N1D/P1D N1S/N2S N2G P1G P1S/P2S N2D/P2D P2G SO-8 N1G N1S P1G P1S P1N1D N2G N2S P2G P2S P2N2D Symbol Parameter Rating Units N-channel P-channel VDS Drain-Source Voltage 35 -35 V VGS Gate-Source Voltage ± 20 ± 20 V ID@TA=25℃ Continuous Drain Current3 4.3 -3.6 A ID@TA=70℃ Continuous Drain Current3 3.4 -2.8 A IDM Pulsed Drain Current1 20 -20 A PD@TA=25℃ Total Power Dissipation 1.38 W Linear Derating Factor 0.01 W/℃ TSTG Storage Temperature Range -55 to 150 ℃ TJ Operating Junction Temperature Range -55 to 150 ℃ Symbol Value Unit Rthj-a Thermal Resistance Junction-ambient3 Max. 90 ℃/W Parameter THERMAL DATA Pb-free; RoHS-compliant

09/13/2007 Rev.1.00 www.SiliconStandard.com 2 SSM9934GM N-CH ELECTRICAL CHARACTERISTICS @Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=250uA 35 - - V ΔBVDSS/ΔTj Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=1mA - 0.03 - V/℃ RDS(ON) Static Drain-Source On-Resistance2 VGS=10V, ID=4A - - 48 mΩ VGS=4.5V, ID=3A - - 70 mΩ VGS(th) Gate Threshold Voltage VDS=VGS, ID=250uA 1 - 3 V gfs Forward Transconductance VDS=10V, ID=4A - 8 - S IDSS Drain-Source Leakage Current (Tj=25oC) VDS=30V, VGS=0V - - 1 uA Drain-Source Leakage Current (Tj=70oC) VDS=24V, VGS=0V - - 25 uA IGSS Gate-Source Leakage VGS=±20V - - ±100 nA Qg Total Gate Charge2 ID=4A - 6 10 nC Qgs Gate-Source Charge VDS=28V - 2 - nC Qgd Gate-Drain ("Miller") Charge VGS=4.5V - 3 - nC td(on) Turn-on Delay Time2 VDS=15V - 6 - ns tr Rise Time ID=1A - 5 - ns td(off) Turn-off Delay Time RG=3.3Ω,VGS=10V - 14 - ns tf Fall Time RD=15Ω -4 - ns Ciss Input Capacitance VGS=0V - 490 780 pF Coss Output Capacitance VDS=25V - 130 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 55 - pF SOURCE-DRAIN DIODE Symbol Parameter Test Conditions Min. Typ. Max. Units VSD Forward On Voltage2 IS=1.2A, VGS=0V - - 1.2 V trr Reverse Recovery Time IS=4A, VGS=0V - 18 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 11 - nC

09/13/2007 Rev.1.00 www.SiliconStandard.com 3 SSM9934GM P-CH ELECTRICAL CHARACTERISTICS @Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=-250uA -35 - - V ΔBVDSS/ΔTj Breakdown Voltage Temperature Coefficient Reference to 25℃,ID=-1mA - -0.02 - V/℃ RDS(ON) Static Drain-Source On-Resistance2 VGS=-10V, ID=-3A - - 72 mΩ VGS=-4.5V, ID=-2A - - 100 mΩ VGS(th) Gate Threshold Voltage VDS=VGS, ID=-250uA -1 - -3 V gfs Forward Transconductance VDS=-10V, ID=-3A - 6 - S IDSS Drain-Source Leakage Current (Tj=25oC) VDS=-30V, VGS=0V - - -1 uA Drain-Source Leakage Current (Tj=70oC) VDS=-24V, VGS=0V - - -25 uA IGSS Gate-Source Leakage VGS=±20V - - ±100 nA Qg Total Gate Charge2 ID=-3A - 6 10 nC Qgs Gate-Source Charge VDS=-28V - 1 - nC Qgd Gate-Drain ("Miller") Charge VGS=-4.5V - 3 - nC td(on) Turn-on Delay Time2 VDS=-15V - 7 - ns tr Rise Time ID=-1A - 5 - ns td(off) Turn-off Delay Time RG=3.3Ω,VGS=-10V - 19 - ns tf Fall Time RD=15Ω -4 - ns Ciss Input Capacitance VGS=0V - 420 1100 pF Coss Output Capacitance VDS=-25V - 140 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 65 - pF SOURCE-DRAIN DIODE Symbol Parameter Test Conditions Min. Typ. Max. Units VSD Forward On Voltage2 IS=-1.2A, VGS=0V - - -1.2 V trr Reverse Recovery Time IS=-3A, VGS=0V - 20 - ns Qrr Reverse Recovery Charge dI/dt=-100A/µs - 16 - nC Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board , t <10sec ; 186 ℃/W when mounted on Min. copper pad.

09/13/2007 Rev.1.00 www.SiliconStandard.com 4 SSM9934GM N-Channel Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature Fig 5. Forward Characteristic of Fig 6. Gate Threshold Voltage v.s. Reverse Diode Junction Temperature 0123 456 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T A =25 o C V G =2.5V 10V 7.0V 5.0V 4.5V 01 234 56 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T A = 150 o C 10V 7.0V 5.0V 4.5V V G =2.5V 24 68 10 V GS , Gate-to-Source Voltage (V) RDS(ON) (m ΩΩΩΩ) I D =3A T A =25 o C 0.6 0.8 1.0 1.2 1.4 1.6 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) I D =4A V G =10V 0.5 1.5 -50 0 50 100 150 T j ,Junction Temperature ( o C) Normalized VGS(th) (V) V SD , Source-to-Drain Voltage (V) IS(A) T j =25 o CT j =150 o C

09/13/2007 Rev.1.00 www.SiliconStandard.com 5 SSM9934GM N-Channel Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform td(on) tr td(off) tf VDS VGS 10% 90% 036 9 12 Q G , Total Gate Charge (nC) VGS , Gate to Source Voltage (V) I D =4 A V DS = 28V 100 1000 1 5 9 131 7 212 5 29 V DS , Drain-to-Source Voltage (V) C (pF) f=1.0MHz C iss C oss C rss Q VG 4.5V QGS QGD QG Charge 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Normalized Thermal Response (Rthja) 0.01 0.05 0.1 0.2 Duty factor=0.5 Single Pulse PDM Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 186℃℃℃℃/W t T 0.02 0.01 0.1 100 0.1 1 10 100 V DS , Drain-to-Source Voltage (V) ID (A) 100us 1ms 10ms 100ms DC T A =25 o C Single Pulse

09/13/2007 Rev.1.00 www.SiliconStandard.com 6 SSM9934GM P-Channel Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature Fig 5. Forward Characteristic of Fig 6. Gate Threshold Voltage v.s. Reverse Diode Junction Temperature 012345 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) -10V -7.0V -5.0V -4.5V V G = - 2.5V T A =25 o C 012 345 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T A = 150 o C V G = - 2.5V -10V -7.0V -5.0V -4.5V 100 2468 10 -V GS , Gate-to-Source Voltage (V) RDS(ON) (m ΩΩΩΩ) I D =- 2A T A =25 o C 0.6 0.8 1.0 1.2 1.4 1.6 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) I D =- 3A V G = - 10V 0.5 1.5 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized -VGS(th) (V) -V SD , Source-to-Drain Voltage (V) -IS(A) T j =25 o CT j =150 o C

09/13/2007 Rev.1.00 www.SiliconStandard.com 7 SSM9934GM P-Channel Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform td(on) tr td(off) tf VDS VGS 10% 90% Q VG -4.5V QGS QGD QG Charge 0369 12 Q G , Total Gate Charge (nC) -VGS , Gate to Source Voltage (V) I D =- 3 A V DS = - 28V 100 1000 1 5 9 131 72 1 252 9 -V DS , Drain-to-Source Voltage (V) C (pF) f=1.0MHz C iss C oss C rss 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Normalized Thermal Response (Rthja) 0.01 0.05 0.1 0.2 Duty factor=0.5 Single Pulse PDM Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 186℃℃℃℃/W t T 0.02 0.01 0.1 100 0.1 1 10 100 -V DS , Drain-to-Source Voltage (V) -ID (A) 100us 1ms 10ms 100ms DC T A =25 o C Single Pulse

09/13/2007 Rev.1.00 www.SiliconStandard.com 4 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.