SSM9926O SSC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 6
Technical content
03/11/2007 Rev.1.00 www.SiliconStandard.com 1 N-CHANNEL ENHANCEMENT MODE POWER MOSFET PRODUCT SUMMARY Low on-resistance Capable of 2.5V gate drive Low drive current Surface mount package
DESCRIPTION
The Advanced Power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, ultra low on-resistance and cost-effectiveness. D2 S2 TSSOP-8 ABSOLUTE MAXIMUM RATINGS THERMAL DATA BVDSS 20V RDS(ON) 28mΩ ID 4.6A Symbol Units VDS V VGS V ID@TA=25℃ A ID@TA=70℃ A IDM A PD@TA=25℃ W W/℃ TSTG ℃ TJ ℃ Symbol Value Unit Rthj-a Thermal Resistance Junction-ambient3 Max. 125 ℃/W D A Parameter Rating Drain-Source Voltage 20 Gate-Source Voltage Continuous Drain Current3 4.6 Continuous Drain Current3 3.7 Pulsed Drain Current1 20 Total Power Dissipation 1 -55 to 150 Operating Junction Temperature Range -55 to 150 Linear Derating Factor 0.008 T Parameter Storage Temperature Range Pb-free; RoHS-compliant
03/11/2007 Rev.1.00 www.SiliconStandard.com 2 ELECTRICAL CHARACTERISTICS@Tj=25oC(unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage V GS=0V, ID=250uA 20 - - V ΔBVDSS/ΔTj Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=1mA - 0.1 - V/ ℃ RDS(ON) Static Drain-Source On-Resistance2 VGS=4.5V, ID=4A - 23 28 mΩ VGS=2.5V, ID=2A - - 40 mΩ VGS(th) Gate Threshold Voltage VDS=VGS, ID=250uA 0.5 - - V gfs Forward Transconductance VDS=10V, ID=4.6A - 9.7 - S IDSS Drain-Source Leakage Current (Tj=25oC) VDS=20V, VGS=0V - - 1 uA Drain-Source Leakage Current (Tj=70oC) VDS=20V ,VGS=0V - - 25 uA IGSS Gate-Source Leakage VGS=- - nA Qg Total Gate Charge2 ID=4.6A - 12.5 - nC Qgs Gate-Source Charge VDS=20V - 1 - nC Qgd Gate-Drain ("Miller") Charge V GS=5V - 6.5 - nC td(on) Turn-on Delay Time2 VDS=10V - 7 - ns tr Rise Time ID=1A - 14.5 - ns td(off) Turn-off Delay Time RG=3.3Ω,VGS=5V - 19 - ns tf Fall Time RD=10Ω -1 2- ns Ciss Input Capacitance VGS=0V - 355 - pF Coss Output Capacitance VDS=20V - 190 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 85 - pF SOURCE-DRAIN DIODE Symbol Parameter Test Conditions Min. Typ. Max. Units IS Continuous Source Current ( Body Diode ) VD=VG=0V,VS=1.2V - - 0.83 A VSD Forward On Voltage2 Tj=25℃,IS=1.25A,VGS=0V - - 1.2 V Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 208℃/W when mounted on Min. copper pad. A ± 8V ±100
03/11/2007 Rev.1.00 www.SiliconStandard.com 3 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 12 34 56 V GS (V) RDS(ON) (m ΩΩΩΩ) T C =25 o C I D = 4A 0 0.5 1 1.5 2 2.5 3 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T C =25 o C 4.5V 4.0V 3.5V 3.0V 2.5V V GS =2.0V 0 0.5 1 1.5 2 2.5 3 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T C =150 o C 4.5V 4.0V 3.5V 3.0V 2.5V V GS =2.0V 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) V GS =4.5V I D = 4A
03/11/2007 Rev.1.00 www.SiliconStandard.com 4 Fig 5. Maximum Drain Current v.s. Fig 6. Typical Power Dissipation Case Temperature Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance A 0.01 0.1 100 0.1 1 10 100 V DS (V) ID (A) T C =25 o C Single Pulse 100us 1ms 10ms 100ms DC 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 t , Pulse Width (s) Normalized Thermal Response (Rthja) PDM Duty Factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=208oC/W t T 0.02 0.05 0.1 0.2 Duty Factor = 0.5 Single Pulse 0.01 0.2 0.4 0.6 0.8 1.2 0 50 100 150 T c , Case Temperature ( o C) PD (W) 25 50 75 100 125 150 T c , Case Temperature ( o C) ID , Drain Current (A)
03/11/2007 Rev.1.00 www.SiliconStandard.com 5 Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics Fig 11. Forward Characteristic of Fig 12. Gate Threshold Voltage v.s. Reverse Diode Junction Temperature 0 5 10 15 20 25 Q G , Total Gate Charge (nC) VGS , Gate to Source Voltage (V) V DS =10V V DS =15V V DS =20V I D =4.6A 100 1000 1 5 9 131 7 212 5 29 V DS (V) C (pF) f=1.0MHz Ciss Coss Crss 0.01 0.1 100 0 0.4 0.8 1.2 1.6 V SD (V) IS (A) T j =25 o C T j =150 o C 0.2 0.4 0.6 0.8 1.2 1.4 1.6 -50 0 50 100 150 Junction Temperature ( o C ) VGS(th) (V)
03/11/2007 Rev.1.00 www.SiliconStandard.com 6 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform td(on) tr td(off) tf VDS VGS 10% 90% Q VG QGS QGD QG Charge 0.5x RATED VDS TO THE OSCILLOSCOPE 5 v D G S VDS VGS RG RD RATED VDS TO THE OSCILLOSCOPE D G S VDS VGS IDIG 1~ 3 mA