SSM9567GM

SSM9567GM SSC | Alldatasheet

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www.SiliconStandard.com 1 of 5 P-channel Enhancement-mode Power MOSFET BVDSS -40V RDS(ON) 50mΩ ID -6A The SSM9567GM acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC Pb-free; RoHS-compliant SO-8 PRODUCT SUMMARY DESCRIPTION Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 3.Mounted on a square inch of copper pad on FR4 board; 125°C/W when mounted on the minimum pad area required for soldering. converters and general load-switching circuits. The SSM9567GM is supplied in an RoHS-compliant SO-8 package, which is widely used for medium power commercial and industrial surface mount applications. S S S G D D D D SO-8 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Units VDS VGS V ID IDM A PD W/°C TSTG TJ Symbol Parameter Value Units RΘJA Maximum thermal resistance, junction-ambient 3 50 °C/W Drain-source voltage -40 V Gate-source voltage ±25 Continuous drain current, TC = 25°C -6 A TC = 70°C -4.8 A Pulsed drain current1 -30 Total power dissipation, TC = 25°C 2.5 W -55 to 150 °C Operating junction temperature range -55 to 150 °C Linear derating factor 0.02 THERMAL CHARACTERISTICS Storage temperature range SSM9567GM 9/27/2006 Rev.3.01

www.SiliconStandard.com 2 of 5 ELECTRICAL CHARACTERISTICS (at Tj = 25°C, unless otherwise specified) Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-source breakdown voltage V GS=0V, ID=-250uA -40 - - V Δ BVDSS/ ΔTj Breakdown voltage temperature coefficient Reference to 25°C, ID=-1mA - -0.03 - V/°C RDS(ON) Static drain-source on-resistance2 V GS=-10V, ID=-6A - - 50 mΩ VGS=-4.5V, ID=-4A - - 80 mΩ VGS(th) Gate threshold voltage VDS=VGS, ID=-250uA -1 - -3 V gfs Forward transconductance V DS=-10V, ID=-6A - 9 - S IDSS Drain-source leakage current VDS=-40V, VGS=0V, Tj = 25°C - - -1 uA VDS=-32V ,VGS=0V, Tj = 70°C - - -25 uA IGSS Gate-source leakage current VGS=±25V - - ±100 nA Qg Total gate charge 2 ID=-6A - 11 18 nC Qgs Gate-source charge VDS=-32V - 3 - nC Qgd Gate-drain ("Miller") charge V GS=-4.5V - 5 - nC td(on) Turn-on delay time 2 VDS=-20V - 10 - ns tr Rise time ID=-1A - 5 - ns td(off) Turn-off delay time R G=3.3Ω , VGS=-10V - 30 - ns tf Fall time R D=20Ω - 6 - ns Ciss Input capacitance VGS=0V - 880 1400 pF Coss Output capacitance VDS=-25V - 135 - pF Crss Reverse transfer capacitance f=1.0MHz - 110 - pF Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Units VSD Forward voltage2 IIS=-2A, VGS=0V - - -1.2 V trr Reverse-recovery time2 IS=-6A, VGS=0V, - 24 - ns Qrr Reverse-recovery charge dI/dt=100A/µs - 21 - nC SSM9567GM 9/27/2006 Rev.3.01 Rg Gate resistance f=1.0MHz - 5 8 Ω

www.SiliconStandard.com 3 of 5 SSM9567GM 9/27/2006 Rev.3.01 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature Fig 5. Forward Characteristic of Fig 6. Gate Threshold Voltage vs. Reverse Diode Junction Temperature 02468 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T A =2 5o C -10V -7.0V - 5.0V -4.5V V G = -3.0 V 02468 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T A =150°C -10V -7.0V - 5.0V -4.5V V G = -3.0 V 2468 1 0 -V GS , Gate-to-Source Voltage (V) RDS(ON) (mΩ ) I D =-4A T A =25°C 0.4 0.8 1.2 1.6 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) I D =-6A V G =-10V -V SD , Source-to-Drain Voltage (V) -IS(A) T j =25 o CT j =150 o C 0.2 0.7 1.2 1.7 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized -VGS(th) (V)

www.SiliconStandard.com 4 of 5 SSM9567GM 9/27/2006 Rev.3.01 Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance Fig 11. Transfer Characteristics Fig 12. Gate Charge Waveform Q VG -4.5V QGS QGD QG Charge 100 1000 10000 1 5 9 13 17 21 25 29 -V DS , Drain-to-Source Voltage (V) C (pF) f=1.0MHz C iss C oss C rss 0 5 10 15 20 25 Q G , Total Gate Charge (nC) -VGS , Gate to Source Voltage (V) I D = -6A V DS = -32V 0.01 0.1 100 0.1 1 10 100 -V DS , Drain-to-Source Voltage (V) -ID (A) T A =25 o C Single Pulse 1ms 10ms 100ms DC 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Normalized Thermal Response (Rthja) PDM Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=125oC/W t T 0.02 0.01 0.05 0.1 0.2 Duty factor=0.5 Single Pulse 02468 -V GS , Gate-to-Source Voltage (V) -ID , Drain Current (A) T j =150 o CT j =25 o C V DS =-5V

www.SiliconStandard.com 5 of 5 PHYSICAL DIMENSIONS PART MARKING PACKING: Moisture sensitivity level MSL3 3000 pcs in antistatic tape on a 13 inch (330mm) reel packed in a moisture barrier bag (MBB). SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27(TYP) H 5.80 6.50 L 0.38 1.27 D H e A B C E L Dimensions do not include mold protrusions. PART NUMBER: 9567GM = SSM9567GM 9567GM YWWSSS DATE/LOT CODE: (YWWSSS) Y = last digit of the year WW = week SSS = lot code sequence All dimensions in millimeters. SSM9567GM 9/27/2006 Rev.3.01 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expre ssed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.