SSM9563GM

SSM9563GM SSC | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 5

Technical content

www.SiliconStandard.com 1 of 5 P-channel Enhancement-mode Power MOSFET BVDSS -40V RDS(ON) 40mΩ ID -6A The SSM9563GM acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC Pb-free; RoHS-compliant SO-8 PRODUCT SUMMARY DESCRIPTION Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 3.Mounted on a square inch of copper pad on FR4 board; 125°C/W when mounted on the minimum pad area required for soldering. converters and general load-switching circuits. The SSM9563GM is supplied in an RoHS-compliant SO-8 package, which is widely used for medium power commercial and industrial surface mount applications. S S S G D D D D SO-8 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Units VDS VGS V ID IDM A PD W/°C TSTG TJ Symbol Parameter Value Units RΘJA Maximum thermal resistance, junction-ambient 3 50 °C/W Drain-source voltage -40 V Gate-source voltage ±2 5 Continuous drain current , T C = 25°C -6 A T C = 70°C -4.8 A Pulsed drain current1 -30 Total power dissipation, TC = 25°C 2.5 W -55 to 150 °C Operating junction temperature range -55 to 150 °C Linear derating factor 0.02 THERMAL CHARACTERISTICS Storage temperature range SSM9563GM 9/26/2006 Rev.3.01

www.SiliconStandard.com 2 of 5 ELECTRICAL CHARACTERISTICS (at Tj = 25°C, unless otherwise specified) Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-source breakdown voltage V GS=0V, ID=-250uA -40 - - V Δ BVDSS/ ΔTj Breakdown voltage temperature coefficient Reference to 25°C, ID=-1mA - -0.03 - V/°C RDS(ON) Static drain-source on-resistance2 V GS=-10V, ID=-6A - - 40 mΩ VGS=-4.5V, ID=-4A - - 60 mΩ VGS(th) Gate threshold voltage VDS=VGS, ID=-250uA -1 - -3 V gfs Forward transconductance V DS=-10V, ID=-6A - 10 - S IDSS Drain-source leakage current VDS=-40V, VGS=0V, Tj = 25C - - -1 uA VDS=-32V ,VGS=0V, Tj = 70°C - - -25 uA IGSS Gate-source leakage current VGS=±25V - - ±100 nA Qg Total gate charge 2 ID=-6A - 19 30 nC Qgs Gate-source charge VDS=-32V - 5 - nC Qgd Gate-drain ("Miller") charge V GS=-4.5V - 8 - nC td(on) Turn-on delay time 2 VDS=-20V - 12 - ns tr Rise time ID=-1A - 7 - ns td(off) Turn-off delay time R G=3.3Ω , VGS=-10V - 68 - ns tf Fall time R D=20Ω - 38 - ns Ciss Input capacitance VGS=0V - 1600 2560 pF Coss Output capacitance VDS=-25V - 240 - pF Crss Reverse transfer capacitance f=1.0MHz - 190 - pF Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Units VSD Forward voltage 2 IS=-2A, VGS=0V - - -1.2 V trr Reverse-recovery time2 IS=-6A, VGS=0V, - 37 - ns Qrr Reverse-recovery charge dI/dt=100A/µs - 54 - nC SSM9563GM 9/26/2006 Rev.3.01

www.SiliconStandard.com 3 of 5 SSM9563GM 9/26/2006 Rev.3.01 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature Fig 5. Forward Characteristic of Fig 6. Gate Threshold Voltage vs. Reverse Diode Junction Temperature 100 02468 1 0 1 2 1 4 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T A =2 5o C -10V -7.0V -5.0V -4.5V V G = -3.0 V 0 2 4 6 8 10 12 14 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T A =150 o C -10V -7.0V -5.0V -4.5V V G = -3.0 V 3579 1 1 -V GS , Gate-to-Source Voltage (V) RDS(ON) (mΩ ) I D =-4A T A =25°C 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) I D =-6A V G =-10V -50 0 50 100 150 T j , Junction Temperature ( o C) -VGS(th) (V) -V SD , Source-to-Drain Voltage (V) -IS(A) T j =25 o CT j =150 o C

www.SiliconStandard.com 4 of 5 SSM9563GM 9/26/2006 Rev.3.01 Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform td(on) tr td(off)tf VDS VGS 10% 90% Q VG -4.5V QGS QGD QG Charge 100 1000 10000 1 5 9 13 17 21 25 29 -V DS , Drain-to-Source Voltage (V) C (pF) f=1.0MHz C iss C oss C rss 0 1 02 03 04 05 06 07 0 Q G , Total Gate Charge (nC) -VGS , Gate to Source Voltage (V) I D = -6A V DS = -32V 0.01 0.1 100 0.1 1 10 100 -V DS , Drain-to-Source Voltage (V) -ID (A) T A =25 o C Single Pulse 1ms 10ms 100ms DC 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Normalized Thermal Response (Rthja) PDM Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=125oC/W t T 0.02 0.01 0.05 0.1 0.2 Duty factor=0.5 Single Pulse

www.SiliconStandard.com 5 of 5 PHYSICAL DIMENSIONS PART MARKING PACKING: Moisture sensitivity level MSL3 3000 pcs in antistatic tape on a 13 inch (330mm) reel packed in a moisture barrier bag (MBB). SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27(TYP) H 5.80 6.50 L 0.38 1.27 D H e A B C E L Dimensions do not include mold protrusions. PART NUMBER: 9563GM = SSM9563GM 9563GM YWWSSS DATE/LOT CODE: (YWWSSS) Y = last digit of the year WW = week SSS = lot code sequence All dimensions in millimeters. SSM9563GM 9/26/2006 Rev.3.01 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.