SSM9435K

SSM9435K SSC | Alldatasheet

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Technical content

www.SiliconStandard.com 1 of 4 SSM9435K Rev.1.01 5/25/2004 P-CHANNEL ENHANCEMENT-MODE POWER MOSFET Simple drive requirement BV DSS -30V Low on-resistance R DS(ON) 50mΩ Fast switching ID -6A

Description

ID @ TA=25°C ID @ TA=70°C IDM A PD @ TA=25°C W/°C TSTG TJ Symbol Value Unit Rthj-amb Thermal Resistance Junction-ambient3 Max. 45 °C/W Thermal Data Parameter Total Power Dissipation 2.7 W -55 to 150 °C Operating Junction Temperature Range -55 to 150 °C Linear Derating Factor 0.02 Storage Temperature Range Continuous Drain Current3 -4.8 A Pulsed Drain Current1 -20 Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Rating -30 -6 A ± 25 Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, low on-resistance and cost-effectiveness. G D S D D S GSOT-223

www.SiliconStandard.com 2 of 4 SSM9435K Rev.1.01 5/25/2004 Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=-250uA -30 - - V Δ BVDSS/ Δ Tj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=-1mA - -0.02 - V/°C RDS(ON) Static Drain-Source On-Resistance2 VGS=-10V, ID=-5.3A - - 50 mΩ VGS=-4.5V, ID=-4.2A - - 100 mΩ VGS(th) Gate Threshold Voltage VDS=VGS, ID=-250uA -1 - -3 V gfs Forward Transconductance VDS=-10V, ID=-5.3A - 10 - S IDSS Drain-Source Leakage Current (Tj=25oC) VDS=-30V, VGS=0V - - -1 uA Drain-Source Leakage Current (Tj=70oC) VDS=-24V, VGS=0V - - -25 uA IGSS Gate-Source Leakage VGS=- - nA Qg Total Gate Charge2 ID=-5.3A - 9.2 16 nC Qgs Gate-Source Charge VDS=-24V - 2.8 - nC Qgd Gate-Drain ("Miller") Charge VGS=-4.5V - 5.2 - nC td(on) Turn-on Delay Time2 VDS=-15V - 11 - ns tr Rise Time ID=-1A - 8 - ns td(off) Turn-off Delay Time RG=6Ω ,VGS=-10V - 25 - ns tf Fall Time RD=15Ω -1 7- ns Ciss Input Capacitance VGS=0V - 507 912 pF Coss Output Capacitance VDS=-15V - 222 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 158 - pF Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Units VSD Forward On Voltage2 IS=-2.3A, VGS=0V - - -1.2 V trr Reverse Recovery Time IS=-5.3A, VGS=0V, - 29 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs nC Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 120 °C/W when mounted on Min. copper pad. ± 25V ±100

www.SiliconStandard.com 3 of 4 SSM9435K Rev.1.01 5/25/2004 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature Fig 5. Forward Characteristic of Fig 6. Gate Threshold Voltage vs. Reverse Diode Junction Temperature 012345 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T A =25 o C -10V -8.0V -6.0V -5.0V V G =-4.0V 01234567 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T A =150 o C -10V -8.0V -6.0V -5.0V V G =-4.0V 0.01 0.10 1.00 10.00 100.00 -V SD , Source-to-Drain Voltage (V) -IS(A) T j =25 o CT j =150 o C -50 0 50 100 150 T j , Junction Temperature ( o C) VGS(th) (V) 100 110 34567891 01 1 -V GS , Gate-to-Source Voltage (V) RDS(ON) (mΩ ) I D =5.3A T A =25°C 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) V G =10V I D =-5.3A

Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. www.SiliconStandard.com 4 of 4 SSM9435K Rev.1.01 5/25/2004 td(on) tr td(off)tf VDS VGS 10% 90% Q VG -4.5V QGS QGD QG Charge Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedanc e 0.01 0.1 100 0.1 1 10 100 -V DS , Drain-to-Source Voltage (V) -ID (A) T A =25 o C Single Pulse 1ms 10ms 100ms DC 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Normalized Thermal Response (Rthja) PDM Duty factor = t/T Peak Tj = PDM x Rthja + Ta t T 0.02 0.01 0.05 0.1 0.2 DUTY=0.5 Single Pulse Rthja = 120°C/W Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics 02468 1 0 1 2 1 4 1 6 1 8 Q G , Total Gate Charge (nC) -VGS , Gate to Source Voltage (V) I D = -5.3A V DS = -24V 100 1000 10000 1 5 9 1 31 72 12 52 9 -V DS , Drain-to-Source Voltage (V) C (pF) f=1.0MHz Ciss Coss Crss