SSM6322 (Rev. 0)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 20
Technical content
High Fidelity, Low Power, Integrated Stereo Audio Amplifier Data Sheet SSM6322 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Flexible architecture to interface with all digital-to-analog converters (DACs) Accepts differential current or voltage input (provides single-ended voltage output) High output current drive capability Greater than 100 mA rms output current Accurately reproduces large music transients into heavy loads (16 Ω to 32 Ω) Excellent audio fidelity −121 dB total harmonic distortion plus noise (THD + N) at 1 kHz, 2 V rms output with ±5 V supply and 32 Ω load Low output integrated noise (10 Hz to 22 kHz) of 1.8 μV rms with A-weighted filter Supply range: ±3.3 V to ±6 V (typical) Low power operation Enabled: 60 mW, V CC = +5 V, VEE = −5 V Disabled/voice select: <30 μA Low power disable mode with high output impedance High-Z in power-down mode eliminating voice mode switch from the high fidelity path Greater than 87 dB power supply rejection ratio (PSRR) at 20 kHz Adjustable input common-mode voltage with resistor programmable reference voltage
1.45 V (typical) with no external components
Capable of two single-pole, low-pass filters in series 2.2 nF maximum input capacitor Second filter between the GAINx and FIL Tx pins Pop and click noise suppression Signal chain integration supports small printed circuit board (PCB) area Compact 4 mm × 4 mm LFCSP package
APPLICATIONS
High fidelity headphone drivers Mobile phones Bluetooth speakers and headphones Gaming notebooks and tablets A/V receivers Professional audio equipment Audio test equipment Automobile infotainment systems FUNCTIONAL BLOCK DIAGRAM SSM6322 GAIN1 VNFB1 REF1 GND1 VEE2 VP1 VN1 INPUT VOUT1 OUTPUT GAIN2 FILT1 FILT2 VP2 VN2 INPUT VOUT2 VNFB2 OUTPUT 24 23
9 REF2
Figure 1. GENERAL DESCRIPTION The SSM6322 is an integrated, dual-channel audio amplifier solution that interfaces directly with audio DAC/CODEC, maximizing the fidelity of high fidelity audio signal chains. The highly efficient design of the SSM6322 delivers outstanding audio performance while minimizing power dissipation for maximum battery life in portable applications. The SSM6322 features −121 dB THD + N at 1 kHz, along with very low output noise from 20 Hz to 20 kHz. The low power operation, high peak output current, and high PSRR make the SSM6322 an ideal candidate for applications that require high fidelity audio, high dynamic range, precision, and low power. This highly integrated drive solution also reduces development time while reducing board space and minimizing external components. The SSM6322 is available in a 24-lead LFCSP package. The SSM6322 operates over the industrial temperature of −40°C to +85°C.
Rev. 0 | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
3/2017—Revision 0: Initial Version
Rev. 0 | Page 3 of 20 SPECIFICATIONS ±5 V SUPPLY TA = 25°C, reference voltage (VREF) = 0 V , feedback resistor (RF) = gain resistor (RG) = 1 kΩ (see Figure 38), unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Gain Bandwidth RIN1 = 1 kΩ, RIN2 = 1 kΩ (see Figure 38), output voltage (VOUT) = 0.2 V p-p
25 MHz
Slew Rate Gain = 1, VOUT = 2 V step 18 V/μs Channel Separation 1 kHz to 10 kHz, input voltage (VIN) = 5 V p-p, RL = 600 Ω, 32 Ω, 16 Ω −140 dB DISTORTION PERFORMANCE THD + N 1 kHz, VOUT = 2 V rms, low-pass filter = 80 kHz, RL = 600 Ω −122 dB 1 kHz, VOUT =2 V rms, low-pass filter = 80 kHz, RL = 32 Ω −121 dB 1 kHz, VOUT = 1.6 V rms, low-pass filter = 80 kHz, RL = 16 Ω −118 dB Intermodulation Distortion (IMD) SMPTE two-tone, 4:1 (60 Hz and 7 kHz), gain = 1, VOUT = 2 V rms, RL = 600 Ω, 90 kHz measurement bandwidth −125 dB CCIF two-tone (19 kHz and 20 kHz), gain = 1, VOUT = 2 V rms, RL = 600 Ω, 90 kHz measurement bandwidth −131 dB NOISE PERFORMANCE A-Weight Output Noise f = 10 Hz to 22 kHz 1.8 μV rms Input Voltage Noise f = 10 Hz 5.2 nV/√Hz f = 100 kHz 3.6 nV/√Hz Input Current Noise f = 10 Hz 10 pA/√Hz f = 100 kHz 1.2 pA/√Hz DC PERFORMANCE Output Offset Voltage 90 250 μV Output Offset Voltage Drift 1.5 7.5 μV/°C Input Bias Current −2.4 −1.8 −1 μA Input Offset Current 60 320 nA Open-Loop Gain VOUT = ±2.3 V, RL = 600 Ω 107 120 dB INPUT CHARACTERISTICS Input Capacitance 2 pF Input Common-Mode Voltage Range I DIFF = 3 mA ±1.5 V Common-Mode Rejection VCM = ±1 V 113 140 dB VREF1/VREF2 Open Circuit Voltage Referenced to ground 1.45 V Output Current 15 μA OUTPUT CHARACTERISTICS Output Voltage Swing Each Output RL = 600 Ω ±3.3 ±3.4 V R L = 32 Ω ±2.8 ±2.9 V R L = 16 Ω ±2.0 ±2.6 V Output Current RL = 16 Ω, rms voltage (VRMS) = 1.6 V, THD + N= −118 dB 100 mA rms Short-Circuit Current RL = 10 Ω; source/sink +240/−190 mA Closed-Loop Output Impedance 10 Hz to 20 kHz 0.04 Ω
Rev. 0 | Page 4 of 20 Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Operating Range ±3.3 to ±6 V Quiescent Current VSD = VSD2 = VCCx, VREF = 0 V, per channel 3 3.35 mA Quiescent Current Power-Down Mode V SD = 0 V, VSD2 = VCCx, per channel 1.4 mA V SD = VSD2 = 0 V, per channel 15 μA DC Power Supply Rejection Ratio Supply voltage (V SY) = 3.3 V to 5.5 V 115 140 dB AC Power Supply Rejection Ratio 20 kHz 87 dB POWER-DOWN INPUTS Logic High Chip on, referenced to ground >1.5 V Logic Low Chip off, referenced to ground <0.75 V ±3.3 V SUPPLY TA = 25°C, VREF = 0 V , RF = RG = 1 kΩ (see Figure 38), unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Gain Bandwidth RIN1 = 1 kΩ, RIN2 = 1 kΩ (see Figure 38), VOUT = 0.2 V p-p 25 MHz Slew Rate Gain = 1, VOUT = 2 V step 14 V/μs Channel Separation 1 kHz to 10 kHz, VIN = 1 V p-p, RL = 600 Ω, 32 Ω, and 16 Ω −140 dB DISTORTION PERFORMANCE THD + N 1 kHz, VOUT = 1 V rms, low-pass filter = 80 kHz, RL = 600 Ω −116 dB 1 kHz, VOUT = 1 V rms, low-pass filter = 80 kHz, RL = 32 Ω −116 dB 1 kHz, VOUT = 0.9 V rms, low-pass filter = 80 kHz, RL = 16 Ω −111 dB NOISE PERFORMANCE A-Weight Output Noise f = 10 Hz to 22 kHz 1.8 μV rms Input Voltage Noise f = 10 Hz 5.2 nV/√Hz f = 100 kHz 3.6 nV/√Hz Input Current Noise f = 10 Hz 10 pA/√Hz f = 100 kHz 1.2 pA/√Hz DC PERFORMANCE Output Offset Voltage 90 250 μV Output Offset Voltage Drift 1.5 7.5 μV/°C Input Bias Current −2.4 −1.8 −1 μA Input Offset Current 60 300 nA Open-Loop Gain VOUT = ±2.3 V, RL = 600 Ω 106 120 dB INPUT CHARACTERISTICS Input Capacitance 2 pF Input Common-Mode Voltage Range Differential current (IDIFF) = 3 mA ±0.3 V Common-Mode Rejection Common-mode voltage (V CM) = ±0.3 V 109 135 dB VREF1/VREF2 V Open Circuit Voltage Referenced to ground 1.45 V Output Current 15 μA OUTPUT CHARACTERISTICS Output Voltage Swing Each Output RL = 600 Ω ±1.6 ±1.7 V R L = 32 Ω ±1.4 ±1.45 V R L = 16 Ω ±1.2 ±1.4 V Output Current RL = 16 Ω, VRMS = 0.9 V, THD + N = −111 dB 56 mA rms Short-Circuit Current RL = 10 Ω +115/−120 mA Closed-Loop Output Impedance 10 Hz to 20 kHz 0.04 Ω
Rev. 0 | Page 5 of 20 Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Operating Range ±3.3 to ±6 V Quiescent Current VSD = VSD2 = VCCx, VREF = 0 V, per channel 2.9 3.35 mA Quiescent Current Power-Down Mode VSD = 0 V, VSD2 = VCCx 1.3 mA V SD = VSD2 = 0 V 10 μA DC Power Supply Rejection Ratio V SY = 3.3 V to 5.5 V 115 140 dB AC Power Supply Rejection Ratio 20 kHz 85 dB POWER-DOWN INPUTS Logic High Chip on, referenced to ground >1.5 V Logic Low Chip off, referenced to ground <0.75 V
- EXPOSED PAD. CONNECT THE EXPOSED
Figure 3. Pin Configuration Table 5. Pin Function Descriptions 1 VN1 Negative Input of Channel 1 Input Stage. 2 VP1 Positive Input of Channel 1 Input Stage. 5 VP2 Positive Input of Channel 2 Input Stage. 6 VN2 Negative Input of Channel 2 Input Stage. 7 GAIN2 Output of Channel 2 Input Stage. 9 FILT2 Positive Input of Channel 2 Output Stage. 9 REF2 Input Common-Mode Voltage of Channel 2 Input Stage. 11 VEE2 Negative Supply 2. This pin is internally shorted to Pin 20. 12 VCC2 Positive Supply 2. This pin is internally shorted to Pin 19. 13 VOUT2 Output of Channel 2 Output Stage. 14 VNFB2 Negative Feedback of Channel 2 Output Stage. 15 SD2 Shuts Down Power for the Entire Device. This pin is referenced to ground. 16 SD Shuts Down Power for the Output Stage. This pin is referenced to ground. 17 VNFB1 Negative Feedback of Channel 1 Output Stage. 18 VOUT1 Output of Channel 1 Output Stage. 19 VCC1 Positive Supply 1. This pin is internally shorted to Pin 12. 20 VEE1 Negative Supply 1. This pin is internally shorted to Pin 11. 22 REF1 Input Common-Mode Voltage of Channel 1 Input Stage. 23 FILT1 Positive Input of Channel 1 Output Stage. 24 GAIN1 Output of Channel 1 Input Stage. EPAD Exposed Pad. Connect the exposed pad to a negative power plane (V−) or ground.
Figure 16. CCIF vs. Input Voltage (VIN), VSY = ±5 V Figure 17. Input Voltage Noise vs. Frequency, VSY = ±5 V Figure 18. Input Voltage Noise vs. Frequency, VSY = ±3.3 V Figure 19. Input Current Noise vs. Frequency Figure 20. Enabled Output Impedance vs. Frequency
600 CHANNELS
Figure 21. Input Offset Voltage (VOS) Distribution, VSY = ±5 V
Figure 22. Input Offset Voltage (VOS) Distribution, VSY = ±3.3 V Figure 23. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD), Figure 24. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD) Figure 25. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD), Figure 26. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD) , Figure 27. Positive Supply Current (+ISY) vs. Supply Voltage (VSY)
Figure 38. Test Circuit
additional amplifiers from the signal path. when the applied external signal is between the supply rails. 15 μA current results in a common-mode voltage of 0.765 V . current of only 15 μA (see Table 6). Table 6. Disabled Mode and Enabled Mode SD and SD2 = 1 Entire device is enabled.
which must be routed directly to the ground of the jack. resistors are suggested to avoid this situation (see Figure 46). Use a low dropout regulator (LDO) as the power supply. away from the SSM6322 circuit. connected to the negative supply plane or ground plane. The maximum input filter capacitor values are 2.2 nF. Figure 48. Sensing Ground of Input Stage
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
Figure 49. 24-Lead Lead Frame Chip Scale Package [LFCSP] registered trademarks are the prop erty of their respective owners.