SSM630GP

SSM630GP SSC | Alldatasheet

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www.SiliconStandard.com 1 of 7 N-channel Enhancement-mode Power MOSFET BVDSS 200V RDS(ON) 400mΩ ID 9A The SSM630GP achieves fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC Pb-free; RoHS-compliant TO-220 PRODUCT SUMMARY DESCRIPTION Notes: 1. Pulse width must be limited to avoid exceeding the safe operating area. 2. Pulse width <300us, duty cycle <2%. 3. Starting Tj = 25°C, VDD=50V , L=4.5mH , RG=25Ω, I AS=9A. converters and general load-switching circuits. The SSM630GP is in TO-220 for through-hole mounting where a small footprint is required on the board, and/or an G D S TO-220 (suffix P) external heatsink is to be attached. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Units VDS VGS ID IDM PD W/°C EAS Single pulse avalanche energy3 TSTG TJ Symbol Parameter Value Units RΘ JC Maximum thermal resistance, junction-case 1.7 °C/W RΘ JA Maximum thermal resistance, junction-ambient 62 °C/W Drain-source voltage 200 V Gate-source voltage ±30 V Continuous drain current, TC = 25°C 9 A TC = 100°C 5.7 A Pulsed drain current1 36 A Total power dissipation, TC = 25°C 74 W -55 to 150 °C Operating junction temperature range -55 to 150 °C Linear derating factor 0.59 240 mJ THERMAL CHARACTERISTICS Storage temperature range SSM630GP 8/2 2 /2006 Rev.3.1 IAR Avalanche current 9 A EAR Repetitive avalanche energy 7 mJ

ELECTRICAL CHARACTERISTICS (at Tj = 25°C, unless otherwise specified) Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-source breakdown voltage V GS=0V, ID=250uA 200 - - V Δ BVDSS/ ΔTj Breakdown voltage temperature coefficient Reference to 25°C, ID=1mA - 0.248 - V/°C RDS(ON) Static drain-source on-resistance V GS=10V, ID=5A - - 400 mΩ VGS(th) Gate threshold voltage VDS=VGS, ID=250uA 2 - 4 V gfs Forward transconductance V DS=10V, ID=5A - 40 - S IDSS Drain-source leakage current VDS=200V, VGS=0V - - 10 uA VDS=160V ,VGS=0V, Tj = 150°C - - 25 uA IGSS Gate-source leakage current VGS=±30V - - ±100 nA Qg Total gate charge 2 ID=9A - 25 - nC Qgs Gate-source charge VDS=160V - 3.6 - nC Qgd Gate-drain ("Miller") charge V GS=10V - 14 - nC td(on) Turn-on delay time 2 VDS=100V - 8 - ns tr Rise time ID=9A - 26 - ns td(off) Turn-off delay time R G=10Ω , V GS=10V - 34 - ns tf Fall time R D=11Ω - 22 - ns Ciss Input capacitance VGS=0V - 515 - pF Coss Output capacitance VDS=25V - 90 - pF Crss Reverse transfer capacitance f=1.0MHz - 40 - pF Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Units VSD Forward voltage 2 IS= 9A, VGS=0V - - 1.3 V IS Continuous source current (body diode) VD=VG=0V , VS=1.3V - - 36 A I SM Pulsed source current (body diode)1 - - 9 A www.SiliconStandard.com 2 of 7 SSM630GP 8/2 2 /2006 Rev.3.1

www.SiliconStandard.com 3 of 7 SSM630GP 8/2 2 /2006 Rev.3.1 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. Normalized BVDSS vs. Junction Fig 4. Normalized On-Resistance Temperature vs. Junction Temperature 0.5 1.5 2.5 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) V G =10V I D =5A 0 2 4 6 8 10 12 14 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T C =25 o C V G =7.0V V G =6.0V V G =5.0V V G =4.0V V G =8.0V V G =10V 02468 1 0 1 2 1 4 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T C =150 o C V G =7.0V V G =6.0V V G =5.0V V G =4.0V V G =8.0V V G =10V 0.8 0.9 1.1 1.2 -50 0 50 100 150 T j , Junction Temperature ( o C ) Normalized BVDSS (V)

www.SiliconStandard.com 4 of 7 SSM630GP 8/2 2/2006 Rev.3.1 Fig 5. Maximum Drain Current vs. Fig 6. Typical Power Dissipation Case Temperature Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance 0 50 100 150 Tc , Case Temperature ( o C) PD (W) 25 50 75 100 125 150 T c , Case Temperature ( o C) ID , Drain Current (A) 100 1 10 100 1000 V DS (V) ID (A) T c =25 o C Single Pulse 10us 100us 1ms 10ms 100ms 0.01 0.1 t , Pulse Width (s) Normalized Thermal Response (R thjc) PDM Duty factor = t/T Peak Tj = PDM x Rthjc + TC t T 0.02 0.01 0.05 0.1 0.2 DUTY=0.5 SINGLE PULSE

www.SiliconStandard.com 5 of 7 SSM630GP 8/2 2/2006 Rev.3.1 Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics Fig 11. Forward Characteristic of Fig 12. Gate Threshold Voltage vs. Reverse Diode Junction Temperature 100 10000 11 1 2 1 3 1 V DS (V) C (pF) f=1.0MHz Ciss Coss Crss 2.5 3.5 -50 0 50 100 150 T j Junction Temperayure ( o C) VGS(th) (V) 0.01 0.10 1.00 10.00 100.00 V SD (V) IS (A) T j =25 o C T j =150 o C 0 5 10 15 20 25 30 35 Q G , Total Gate Charge (nC) VGS , Gate to Source Voltage (V) I D =9A V DS =80V V DS =120V V DS =160V

www.SiliconStandard.com 6 of 7 SSM630GP 8/2 2/2006 Rev.3.1 Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform td(on) tr td(off) tf VDS VGS 10% 90% Q VG 10V QGS QGD QG Charge 0.5x RATED VDS TO THE OSCILLOSCOPE 10 V D G S VDS VGS RG RD 0.8 x RATED V DS TO THE OSCILLOSCOPE D G S VDS VGS IDIG 1~ 3 mA

www.SiliconStandard.com 7 of 7 PHYSICAL DIMENSIONS - TO-220 PART MARKING - TO-220 PACKING: Moisture sensitivity level MSL3 1000pcs in tubes packed inside a 630GP YWWSSS DATE/LOT CODE: Y = last digit of the year WW = work week (01 -> 52) SSS = lot code sequence Millimeters MIN NOM MAX A 4.25 4.48 4.70 b 0.65 0.80 0.90 b1 1.15 1.38 1.60 c 0.40 0.50 0.60 c1 1.00 1.20 1.40 E 9.70 10.00 10.40 e ---- 2.54 ---- L 12.70 13.60 14.50 L1 2.60 2.80 3.00 L2 1.00 1.40 1.80 L3 2.6 3.10 3.6 L4 14.70 15.50 16 L5 6.30 6.50 6.70 φ 3.50 3.60 3.70 D 8.40 8.90 9.40 1. All dimensions are in m illimeters. 2. Dimensions do not include mold protrusions. SYMBOLS E b e D A c L φ SSM630GP 8/2 2 /2006 Rev.3.1 PART NUMBER: 630GP = SSM630GP moisture barrier bag (MBB). Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.