SSM4410M

SSM4410M SSC | Alldatasheet

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Technical content

www.SiliconStandard.com 1 of 6 SSM4410M N-CHANNEL ENHANCEMENT MODE POWER MOSFET Low on-resistance BV DSS 30V Fast switching RDS(ON) 13.5mΩ Simple drive requirement I D 10A

Description

ID @ TA=25°C ID @ TA=70°C IDM A PD @ TA=25°C W/°C TSTG TJ Symbol Value Unit Rthj-amb Thermal Resistance Junction-ambient Max. 50 °C/W Thermal Data Parameter Storage Temperature Range Total Power Dissipation 2.5 W -55 to 150 °C Operating Junction Temperature Range -55 to 150 °C Linear Derating Factor 0.02 Continuous Drain Current3 8 A Pulsed Drain Current1,2 50 Gate-Source Voltage Continuous Drain Current3 10 A Parameter Rating Drain-Source Voltage 30 Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SO-8 package is widely preferred for commercial and industrial surface mount applications and well suited for low voltage applications such as DC/DC converters. G D S ± 20 V S S S G D D D D SO-8 Rev.2.02 12/29/2003

www.SiliconStandard.com 2 of 6 SSM4410M Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=250uA 30 - - V Δ BV DSS/ Δ Tj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA - 0.037 - V/°C RDS(ON) Static Drain-Source On-Resistance VGS=10V, ID=10A - - 13.5 mΩ VGS=4.5V, ID=5A - - 22 mΩ VGS(th) Gate Threshold Voltage V DS=VGS, ID=250uA 1 - 3 V gfs Forward Transconductance V DS=15V, ID=10A - 20 - S IDSS Drain-Source Leakage Current (Tj=25oC) VDS=30V, VGS=0V - - 1 uA Drain-Source Leakage Current (Tj=55oC) VDS=24V, VGS=0V - - 25 uA IGSS Gate-Source Leakage VGS=- - nA Qg Total Gate Charge2 ID=10A - 16.6 - nC Qgs Gate-Source Charge V DS=15V - 2.7 - nC Qgd Gate-Drain ("Miller") Charge V GS=5V - 10.6 - nC td(on) Turn-on Delay Time2 VDS=25V - 9.6 - ns tr Rise Time I D=1A - 12.4 - ns td(off) Turn-off Delay Time RG=3.3Ω , VGS=5V - 25.4 - ns tf Fall Time RD=25Ω -3 3- ns Ciss Input Capacitance V GS=0V - 745 - pF Coss Output Capacitance V DS=15V - 510 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 210 - pF Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Units IS Continuous Source Current ( Body Diode ) VD=VG=0V , VS=1.3V - - 2.3 A ISM Pulsed Source Current ( Body Diode )1 -- 5 0 A VSD Forward On Voltage2 Tj=25°C, IS=2.3A, VGS=0V - - 1.3 V Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on FR4 board, t<10 sec. ± 20V ±100 Rev.2.02 12/29/2003

www.SiliconStandard.com 3 of 6 SSM4410M Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 0.6 0.8 1.2 1.4 1.6 1.8 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) I D =10A V G =10V 100 150 200 012345678 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T C =25 o C V G =10V V G =8.0V V G =6.0V V G =4.0V 100 150 02468 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T C =150 o C V G =4.0V V G =6.0V V G =8.0V V G =10V 3456789 1 0 1 1 V GS (V) RDSON (m ΩΩΩΩ) I D =10A T C =25 o C Rev.2.02 12/29/2003

www.SiliconStandard.com 4 of 6 SSM4410M Fig 5. Maximum Drain Current v.s. Fig 6. Typical Power Dissipation Case Temperature Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance 25 50 75 100 125 150 T c , Case Temperature ( o C ) ID , Drain Current (A) 0.5 1.5 2.5 0 30 60 90 120 150 T c , Case Temperature ( o C) PD (W) 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Normalized Thermal Response (R thja) PDM Duty factor = t/T Peak Tj = PDM x Rthja + Ta t T 0.02 0.01 0.05 0.1 0.2 DUTY=0.5 SINGLE PULSE 0.1 100 0.1 1 10 100 V DS (V) ID (A) T c =25 o C Single Pluse 1ms 10ms 100ms Rev.2.02 12/29/2003

www.SiliconStandard.com 5 of 6 SSM4410M Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics Fig 11. Forward Characteristic of Fig 12. Gate Threshold Voltage vs. Reverse Diode Junction Temperature -50 0 50 100 150 T j , Jujnction Temperature ( o C ) VGS(th) (V) 100 1000 10000 1 7 13 19 V DS (V) C (pF) f=1.0MHz Ciss Coss Crss 0.01 0.10 1.00 10.00 100.00 0 0.4 0.8 1.2 V SD (V) IS(A) T j =25 o C Tj =150 o C 0 5 10 15 20 25 Q G , Total Gate Charge (nC) VGS , Gate to Source Voltage (V) I D =10A V DS =15V Rev.2.02 12/29/2003

Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform td(on) tr td(off) tf VDS VGS 10% 90% Q VG QGS QGD QG Charge VDS = 25V TO THE OSCILLOSCOPE 5 v D G S VDS VGS RG RD 0.5 x RATED VDS TO THE OSCILLOSCOPE D G S VDS VGS IDI G 1~ 3 mA Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. www.SiliconStandard.com 6 of 6 Rev.2.02 12/29/2003