SSM4321ACBZ-RL

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Mono 2.9 W Class-D Audio Amplifier with Digital Current and Voltage Output Data Sheet SSM4321 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Filterless Class-D amplifier with spread-spectrum Σ-Δ modulation Digitized output of output voltage, output current, and PVDD supply voltage 72 dB signal-to-noise ratio (SNR) on output current sensing and 77 dB SNR on output voltage sensing TDM or multichip I2S slave output interface Up to 4 chips supported on a single bus 8 kHz to 48 kHz operation I2S/left justified slave output interface 1 or 2 chips supported on a single bus 8 kHz to 48 kHz operation PDM output interface operates from 1 MHz to 6.144 MHz 2.2 W into 4 Ω load and 1.4 W into 8 Ω load at 5.0 V supply with <1% total harmonic distortion plus noise (THD + N) 89% efficiency at 5.0 V, 1.4 W into 8 Ω + 0.2 Ω R SENSE speaker >100 dB signal-to-noise ratio (SNR) High PSRR at 217 Hz: 86 dB Amplifier supply operation from 2.5 V to 5.5 V Input/output supply operation from 1.42 V to 3.6 V Flexible gain adjustment pin: 0 dB to 12 dB in 3 dB steps with fixed input impedance of 80 kΩ <1 μA shutdown current Smart power-down with loss of BCLK Short-circuit and thermal protection with autorecovery Available in a 16-ball, 0.4 mm pitch, 1.74 mm × 1.74 mm WLCSP Pop-and-click suppression

APPLICATIONS

The SSM4321 is a fully integrated, high efficiency, Class-D audio amplifier with digitized output of output voltage, output current, and the PVDD supply voltage. It is designed to maximize performance for mobile phone applications. The application circuit requires a minimum of external components and operates from a 2.5 V to 5.5 V supply for the amplifier and a 1.42 V to 3.6 V supply for input/output. The SSM4321 is capable of delivering

2.2 W of continuous output power with <1% THD + N driving

a 4 Ω load from a 5.0 V supply with a 0.1 Ω V/I sense resistor. The SSM4321 features a high efficiency, low noise modulation scheme that requires no external LC output filters. The modulation scheme provides high efficiency even at low output power. The SSM4321 operates with 89% efficiency at 1.4 W into 8 Ω from a 5.0 V supply with an SNR of >100 dB. The SSM4321 includes circuitry to sense output current, output voltage, and the PVDD supply voltage. Current sense is performed using an external sense resistor that is connected between an output pin and the load. The output current and voltage are sent to ADCs with 16-bit resolution; the PVDD supply voltage is sent to an ADC with 8-bit resolution. The outputs of these ADCs are available on the TDM or I output serial port. The SLOT pin is used to determine which of four possible output slots is used on the TDM interface. A stereo I 2S interface can be selected by reversing the pin connections for BCLK and FSYNC. Also, a direct PDM bit stream of voltage and current data can be selected via the SLOT pin. Spread-spectrum pulse density modulation (PDM) is used to provide lower EMI-radiated emissions compared with other Class-D architectures. The inherent randomized nature of spread-spectrum PDM eliminates the clock intermodulation (beating effect) of several amplifiers in close proximity. The SSM4321 produces ultralow EMI emissions that significantly reduce the radiated emissions at the Class-D outputs, particularly above 100 MHz. The ultralow EMI emissions of the SSM4321 are also helpful for antenna and RF sensitivity problems. The device includes a highly flexible gain select pin that requires only one series resistor to select a gain setting of 0 dB, 3 dB, 6 dB, 9 dB, or 12 dB. Input impedance is fixed at 80 kΩ, independent of the selected gain. The SSM4321 has a shutdown mode with a typical shutdown current of <1 μA. Shutdown is enabled by removing the BCLK input. A clock must be present on the BCLK pin for the part to operate. The device also includes pop-and-click suppression circuitry, which minimizes voltage glitches at the output during turn-on and turn-off, reducing audible noise on activation and deactivation. The SSM4321 is specified over the industrial temperature range of −40C to +85C. It has built-in thermal shutdown and output short-circuit protection. It is available in a halide-free, 16-ball, 0.4 mm pitch, 1.74 mm × 1.74 mm wafer level chip scale package (WLCSP).

Rev. 0 | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

10/12—Revision 0: Initial Version

Rev. 0 | Page 3 of 24 FUNCTIONAL BLOCK DIAGRAM SENSE– OUT+ OUT– SENSE+ VREG IOVDD GND GAIN PVDD IN+ IN– SLOT BCLK_TDM/PDM_CLK/LRCLK_I2S FSYNC_TDM/BCLK_I2S SDATAO/PDM_DATA TDM OUTPUT PVDD ADC Σ-Δ ADC Σ-Δ ADC Σ-Δ CLASS-D MODULATOR FULL-BRIDGE POWER STAGE VOLTAGE SENSE CURRENT SENSE DIGITAL DECIMATION FILTERING 1.42V TO 3.6V 2.5V TO 5.5V SSM4321 10752-001 Figure 1.

Rev. 0 | Page 4 of 24 SPECIFICATIONS PVDD = 5.0 V, IOVDD = 1.8 V, fS = 24 kHz with I2S output, TA = 25°C, RL = 8 Ω +33 µH, unless otherwise noted. For RL = 8 Ω, use a 200 mΩ V/I sense resistor; for RL = 4 Ω, use a 100 mΩ V/I sense resistor; for RL = 3 Ω, use a 75 mΩ V/I sense resistor. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit DEVICE CHARACTERISTICS Output Power, RMS POUT f = 1 kHz, 20 kHz bandwidth RL = 8 Ω, THD = 1%, PVDD = 5.0 V 1.35 W RL = 8 Ω, THD = 1%, PVDD = 3.6 V 0.70 W RL = 8 Ω, THD = 1%, PVDD = 2.5 V 0.32 W RL = 8 Ω, THD = 10%, PVDD = 5.0 V 1.70 W RL = 8 Ω, THD = 10%, PVDD = 3.6 V 0.86 W RL = 8 Ω, THD = 10%, PVDD = 2.5 V 0.4 W RL = 4 Ω, THD = 1%, PVDD = 5.0 V 2.22 W RL = 4 Ω, THD = 1%, PVDD = 3.6 V 1.12 W RL = 4 Ω, THD = 1%, PVDD = 2.5 V 0.51 W RL = 4 Ω, THD = 10%, PVDD = 5.0 V 2.8 W RL = 4 Ω, THD = 10%, PVDD = 3.6 V 1.42 W RL = 4 Ω, THD = 10%, PVDD = 2.5 V 0.64 W RL = 3 Ω, THD = 1%, PVDD = 5.0 V 3.00 W RL = 3 Ω, THD = 1%, PVDD = 3.6 V 1.51 W RL = 3 Ω, THD = 1%, PVDD = 2.5 V 0.68 W RL = 3 Ω, THD = 10%, PVDD = 5.0 V 3.77 W RL = 3 Ω, THD = 10%, PVDD = 3.6 V 1.90 W RL = 3 Ω, THD = 10%, PVDD = 2.5 V 0.86 W Efficiency η POUT = 1.4 W into 8 Ω, PVDD = 5.0 V 89 % POUT = 2.8 W into 3 Ω, PVDD = 5.0 V 82 % Total Harmonic Distortion Plus Noise THD + N POUT = 1 W into 8 Ω, f = 1 kHz, PVDD = 5.0 V 0.01 % POUT = 0.5 W into 8 Ω, f = 1 kHz, PVDD = 3.6 V 0.01 % Input Common-Mode Voltage Range VCM 1.0 PVDD − 1 V Common-Mode Rejection Ratio CMRRGSM VCM = 100 mV rms at 1 kHz 50 dB Average Switching Frequency fSW 256 kHz Clock Frequency fOSC 6.2 MHz Differential Output Offset Voltage VOOS Gain = 6 dB 0.3 5.0 mV POWER SUPPLY Supply Voltage Range PVDD Guaranteed from PSRR test 2.5 5.5 V IOVDD 1.42 3.6 V Power Supply Rejection Ratio PSRRGSM VRIPPLE = 100 mV at 217 Hz, inputs are ac-grounded, CIN = 0.1 µF 86 dB Supply Current, PVDD ISYPVDD VIN = 0 V No load, PVDD = 5.0 V 3.7 mA No load, PVDD = 3.6 V 3.1 mA No load, PVDD = 2.5 V 2.9 mA RL = 8 Ω, PVDD = 5.0 V 3.8 mA RL = 8 Ω, PVDD = 3.6 V 3.2 mA RL = 8 Ω, PVDD = 2.5 V 2.9 mA Supply Current, IOVDD ISYIOVDD IOVDD = 1.8 V 0.41 mA Shutdown Current, PVDD ISDPVDD No BCLK, PVDD = 5.0 V 0.1 µA Shutdown Current, IOVDD ISDIOVDD No BCLK, IOVDD = 1.8 V 0.77 µA

Rev. 0 | Page 5 of 24 Parameter Symbol Test Conditions/Comments Min Typ Max Unit GAIN CONTROL Closed-Loop Gain Gain 0 12 dB Input Impedance ZIN BCLK enabled, fixed input impedance (0 dB to 12 dB) 80 kΩ SHUTDOWN CONTROL Turn-On Time tWU From BCLK start 12.5 ms Turn-Off Time tSD From BCLK removal 5 µs Output Impedance ZOUT No BCLK >100 kΩ AMPLIFIER NOISE PERFORMANCE Output Voltage Noise en f = 20 Hz to 20 kHz, inputs are ac-grounded, gain = 6 dB, A-weighted PVDD = 5.0 V 30 µV PVDD = 3.6 V 30 µV Signal-to-Noise Ratio SNR POUT = 1.3 W, RL = 8 Ω, A-weighted 101 dB OUTPUT SENSING Output Sampling Rate, TDM fS LRCLK/FSYNC pulse rate 8 48 kHz BCLK Frequency, TDM fBCLK 1 to 4 slots used 0.512 6.144 MHz Voltage Sense Signal-to-Noise Ratio SNRV A-weighted 77 dB Voltage Sense Full-Scale Output Voltage VFS Amplifier voltage with 0 dBFS ADC output 6 VP Voltage Sense Absolute Accuracy 1.5 % Voltage Sense Gain Drift TA = 10°C to 60°C 1 % Current Sense Signal-to-Noise Ratio SNRI A-weighted 72 dB Current Sense Full-Scale Input Voltage VIS ISENSE converter voltage with 0 dBFS ADC output 0.150 VP Current Sense Absolute Accuracy 3 % Current Sense Gain Drift TA = 10°C to 60°C, ideal RSENSE 1 % PVDD Sense Full-Scale Range PVFS PVDD with full-scale ADC output 2 6 V PVDD Sense Absolute Accuracy 3 % Current and Voltage Sense Linearity From −80 dBr to 0 dBr 1 dB ADC −3 dB Corner Frequency fC Digital high-pass filter Output fS = 48 kHz 3.75 Hz Output fS = 24 kHz 1.875 Hz DIGITAL INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit BCLK, FSYNC PINS Ball D2 and Ball D3 Input Voltage High VIH 0.7 × IOVDD 3.6 V Input Voltage Low VIL −0.3 0.3 × IOVDD V Input Leakage Current High IIH 1 µA Input Leakage Current Low IIL 1 µA Input Capacitance CIN 5 pF SDATAO/PDM_DATA PIN Ball D1 Output Drive Strength IOVDD = 1.5 V 3.5 mA IOVDD = 1.8 V 4.5 mA

Absolute maximum ratings apply at 25°C, unless otherwise noted. circuit board (PCB) for surface-mount packages. Table 4. Thermal Resistance

1 Unit

1 The θJA specification is measured on a JEDEC standard 4-layer PCB.

Figure 2. Pin Configuration Table 5. Pin Function Descriptions A1 OUT+ Noninverting Output. A3 PVDD Amplifier Power Supply. A4 VREG Internal LDO Regulator Output. B1 SENSE+ Current Sense Positive Input. C1 SENSE− Current Sense Negative Input. C2 SLOT TDM Slot Selection Input. C3 IOVDD Input/Output Digital Power Supply. D1 SDATAO/PDM_DATA TDM Serial Data Output/PDM Data Output. D2 FSYNC_TDM/BCLK_I2S TDM Frame Synchronization Input/I2S Bit Clock Input. TDM Bit Clock Input/PDM Clock Input/I2S LRCLK Input.

count, conserving board space and, thus, reducing system cost. component of the square wave output. in a number of important benefits.

• Σ-Δ modulators do not produce a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do.
• Σ-Δ modulation reduces the amplitude of spectral compo- nents at high frequencies, thus reducing EMI emissions that might otherwise be radiated by speakers and long cable traces.
• Due to the inherent spread-spectrum nature of Σ-Δ modu- lation, the need for oscillator synchronization is eliminated for designs that incorporate multiple SSM4321 amplifiers. The SSM4321 also integrates overcurrent and overtemperature protection. POWER-DOWN OPERATION The SSM4321 contains a clock loss detect circuit that works with the BCLK input clock. When no BCLK is present, the part automatically powers down all internal circuitry to its lowest power state. When a BCLK is returned, the part automatically powers up. If BCLK is active but FSYNC or LRCLK is not present, the amplifier continues to operate, but the ADC, sense blocks, and digital processing are shut down, reducing quiescent current when the output sense data is not needed. The ADC shutdown feature is not available in PDM operating mode. GAIN SELECTION The gain of the SSM4321 can be set from 0 dB to 12 dB in 3 dB steps using the GAIN pin and one (optional) external resistor. The external resistor is used to select the 9 dB or 12 dB gain setting (see Table 6).

Table 6. Setting the Gain of the SSM4321 with the GAIN Pin

0 Tie to GND

3 Open

6 Tie to PVDD

9 Tie to GND through a 47 kΩ resistor

12 Tie to PVDD through a 47 kΩ resistor

as low as 10 mV can be heard as an audible pop in the speaker. not coming from the system input signal. situation, noise sources are always present. with and without input stimulus. Figure 38. Three-Level, Σ-Δ Output Modulation

emissions at the Class-D outputs, particularly above 100 MHz. voltage greatly reduces radiated emissions. connected to one sense input pin (SENSE−). in signed fractional format.

0.75 A (6 V/8 Ω) with a 200 mΩ sense resistor results in full-scale

values for commonly used output loads. Table 7. Optimal Sense Resistor for Typical Loads output at a rate of 8 kHz to 48 kHz on Slot 2 of the TDM bus. The 16-bit data is in signed fractional format. on the TDM bus. The eight LSBs are driven low.

driven on the SDATAO/PDM_DATA pin at the IOVDD voltage. is output on the SDATAO/PDM_DATA pin one BCLK cycle later. The SDATAO signal should be latched on a rising edge of BCLK. Each slot is 64 BCLK cycles wide. configuration of the SLOT pin on the SSM4321 (see Table 8). The value of the SLOT pin must be stable at startup. Table 8. TDM Slot Selection impedance state when a slot is present that is not being driven. so that it is always in a known state. three SSM4321 devices and 12 TDM slots. Table 9. TDM Output Slot Example—Three SSM4321 Devices

1 Output current, Device 1

2 Output voltage, Device 1

3 PVDD voltage, Device 1

4 High-Z

5 Output current, Device 2

6 Output voltage, Device 2

7 PVDD voltage, Device 2

8 High-Z

9 Output current, Device 3

10 Output voltage, Device 3

11 PVDD voltage, Device 3

12 High-Z

• Selection of I2S or left justified mode.
• Output of PVDD sense information. When PVDD data is output, eight bits are appended to the 16-bit voltage sense data to create a 24-bit output. The 16 MSBs represent the voltage data; the eight LSBs represent the PVDD data.
• Sample rate range. The sample rate ranges from 16 kHz to 48 kHz. A range of 32 kHz to 48 kHz is also allowed in low power I2S mode.

Table 10. I2S and Left Justified Slot Selection

clock-cycle pulses, TDM operating mode is active instead. SLOT pin assignments to ID code. Table 11. Multichip I2S Slot Selection operation, depending on the number of chips detected on the bus. Table 12. FSYNC and BCLK Rates in Multichip I2S Mode, Table 13. FSYNC_TDM Pin Settings for PDM Mode

64 BCLKs

16 BCLKs

16 BCLKs 8 BCLKs

Figure 39. TDM Mode, One Device IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open.

16 BCLKs 16 BCLKs 8 BCLKs

128 BCLKs

Figure 40. TDM Mode, Two Devices IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open; IC 3: SLOT pin is tied to GND.

192 BCLKs

Figure 41. TDM Mode, Three Devices I2S output mode: SLOT pin is tied to GND. Left justified output mode: SLOT pin is tied to IOVDD through a 47 kΩ resistor.

16 BCLKs 16 BCLKs

8 BCLKs

Figure 42. I2S and Left Justified Modes with Voltage, Current, and PVDD Output, 64 × fS

I2S output mode: SLOT pin is tied to IOVDD (or tied to GND through a 47 kΩ resistor for low power operation at 64 × fS). Left justified output mode: SLOT pin is open. Figure 43. I2S and Left Justified Modes with Voltage and Current Output Only, 64 × fS SLOT pin is tied to GND through a 47 kΩ resistor for low power operation at 32 × fS.

32 BCLKs

Figure 44. I2S Low Power Mode with Voltage and Current Output Only, 32 × fS IC 1: SLOT pin is tied to IOVDD; IC 2: SLOT pin is open.

16 BCLKs 8 BCLKs 16 BCLKs

4 BCLKs

Figure 45. Multichip I2S Mode with Two Devices on the Bus Figure 46. Multichip I2S Mode with Three or Four Devices on the Bus

Rev. 0 | Page 21 of 24 APPLICATIONS INFORMATION LAYOUT As output power increases, care must be taken to lay out PCB traces and wires properly between the amplifier, load, and power supply. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. Ensure that track widths are at least 200 mil for every inch of track length for lowest DCR, and use 1 oz or 2 oz copper PCB traces to further reduce IR drops and inductance. A poor layout increases voltage drops, conse- quently affecting efficiency. Use large traces for the power supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Proper grounding helps to improve audio performance, mini- mize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load, as well as the PCB traces to the supply pins, should be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. In addition, good PCB layout isolates critical analog paths from sources of high interference. Separate high frequency circuits (analog and digital) from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emissions and increase immunity to the RF field by a factor of 10 or more compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane should be directly beneath the analog power plane, and, similarly, the digital ground plane should be directly beneath the digital power plane. There should be no overlap between the analog and digital ground planes or between the analog and digital power planes. INPUT CAPACITOR SELECTION The SSM4321 does not require input coupling capacitors if the input signal is biased from 1.0 V to PVDD − 1.0 V . Input capacitors are required if the input signal is not biased within this recommended input dc common-mode voltage range, if high-pass filtering is needed, or if a single-ended source is used. If high-pass filtering is needed at the input, the input capacitor (CIN) and the input impedance of the SSM4321 (80 kΩ) form a high-pass filter with a corner frequency determined by the following equation: fC = 1/(2π × 80 kΩ × CIN) The input capacitor value and the dielectric material can significantly affect the performance of the circuit. Not using input capacitors degrades both the output offset voltage of the amplifier and the dc PSRR performance. POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high PSRR, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input must be decoupled with a good quality, low ESL, low ESR capacitor, with a minimum value of 4.7 µF . This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, use a 0.1 µF capacitor as close as possible to the PVDD pin of the device. Placing the decoupling capacitors as close as possible to the SSM4321 helps to maintain efficient performance.

Figure 49. 16-Ball Wafer Level Chip Scale Package [WLCSP] 2 This package option is halide free.

Rev. 0 | Page 23 of 24 NOTES

Rev. 0 | Page 24 of 24 NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10752-0-10/12(0)