SSM4226M

SSM4226M SSC | Alldatasheet

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www.SiliconStandard.com 1 of 4 SSM4226M/GM 8/06/2004 Rev.1.02 DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Low on-resistance BVDSS 30V Simple drive requirement R DS(ON) 18mΩ High VGS rating ID 8.2A

Description

ID @ TA=25°C ID @ TA=70°C IDM A PD @ TA=25°C W/ °C TSTG TJ Symbol Value Unit Rthj-a Thermal Resistance Junction-ambient3 Max. 62.5 °C/W Parameter Rating Drain-Source Voltage 30 Gate-Source Voltage ± 20 Continuous Drain Current 3 8.2 A Continuous Drain Current3 6.7 A Pulsed Drain Current1 30 Total Power Dissipation 2 W -55 to 150 °C Operating Junction Temperature Range -55 to 150 °C Linear Derating Factor 0.016 Thermal Data Parameter Storage Temperature Range Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, ultra low on-resistance and cost-effectiveness. SO-8 This device is available with Pb-free lead finish (second-level interconnect) as SSM4226GM.

www.SiliconStandard.com 2 of 4 SSM4226M/GM 8/06/2004 Rev.1.02 Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage V GS=0V, ID=250uA 30 - - V Δ B VDSS /Δ Tj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA - 0.03 - V/°C RDS(ON) Static Drain-Source On-Resistance2 VGS=10V, ID=6A - - 18 mΩ VGS=4.5V, ID=4A - - 28 mΩ VGS(th) Gate Threshold Voltage V DS=VGS, ID=250uA 1 - 3 V gfs Forward Transconductance V DS=10V, ID=6A - 15 - S IDSS Drain-Source Leakage Current (Tj=25oC) VDS=30V, VGS=0V - - 1 uA Drain-Source Leakage Current (Tj=70oC) VDS=24V ,VGS=0V - - 25 uA IGSS Gate-Source Leakage V GS= ± 20V - - ±100 nA Qg Total Gate Charge2 ID=8A - 20 30 nC Qgs Gate-Source Charge V DS=24V - 5 - nC Qgd Gate-Drain ("Miller") Charge V GS=4.5V - 12 - nC td(on) Turn-on Delay Time2 VDS=15V - 12 - ns tr Rise Time ID=1A - 8 - ns td(off) Turn-off Delay Time RG=3.3Ω ,VGS=10V - 31 - ns tf Fall Time RD=15Ω -1 2- ns Ciss Input Capacitance V GS=0V - 1450 2320 pF Coss Output Capacitance V DS=25V - 320 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 230 - pF Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Units VSD Forward On Voltage2 IS=1.7A, VGS=0V - - 1.2 V trr Reverse Recovery Time I S=8A, VGS=0V, - 27 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 18 - nC Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 135°C/W when mounted on Min. copper pad.

www.SiliconStandard.com 3 of 4 SSM4226M/GM 8/06/2004 Rev.1.02 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature Fig 5. Forward Characteristic of Fig 6. Gate Threshold Voltage Reverse Diode vs. Junction Temperature 011223 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T A =150 o C 10V 5.0V 4.0V V G =3.0V 011223 V DS , Drain-to-Source Voltage (V) ID , Drain Current (A) T A =25 o C 10V 5.0V 4.0V V G =3.0V 0.6 0.8 1.2 1.4 1.6 1.8 -50 0 50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) I D =6A V GS =10V 2 4 6 8 10 12 V GS , Gate-to-Source Voltage (V) RDS(ON) (mΩ ) I D =6.0A T A =25°C 0.1 0 0.4 0.8 1.2 1.6 V SD ,Source-to-Drain Voltage (V) IS(A) T j =25 o CT j =150 o C 1.00 1.25 1.50 1.75 2.00 2.25 2.50 -50 0 50 100 150 T j , Junction Temperature ( o C ) VGS(th) (V)

Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. www.SiliconStandard.com 4 of 4 SSM4226M/GM 8/06/2004 Rev.1.02 Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1000 10000 1 5 9 13 17 21 25 29 V DS , Drain-to-Source Voltage (V) C (pF) f=1.0MHz Ciss Coss Crss 0 1 02 03 04 05 0 Q G , Total Gate Charge (nC) VGS , Gate to Source Voltage (V) V DS =15V V DS =20V V DS =24V I D =8A 0.001 0.01 0.1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , Pulse Width (s) Normalized Thermal Response (Rthja) PDM Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 135℃℃ ℃℃/W t T 0.02 0.01 0.05 0.1 0.2 Duty factor=0.5 Single Pulse 0.01 0.1 100 0.1 1 10 100 V DS (V) ID (A) T c =25 o C Single Pulse 1ms 10ms 100ms DC 100us Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance td(on) tr td(off) tf VDS VGS 10% 90% Q VG 4.5V QGS QGD QG Charge Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform