SSM3525BCBZRL

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30 W, Filterless, Class D, Output Sensing

Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES

Filterless digital input, mono Class D amplifier with Σ-Δ modulation Digitized output of output voltage, output current, and PVDD supply voltage Operates from 4.5 V to 17 V supply, such as a 2-cell or 3-cell battery Input/output supply operation from 1.1 V to 1.98 V

30.2 W output power, 17 V supply and 4 Ω load at 1% THD + N

37.5 μV rms noise, 107 dB A weighted signal-to-noise ratio I2C control with up to 4 pin-selectable addresses Multiple serial data formats TDM, I2S, or left justified slave PDM input/output operating from 2.048 MHz to

6.144 MHz

Support sample rates from 8 kHz to 192 kHz Flexible digital and analog gain adjustment AGC with battery voltage-based limiter 74 dB SNR on output current sensing and 85 dB SNR on voltage sensing 6.62 mA quiescent current at 12 V PVDD supply Temperature sensor with 1°C readout Short-circuit, thermal protection, and thermal warning 23-ball, 2.26 mm × 2.38 mm, 0.4 mm pitch WLCSP Pop and click suppression User-selectable ultralow EMI emissions mode Power-on reset

APPLICATIONS

The SSM3525 is a fully integrated, high efficiency, mono Class D audio amplifier with digital input and digitized output of output voltage, output current, and PVDD supply. The application circuit requires few external components and can operate from 4.5 V to 17 V (PVDD) and 1.8 V (IOVDD) supplies. It is capable of delivering 8.3 W of continuous output power into an 8 Ω load (or

15.3 W into 4 Ω) with <1% total harmonic distortion + noise (THD

+ N) from a 12 V supply, or 30.2 W into an 4 Ω load from a 17 V power supply, all with <1% THD + N. The SSM3525 features a high efficiency, low noise modulation scheme that requires no external inductor/capacitor (LC) output filters. This scheme continues to provide high efficiency even at low output power. It operates with 92% efficiency at 9 W into an 8 Ω load, 12V or 89% efficiency at 20 W into 4 Ω from a 17 V supply, and it has an signal-to-noise ratio (SNR) of 107 dB, A weighted. Spread spectrum pulse density modulation provides lower electromagnetic interference (EMI) radiated emissions compared with other Class D architectures, particularly above 100 MHz. The digital input eliminates the need of an external digital-to- analog converter (DAC). The SSM3525 has a micropower shutdown mode with a typical shutdown current of 90 nA at

12 V PV

DD supply. Individual sense blocks can be powered down to save power when sense is not needed. The device also includes pop and click suppression circuitry that minimizes voltage glitches at the output during turn on and turn off. Current sensing is accomplished using an integrated analog-to- digital converter (ADC) and internal sense resistor. The digitized voltage and current information can be returned in various serial audio formats, including I 2S, time division multiplexing (TDM) and pulse density modulation (PDM). The SSM3525 includes an integrated regulator to generate the required 5 V analog supply. Alternatively, if an external 5 V rail from a dc-to-dc converter is available, it can improve system efficiency. The SSM3525 is designed to operate with an I2C control interface and specified over the temperature range of −40°C to +85°C. It has built-in thermal shutdown and output short-circuit protection. It is available in a halide free, 23-ball, 2.26 mm × 2.38 mm wafer-level chip scale package (WLCSP).

Rev. A | Page 2 of 60 TABLE OF CONTENTS SSM3525 I2C Mode Register Map (SSM3525_I2C_Regmap) SSM3525 I2C Mode Register Map (SSM3525_I2C_REGMAP) Amplifier Gain, Edge Control, and Sense Sample Rate

Rev. A |Page 3 of 60

REVISION HISTORY

5/2018—Rev. 0 to Rev. A 1/2018—Revision 0: Initial Version

Figure 1. SSM3525 Block Diagram

Rev. A |Page 5 of 60 SPECIFICATIONS PVDD = 12 V, AVDD = 5 V (internal), IOVDD = 1.8 V (external), RL = 8 Ω + 33 μH, BCLK = 3.072 MHz, FSYNC = 48 kHz, −40°C to +85°C, unless otherwise noted. The measurements are taken with a 20 kHz AES17 low-pass filter. The other load impedances used are 4 Ω + 15 μH and 3 Ω +10 μH. The sine wave output powers above 20 W in 4 Ω cannot be continuous and might invoke the thermal limit indicator based on the power dissipation capability of the printed circuit board (PCB). Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit DEVICE CHARACTERISTICS Output Power/Channel POUT Frequency (f ) = 1 kHz RL = 8 Ω THD + N = 1%, PVDD = 17 V 15.2 W THD + N = 1%, PVDD = 12 V 8.3 W THD + N = 1%, PVDD = 7 V 2.8 W THD + N = 1%, PVDD = 5 V 1.4 W THD + N = 10%, PVDD = 17 V 18.7 W THD + N = 10%, PVDD = 12 V 10.4 W THD + N = 10%, PVDD = 7 V 3.5 W THD + N = 10%, PVDD = 5 V 1.8 W RL = 4 Ω THD + N = 1%, PVDD = 17 V 30.2 W THD + N = 1%, PVDD = 12 V 15.3 W THD + N = 1%, PVDD = 7 V 5.2 W THD + N = 1%, PVDD = 5 V 2.7 W THD + N = 10%, PVDD = 17 V 37.2 W THD + N = 10%, PVDD = 12 V 19.1 W THD + N = 10%, PVDD = 7 V 6.6 W THD + N = 10%, PVDD = 5 V 3.3 W Efficiency η POUT = 9 W, RL = 8 Ω, PVDD = 12 V 92.1 % POUT = 9 W, RL = 8 Ω, PVDD = 12 V (low EMI mode) 92 % POUT = 20 W, RL = 4 Ω, PVDD = 17 V 89 % POUT = 20 W, RL = 4 Ω, PVDD = 17 V (low EMI mode) 88.8 % Total Harmonic Distortion + Noise THD + N POUT = 5 W, RL = 8 Ω, f = 1 kHz, PVDD = 16 V 0.004 0.01 % Load Inductance 5 μH Output FET On Resistance RON 110 mΩ OverCurrent Protection Trip Point IOC 6 APEAK Average Switching Frequency fSW 300 kHz Differential Output Offset Voltage VOOS Gain = 8.9V/V ±5.0 mV POWER SUPPLIES Supply Voltage Range PVDD Guaranteed from PSRR test 4.5 17 V AVDD 4.5 5.0 5.5 V IOVDD I2S/TDM operation 1.1 1.80 1.98 V Power Supply Rejection Ratio (AC) PSRRAC VRIPPLE = 1 V rms at 1 kHz 87 73 dB GAIN CONTROL Measured with 0 dBFS input at 1 kHz, no load Output Voltage Peak Analog gain setting = 6.3 V/V with PVDD = 6.3 V 6.3 VPEAK Analog gain setting = 8.9 V/V with PVDD = 8.9 V 8.9 VPEAK Analog gain setting = 12.6 V/V with PVDD = 12.6 V 12.6 VPEAK Analog gain setting = 16.0 V/V with PVDD = 16 V 16 VPEAK PDM Input Gain PDM input density for full-scale output 0.5 FS

Rev. A | Page 6 of 60 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SHUTDOWN CONTROL Turn-On Time tWU I2S mode 10 ms Turn-Off Time tSD 500 µs Output Impedance ZOUT 100 kΩ NOISE PERFORMANCE1 Output Voltage Noise en f = 20 Hz to 20 kHz, A weighted, PVDD = 12 V 37.5 µV rms f = 20 Hz to 20 kHz, A weighted, PVDD = 17 V 48 µV rms Signal-to-Noise Ratio SNR POUT = 8.2 W, RL= 8 Ω, A weighted, PVDD = 12 V 107 dB POUT = 31 W, RL= 4 Ω, A weighted, PVDD = 17 V 107 dB OUTPUT SENSING Output Sampling Rate (TDM) fs FSYNC pulse rate 8 192 KHz PDM Gain Mapping Voltage to current (V/I) sense PDM output with full-scale input 0.71 FS Voltage Sense Signal-to- Noise Ratio SNRV 85 dB Voltage Sense Full-Scale VFS Output voltage at 0 dBFS output from ADC ±18 VPEAK Voltage Sense Absolute Accuracy Temperature = 0°C to 70° C, output >−40 dBFS ±1.5 % Voltage Sense Gain Drift Temperature = 0°C to 70° C, output >−40 dBFS 0.5 % Current Sense SNR SNRI 74 dB Current Sense Full-Scale ISENSE,FS Peak current with 0 dBFS output from ADC 6.96 APEAK Current Sense Absolute Accuracy Temperature = 0°C to 70° C, output >−40 dBFS ±2 % Current Sense Gain Drift Temperature = 0°C to 70° C, output >−40 dBFS ±0.5 % Voltage Sense over Current Sense Ratio Drift Temperature = 0°C to 70° C, output >−40 dBFS ±0.5 % PVDD Sense Full-Scale Range PVFS PVDD with full-scale ADC output 4 18 V PVDD Sense Absolute Accuracy Temperature = 0°C to 70°C 3 LSBs Current and Voltage Sense Linearity From −40 dBr to 0 dBr ±0.5 dB 1 The noise performance minimum and maximum limits are based on the bench data for −40°C to +85°C.

signal. All specifications are typical, with a 48 kHz sample rate, unless otherwise noted. Table 2. Power Supply Current Consumption1 Table 3. Digital Input/Output Table 4. I2C Port Timing

Table 5. Serial Port Digital Input Timing (I2S/TDM Operation Modes Only) Table 6. Serial Port Digital Output Timing (I2S/TDM Operation Modes Only) tBIL 8 ns BCLK low pulse width. tBIH 8 ns BCLK high pulse width. Table 7. PDM Timing Parameters Figure 2. I2C Port Timing

Absolute maximum ratings apply at 25°C, unless otherwise noted. JESD51-9 on a 4-layer PCB with natural convection cooling. Table 9. Thermal Resistance

1 Thermal impedance simulated values are based on JEDEC2S2P thermal

test board with two thermal vias. See JEDEC JESD51.

Figure 5. Ball Configuration (Top Side View) Table 10. Pin Function Descriptions A1 BST− AIN Bootstrap Capacitor, Inverting Output. A2 OUT− AOUT Inverting Output. A3, B3, C3 PVDD/VBAT PWR Power Stage Supply/Battery Supply. A4 OUT+ AOUT Noninverting Output. A5 BST+ AIN Bootstrap Capacitor, Noninverting Output. B1, B5, C1, C5 PGND PWR Power Stage Ground. B2 OUT− AOUT Inverting Output. B4 OUT+ AOUT Noninverting Output. D1 VREG/AVDD AIO Analog Input/Output. 5 V regulator output/AVDD input. D3 ADDR DIN Address Selection. D4 IOVDD PWR Input/Output and Digital Supply. D5 FSYNC DIN Frame Sync Input. E3 SDATAI DIN I2S/TDM Serial Data Input or PDM Data Input. E4 SDATAO DOUT I2S/TDM Serial Data Output or PDM Data Output. 1 AOUT is analog output, PWR is power supply or ground pin, AIN is analog input, DIN is digital input, DOUT is digital output, and DIO is digital input/output.

Figure 64. Typical Application Circuit

for designs incorporating multiple SSM3525 amplifiers. the battery or power supply in the system.

• PVDD, the power supply, is used for the output stage.
• AVDD is the analog supply used for the input stage, modulator, power stage gate drive, and other blocks. It can be generated internally by the integrated linear regulator. Alternatively, if higher system efficiency is needed, connect the AVDD pin to an external 5 V supply in the system.
• If the REG_EN control register is set to 1, the internal regulator is enabled; otherwise, an external 5 V supply is required.
• IOVDD is the digital supply voltage for the serial audio interface and internal digital circuitry. It must be supplied externally. ADDR PIN SETUP AND CONTROL The SSM3525 supports I2C control. The ADDR pin can be set to four different levels: pulled to GND, pulled up to IOVDD via a 47 kΩ resistor, pulled down to ground via a 47 kΩ resistor, or left open. The state of the ADDR pin determines the I2C device address. By default in I2C mode, the device uses the BCLK, FSYNC, SDATAI, and SDATAO pins for TDM/I2S data. Alternatively, the device can be set to receive and transmit PDM data by setting the PDM_MODE register bit field. See Table 12 for setting up the desired mode.

Table 11. I2C Address Selection Table 12. Serial Port Mode Setup for I2S, TDM, and PDM

Rev. A | Page 24 of 60 POWER-DOWN MODES The SSM3525 can be powered down by several methods. Setting the SPWDN bit to 1 in Register 0x20 fully powers down the device except for the I2C interface. Individual blocks can also be powered on or off via the block level power-down controls. For lowest power shutdown, the SSM3525 also contains a clock loss detection circuit that monitors the BCLK input clock. When no BCLK is present, the device automatically powers down all internal circuitry to its lowest power state. When BCLK returns, the device automatically powers up following its usual power sequence. There is an optional auto power-down feature when using I2S/TDM: the device enters a lower power state when 2048 consecutive zero input samples are received. The device auto- matically powers back up from this state once a single nonzero value sample is received. Only the I2C and digital audio input blocks are active. OUTPUT CURRENT SENSING The SSM3525 uses an integrated sense resistor (50 mΩ typical) to determine the output current flowing to the load. The voltage across this sense resistor is proportional to the load current and sent to a 1-bit ADC running nominally at 128 × fs. The sense voltage can be output in I2S/TDM format in I2S/TDM mode or via the PDM interface in PDM mode. The output of this ADC can also be downsampled using digital filtering. The data is 16 bits, twos complement and in signed fraction format. This downsampled signal is at an 8 kHz to 192 kHz sample rate. It can be output on the SDATAO pin. To s et a different sample rate for both current and voltage sensing, use the SNS_FS bit in Register 0x05. OUTPUT VOLTAGE SENSING The output voltage level is monitored at the OUT± pins and sent to a 1-bit analog to digital converter running nominally at 128 × fs. This can be output in PDM format in PDM mode or via the PDM interface in PDM mode. The output of this ADC is can also be downsampled using digital filtering. This downsampled signal at 8 kHz to 192 kHz sample rate is output on the digital audio interface. The data is 16 bits twos complement and in signed fraction format. It can be output on the SDATAO pin. TEMPERATURE SENSOR The SSM3525 contains an 8-bit ADC that measures the die temperature of the device and is enabled via the TEMP_PWDN bit in Register 0x20. After the sensor is enabled, the temperature sense value can be read via the I 2C in Register 0x12 in an 8-bit, unsigned format. The ADC input range is fixed internally from −60°C to +195°C. To convert the hexadecimal value to the temperature (Celsius) value, use the following steps: 1. Convert the hexadecimal value to decimal and then subtract 60. For example, if the hexadecimal value is 0x54, the decimal value is 84. 2. Calculate the temperature using the following equation: Temperature = Decimal Value − 60 3. With a decimal value of 84, Temperature = 84 − 60 = 24°C PCM DIGITAL AUDIO SERIAL INTERFACE The SSM3525 includes a standard serial audio interface that is slave only and used when in I2C mode. The interface is capable of receiving and transmitting I2S, left justified, pulse code modulated (PCM), or TDM formatted data. There is an input interface for sending audio to the DAC and amplifier and an output interface for the sense, temperature, and automatic gain control (AGC) gain data. These interfaces share the same FSYNC and BCLK signals. Provide a BCLK signal to the SSM3525 for correct operation. The BCLK signal must have a minimum frequency of 2.048 MHz. The BCLK signal internally clocks the device. The BCLK rate is auto detected, but the sampling frequency must be known to the device. At the 32 kHz to 48 kHz sample rate, the supported BCLK rates are 50, 64, 100, 128, 150, 192, 200, 250, 256, 384, 400, 500, 512, 768, 800, and 1024 times the sample rate. The serial interfaces have three main operating modes. Stereo modes, typically I2S or left justified, are used when there are one or two chips on the interface bus. TDM modes are more flexible and can support up to 32 chips on the bus. These mode selections can be set via the I2C interface with the SAI_MODE bit. The SAI_DRV bit setting determines the state of the SDATAO pin during the unused bit clock cycles. When the SAI_DRV bit is set to 1, the SDATAO pin is driven to logic low or not driven (high-Z) when set to 0. If using multiple chips on the serial interface bus, SAI_DRV bit must be set to 0. STEREO (I2S/LEFT JUSTIFIED) OPERATING MODE Stereo modes use both edges of the FSYNC signal to determine placement of data. Stereo mode is enabled when SAI_MODE = 0 and the I2S or left justified format is determined by the SDATA_FMT bit. The I2S or left justified formats accepts any number of BCLK cycles per FSYNC cycle. The six placement control registers (Address 0x24 to Address 0x29) determine placement of input and output data. Odd numbered placement control registers determine the order on the left channel and even number on the right channel. Sample rates from 8 kHz to 192 kHz are accepted.

SDATAO signal must be latched on a rising edge of BCLK. Bits Px_SNS in Register 0x24 to Register 0x29. bits (Px_SNS) for when output data is driven. several data placements of varying length. sequential order on the serial data signal. basic timing diagram of the placements in TDM mode. V/I marker and status data, or 8 zero bits. STATUS register, the formatting for can be seen in Figure 14.

8 BITS/16 BITS/24 BITS

Figure 65. Basic Timing Diagram of Placements in TDM Stream

Figure 66. Basic Timing Diagram of Placements in I2S Stream

16 BCLKs 16 BCLKs

8 BCLKs

Figure 67. Standard I2S Data Placement Timing Diagram

32 BCLKS

Figure 68. TDM Serial Interface Format Table 13. 8-Bit Status Sense Output Format (STATUS Register) Table 14. 8-Bit V/I Marker and Status Sense Output Format (STATUS Register) Figure 69. SDATA Output in PDM Mode Table 15. FSYNC Settings for PDM Mode

provide optimal gain staging at various PVDD supply voltages.

1. Convert the hex value to decimal. For example, if the

hexadecimal value is 0xA9, the decimal value is 169.

1. Calculate the voltage using the following equation:

interface, as previously mentioned. faults at the outputs and reporting to help with system design. The faults listed in Table 16 are reported using the status registers. Table 16. Register 0x11 Faults

5 V Regulator or AVDD

5 V regulator

6 A peak

can be read via I2C by the microcontroller in the system. faults can be controlled by using Register 0x10. Table 17. Register 0x10 Fault Recovery until the fault is resolved. disabled using LIM_EN, Bits[1:0] in Register 0x08. by the LIM_THRES register setting, in Register 0x09, Bits[7:3]. threshold can be set from 2 VPEAK to 16 VPEAK. voltage and not the limiter. battery voltage via the VBAT_TRACK bit (Register 0x08, Bit 2). 16 VPEAK using the LIM_THRES bit (see Figure 71). based on the VBAT supply voltage.

Rev. A | Page 30 of 60 Linking Limiters of Multiple SSM3525 Devices If multiple SSM3525 devices are used in a system, the gain adjustment from the limiters of all or some of the devices can be linked. The device internally generates the gain adjustment value (AGC_GAIN) based on the limiter settings. When limiters of multiple devices on the bus are linked, the device uses the highest (most gain reduction) gain adjustment value (AGC_GAIN) of all devices. Up to four SSM3525 devices can be linked in this manner. To link the AGC_GAIN to other chips, the LIM_LINKx bits must be set in the LIM_LINK register, 0x0E. When using I2S/TDM, for every chip that is linked, the placement of its respective AGC_GAIN value within the TDM stream must be given. The AGC_GAIN data for a respective device is made available at the assigned slot using the AGC_GAINx_SLOT bits. The AGC_GAIN data is eight bits wide and in an assigned slot, these bits can be placed in any one of eight places in a 64-bit frame. This setting is available in the AGC_GAINx_PLACE register. These values can be set in Register 0x2A through Register 0x2D. The audio signal is not affected by the AGC function unless the peak audio output voltage exceeds the limiter threshold level. POP AND CLICK SUPPRESSION Voltage transients at the output of audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as small as 10 mV can be heard as an audible pop in a speaker. Clicks and pops are defined as undesirable audible transients, generated by the amplifier system, that do not come from the system input signal. Such transients can be generated when the amplifier system changes its operating mode. For example, system power-up and power-down can be sources of audible transients. The SSM3525 has a pop and click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. Set either mute or power-down before the BCLK signal is removed to ensure a pop free power-down. HIGH FREQUENCY CLIPPER The high frequency clipper can be controlled via the DAC_CLIP bits (Register 0x0F , Bits[7:0]). These bits determine the clipper threshold, relative to full scale. When enabled, the clipper digitally clips the signal after the DAC interpolation. EMI NOISE The SSM3525 uses a proprietary modulation and spread spectrum technology to minimize EMI emissions from the device. The SSM3525 passes FCC Class B emissions testing with an unshielded 20 inch cable using ferrite bead-based filtering. For applications that have difficulty passing FCC Class B emission tests, the SSM3525 includes an ultralow EMI emissions mode that significantly reduces the radiated emissions at the Class D outputs, particularly above 100 MHz. Reducing the supply voltage greatly reduces radiated emissions. OUTPUT MODULATION DESCRIPTION The SSM3525 uses three-level, Σ-Δ output modulation. Each output can swing from ground to PVDD, and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, noise sources are always present. Due to this constant presence of noise, a differential pulse is occasionally generated in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. However, typically, the output differential voltage is 0 V. This feature ensures the current flowing through the inductive load is small. When the user sends an input signal, an output pulse is generated to follow the input voltage. The differential pulse density is increased by raising the input signal level. Figure 78 depicts three-level, Σ-Δ output modulation with and without input stimulus.

Figure 78. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus

the PVDD pins of the device. level of performance, particularly at the highest power levels. Figure 79. Recommended Component Placement {should PVDD, AVDD, and IOVDD be AVDD, PVDD, IOVDD?

Rev. A | Page 35 of 60 APPLICATIONS INFORMATION Figure 64 shows typical application for a single channel using I2S/TDM input and I2C control. In a typical application, the PVDD and IOVDD are supplied externally. AVDD can be generated using an internal regulator by setting the REG_EN bit in Register 0x04 to 1. Alternately, AVDD can be provided externally and disabling the REG_EN bit. By default, the AVDD regulator is disabled. The IOVDD by default is set to 1.8 V and can be changed to 1.2 V by using the IOVDD_SEL bit in Register 0x20. During power up, turn the PVDD supply on first, followed by IOVDD. While powering off, turn off the IOVDD supply first, followed by PVDD. The IOVDD must be stable before I2C commands are sent to the device. The digital input data can be 2-channel I2S or multichannel TDM format, and the desired format must be selected in the SAI control registers. Refer to the PCM Digital Audio Serial Interface section. On power-up, the device stays in power-down; to enable the amplifier, the SPWDN bit in Register 0x20 must be set to 0. Once this bit is set to 0, the amplifier turns on and the output starts switching. The slew rate for the output can be set to low EMI mode in Register 0x05. By default, the slew rate is set to normal mode. In low EMI mode, the output slew rate is reduced to lower the radiated emissions at the speaker output. The device can be reset to default settings by writing 1 to the S_RST bit in Register 0x2E. This bit must be cleared by writing 0 to bring the device out of reset. The PVDD (VBAT) sense cannot be powered down and is enabled by default. By default, the high pass filter is enabled and it is recommended to keep it enabled to block the dc from appearing at the speaker outputs. The fault status register, 0x11, can be read to check for any fault conditions during operation. FB1, FB2, C7, and C8 (see Figure 64) are recommended for filtering the switching noise and must be placed closer to the amplifier outputs to be effective.

Table 21. SSM3525_I2C_REGMAP Register Summary

Table 22. Bit Descriptions for VENDOR_ID Table 23. Bit Descriptions for DEVICE_ID1 Table 24. Bit Descriptions for DEVICE_ID2 Table 25. Bit Descriptions for REVISION_ID

turns on if VREG is not applied externally. 0: Never enable internal regulator. Table 26. Bit Descriptions for REG_ENABLE

0 REG_EN Internal Regulator Enable 0x0 R/W

0 Never enable internal regulator. 1 Normal operation. Internal regulator turns on if VREG is not applied externally. 1: I/V sense high pass filter off. 0: I/V sense high pass filter on. Table 27. Bit Descriptions for AMP_CTRL

7 SNS_HPF_BP I/V Sense High Pass Filter On/Off 0x0 R/W

0 I/V sense high pass filter on. 1 I/V sense high pass filter off. ratio of the DAC sample rate/sense sample rate. 00 8 kHz to 12 kHz I and V sense sample rate. 01 16 kHz to 24 kHz I and V sense sample rate. 10 32 kHz to 48 kHz I and V sense sample rate. 11 64 kHz to 96 kHz I and V sense sample rate. 100 128 kHz to 192 kHz I and V sense sample rate.

1: Hard/immediate volume change. 100: 128 kHz to 192 kHz sample rate. 011: 64 kHz to 96 kHz sample rate. 010: 32 kHz to 48 kHz sample rate. 001: 16 kHz to 24 kHz sample rate. 000: 8 kHz to 12 kHz sample rate. 0: DAC high pass filter off. Table 28. Bit Descriptions for DAC_CTRL

7 DAC_HV DAC Hard Volume 0x0 R/W

1 Hard/immediate volume change.

6 DAC_MUTE DAC Mute Control 0x0 R/W

5 DAC_HPF DAC High Pass Filter Enable 0x1 R/W

4 DAC_LPM DAC Low Power Mode Enable 0x1 R/W

3 DAC_POL DAC Output Polarity control 0x0 R/W

000 8 kHz to 12 kHz sample rate. 001 16 kHz to 24 kHz sample rate. 010 32 kHz to 48 kHz sample rate. 011 64 kHz to 96 kHz sample rate. 100 128 kHz to 192 kHz sample rate.

Table 29. Bit Descriptions for DAC_VOL

00: Limiter and mute mode off. gain reduction with battery voltage. 0: Limiter attack threshold fixed. Table 30. Bit Descriptions for LIM_CTRL1

2 VBAT_TRACK Threshold Battery Tracking Enable 0x1 R/W

0 Limiter attack threshold fixed. 1 Limiter attack threshold varies or gain reduction with battery voltage. 00 Limiter and mute mode off. 10 Output mutes if VBAT is below VBAT_INF. 11 Limiter on but only engages if VBAT is below VBAT_INF.

11: 4:1 threshold/battery reduction. 10: 3:1 threshold/battery reduction. 01: 2:1 threshold/battery reduction. 00: 1:1 threshold/battery reduction. Table 31. Bit Descriptions for LIM_CTRL2 00 1:1 threshold/battery reduction. 01 2:1 threshold/battery reduction. 10 3:1 threshold/battery reduction. 11 4:1 threshold/battery reduction.

Table 32. Bit Descriptions for LIM_CTRL3 voltage, see the PVDD (VBAT) Sensing section. Table 33. Bit Descriptions for VBAT_LIM_CTRL1

0 VBAT_LIM_EN VBAT Limiter Enable 0x0 R/W

Table 34. Bit Descriptions for VBAT_LIM_CTRL2 value to the corresponding battery voltage refer to VBAT sensing section. 1111: 12 dB maximum attenuation. 1110: 11.25 dB maximum attenuation. 1101: 10.5 dB maximum attenuation. 10: 2.25 dB maximum attenuation. 1: 1.5 dB maximum attenuation. 0: 0.75 dB maximum attenuation. Table 35. Bit Descriptions for VBAT_LIM_CTRL3 0 0.75 dB maximum attenuation. 1 1.5 dB maximum attenuation. 10 2.25 dB maximum attenuation. 11 3 dB maximum attenuation. 100 3.75 dB maximum attenuation. 101 4.5 dB maximum attenuation. 110 5.25 dB maximum attenuation. 111 6 dB maximum attenuation. 1000 6.75 dB maximum attenuation. 1001 7.5 dB maximum attenuation. 1010 8.25 dB maximum attenuation. 1011 9 dB maximum attenuation. 1100 9.75 dB maximum attenuation. 1101 10.5 dB maximum attenuation. 1110 11.25 dB maximum attenuation. 1111 12 dB maximum attenuation.

Table 36. Bit Descriptions for LIM_LINK

3 LIM_LINK4 Limiter Gain Link with AGC_GAIN4 Input 0x0 R/W

2 LIM_LINK3 Limiter Gain Link with AGC_GAIN3 Input 0x0 R/W

1 LIM_LINK2 Limiter Gain Link with AGC_GAIN2 Input 0x0 R/W

0 LIM_LINK1 Limiter Gain Link with AGC_GAIN1 Input 0x0 R/W

Table 37. Bit Descriptions for DAC_CLIP

10: 3 dB gain reduction in thermal warning. 01: 1.5 dB gain reduction in thermal warning. 00: No gain reduction in thermal warning. 11: Unlimited auto recovery attempts. 10: 7 auto recovery attempts. 01: 3 auto recovery attempts. Table 38. Bit Descriptions for FAULT_CTRL 00 No gain reduction in thermal warning. 01 1.5 dB gain reduction in thermal warning. 10 3 dB gain reduction in thermal warning. 11 5.625 dB gain reduction in thermal warning.

5 MRCV Manual Fault Recovery 0x0 W1

1 Writing 1 causes a manual fault recovery attempt when ARCV_x bits are set to 1. determines how many attempts at auto recovery are performed. 01 3 auto recovery attempts. 10 7 auto recovery attempts. 11 Unlimited auto recovery attempts.

2 ARCV_UV Undervoltage Auto Fault Recovery Control 0x0 R/W

0 Auto fault recovery for undervoltage fault. 1 Manual fault recovery for undervoltage fault.

1 ARCV_OT Overtemperature Auto Fault Recovery Control 0x0 R/W

0 Auto fault recovery for overtemperature fault. 1 Manual fault recovery for overtemperature fault.

0 ARCV_OC Over Current Auto Fault Recovery Control 0x0 R/W

0 Auto fault recovery for over current fault. 1 Manual fault recovery for over current fault.

1: Voltage regulator fault condition. 1: Battery voltage at or below VBAT_INF. 0: Battery voltage above VBAT_INF. 1: Over temperature warning condition. 1: Over temperature fault condition. 1: Amplifier over current fault condition. Table 39. Bit Descriptions for STATUS

7 UVLO_VREG Regulator Undervoltage Fault Status 0x0 R

1 Voltage regulator fault condition.

6 UVLO_PVDD PVDD Undervoltage Fault Condition 0x0 R

5 LIM_EG Limiter/Gain Reduction Engaged 0x0 R

1 Limiter or gain reduction has reduced gain.

4 CLIP Clip Detector 0x0 R

3 AMP_OC Amplifier Over Current Fault Status 0x0 R

1 Amplifier over current fault condition.

2 OTF Overtemperature Fault Status 0x0 R

1 Overtemperature fault condition.

1 OTW Overtemperature Warning Status 0x0 R

1 Overtemperature warning condition.

0 BAT_WARN Battery Voltage Warning 0x0 R

0 Battery voltage above VBAT_INF. 1 Battery voltage at or below VBAT_INF. Table 40. Bit Descriptions for TEMP convert the TEMP hexadecimal value to decimal and then subtract 60.

Table 41. Bit Descriptions for VBAT hexadecimal value to decimal, and then voltage = 4 + 14 × decimal value/255. 1: Software master power-down. 1: Voltage sense powered off. 0: Voltage sense powered on. 1: Current sense powered off. 0: Current sense powered on. 1: Temperature sensor powered down. Table 42. Bit Descriptions for PWR_CTRL

5 VSNS_PWDN Voltage Sense Power-Down 0x0 R/W

1 Voltage sense powered off.

4 ISNS_PWDN Current Sense Power-Down 0x0 R/W

1 Current sense powered off.

2 TEMP_PWDN Temperature Sensor Power-Down 0x1 R/W

1 Temperature sensor powered down.

1 IOVDD_SEL IOVDD Voltage Selection 0x0 R/W

I2C interface in a low power state. 1 Software master power-down.

1: PDM used for input and output. 1: 2 MHz to 3 MHz clock in PDM mode. 0: 4 MHz to 6 MHz clock in PDM mode. Table 43. Bit Descriptions for PDM_CTRL

4 PDM_FS PDM Sample Rate Selection 0x0 R/W

0 4 MHz to 6 MHz clock in PDM mode. 1 2 MHz to 3 MHz clock in PDM mode.

0 PDM_MODE PDM Input and Output Mode 0x0 R/W

1 PDM used for input and output. 100: 64 BCLKs per Chip in TDM. 011: 48 BCLKs per Chip in TDM. 010: 32 BCLKs per Chip in TDM. 001: 24 BCLKs per Chip in TDM. 000: 16 BCLKs per Chip in TDM. 1: Falling edge of BCLK registers SDATA. 0: Rising edge of BCLK registers SDATA. Table 44. Bit Descriptions for SAI_CTRL1

7 SAI_DRV Drive Control for Unused BCLK Cycles 0x0 R/W

0 Unused BCLK cycles on SDATAO are not driven (high-Z). 1 Unused BCLK cycles on SDATAO are driven low. number of bit clocks per chip must be defined. 000 16 BCLKs per chip in TDM. 001 24 BCLKs per chip in TDM. 010 32 BCLKs per chip in TDM. 011 48 BCLKs per chip in TDM. 100 64 BCLKs per chip in TDM.

3 BCLK_POL BCLK Polarity Control 0x0 R/W

0 Rising edge of BCLK registers SDATA. 1 Falling edge of BCLK registers SDATA.

2 FSYNC_MODE FSYNC Mode Control 0x0 R/W

0 Low FSYNC is left channel in stereo modes or pulsed FSYNC mode in TDM modes. 1 High FSYNC is left channel in stereo modes or 50% FSYNC mode in TDM modes.

1 SDATA_FMT Serial Data Format 0x0 R/W

0 I2S/delay by one bit clock from FSYNC edge. 1 Left Justified/no delay from FSYNC edge.

0 SAI_MODE Serial Interface Mode Selection 0x1 R/W

0 Stereo modes (I2S or left justified)

Table 45. Bit Descriptions for SAI_CTRL2

0011: 8-bit AGC_GAIN output. 0010: 8-bit battery voltage output unsigned. 0000: 16-bit voltage output. 0100: Alternating 16-bit voltage and current. Table 46. Bit Descriptions for SAI_PLACE1 0100 Alternating 16-bit voltage and current. 0110 8-bit V/I marker and status. 0111 8-bit temperature output. 0010 8-bit battery voltage output unsigned.

0111: 8-bit temperature output. 0110: 8-bit V/I marker and status. 0010: 8-bit battery voltage output unsigned. 0001: 16-bit current output. Table 47. Bit Descriptions for SAI_PLACE2 0010 8-bit battery voltage output unsigned. 0100 Alternating 16-bit voltage and current. 0110 8-bit V/I marker and status. 0111 8-bit temperature output. 0111: 8-bit temperature output. 0110: 8-bit V/I marker and status. 0010: 8-bit battery voltage output unsigned. 0001: 16-bit current output. Table 48. Bit Descriptions for SAI_PLACE3

0010 8-bit battery voltage output unsigned. 0100 Alternating 16-bit voltage and current. 0110 8-bit V/I marker and status. 0111 8-bit temperature output. 0111: 8-bit temperature output. 0110: 8-bit V/I marker and status. 0010: 8-bit battery voltage output unsigned. 0001: 16-bit current output. Table 49. Bit Descriptions for SAI_PLACE4 0010 8-bit battery voltage output unsigned. 0100 Alternating 16-bit voltage and current. 0110 8-bit V/I marker and status. 0111 8-bit temperature output.

0111: 8-bit temperature output. 0110: 8-bit V/I marker and status. 0010: 8-bit battery voltage output unsigned. 0001: 16-bit current output. 0000: 16-bit voltage output. Table 50. Bit Descriptions for SAI_PLACE5 0010 8-bit battery voltage output unsigned. 0100 Alternating 16-bit voltage and current. 0110 8-bit V/I marker and status. 0111 8-bit temperature output. 0111: 8-bit temperature output. 0110: 8-bit V/I marker and status. 0010: 8-bit battery voltage output unsigned. 0001: 16-bit current output. 0000: 16-bit voltage output. Table 51. Bit Descriptions for SAI_PLACE6 0010 8-bit battery voltage output unsigned. 0100 Alternating 16-bit voltage and current. 0110 8-bit V/I marker and status. 0111 8-bit temperature output.

1111: AGC_GAIN data placed in Slot 16. 1110: AGC_GAIN data placed in Slot 15. 1101: AGC_GAIN data placed in Slot 14. 10: AGC_GAIN data placed in Slot 3. 1: AGC_GAIN data placed in Slot 2. 0: AGC_GAIN data placed in Slot 1. Table 52. Bit Descriptions for AGC_PLACE1 0 AGC_GAIN1 data starts at Bit 0 within assigned slot. 1 AGC_GAIN1 data starts at Bit 8 within assigned slot. 10 AGC_GAIN1 data starts at Bit 16 within assigned slot. 11 AGC_GAIN1 data starts at Bit 24 within assigned slot. 100 AGC_GAIN1 data starts at Bit 32 within assigned slot. 101 AGC_GAIN1 data starts at Bit 40 within assigned slot. 110 AGC_GAIN1 data starts at Bit 48 within assigned slot. 111 AGC_GAIN1 data starts at Bit 54 within assigned slot. 0 AGC_GAIN data placed in Slot 1. 1 AGC_GAIN data placed in Slot 2. 10 AGC_GAIN data placed in Slot 3. 11 AGC_GAIN data placed in Slot 4. 100 AGC_GAIN data placed in Slot 5. 101 AGC_GAIN data placed in Slot 6. 110 AGC_GAIN data placed in Slot 7. 111 AGC_GAIN data placed in Slot 8. 1000 AGC_GAIN data placed in Slot 9. 1001 AGC_GAIN data placed in Slot 10. 1010 AGC_GAIN data placed in Slot 11. 1011 AGC_GAIN data placed in Slot 12. 1100 AGC_GAIN data placed in Slot 13. 1101 AGC_GAIN data placed in Slot 14. 1110 AGC_GAIN data placed in Slot 15. 1111 AGC_GAIN data placed in Slot 16.

1111: AGC_GAIN data placed in Slot 16. 1110: AGC_GAIN data placed in Slot 15. 1101: AGC_GAIN data placed in Slot 14. 10: AGC_GAIN data placed in Slot 3. 1: AGC_GAIN data placed in Slot 2. 0: AGC_GAIN data placed in Slot 1. Table 53. Bit Descriptions for AGC_PLACE2 0 AGC_GAIN2 data starts at Bit 0 within assigned slot. 1 AGC_GAIN2 data starts at Bit 8 within assigned slot. 10 AGC_GAIN2 data starts at Bit 16 within assigned slot. 11 AGC_GAIN2 data starts at Bit 24 within assigned slot. 100 AGC_GAIN2 data starts at Bit 32 within assigned slot. 101 AGC_GAIN2 data starts at Bit 40 within assigned slot. 110 AGC_GAIN2 data starts at Bit 48 within assigned slot. 111 AGC_GAIN2 data starts at Bit 54 within assigned slot. 0 AGC_GAIN data placed in Slot 1. 1 AGC_GAIN data placed in Slot 2. 10 AGC_GAIN data placed in Slot 3. 11 AGC_GAIN data placed in Slot 4. 100 AGC_GAIN data placed in Slot 5. 101 AGC_GAIN data placed in Slot 6. 110 AGC_GAIN data placed in Slot 7. 111 AGC_GAIN data placed in Slot 8. 1000 AGC_GAIN data placed in Slot 9. 1001 AGC_GAIN data placed in Slot 10. 1010 AGC_GAIN data placed in Slot 11. 1011 AGC_GAIN data placed in Slot 12. 1100 AGC_GAIN data placed in Slot 13. 1101 AGC_GAIN data placed in Slot 14. 1110 AGC_GAIN data placed in Slot 15. 1111 AGC_GAIN data placed in Slot 16.

1111: AGC_GAIN data placed in Slot 16. 1110: AGC_GAIN data placed in Slot 15. 1101: AGC_GAIN data placed in Slot 14. 10: AGC_GAIN data placed in Slot 3. 1: AGC_GAIN data placed in Slot 2. 0: AGC_GAIN data placed in Slot 1. Table 54. Bit Descriptions for AGC_PLACE3 0 AGC_GAIN3 data starts at Bit 0 within assigned slot. 1 AGC_GAIN3 data starts at Bit 8 within assigned slot. 10 AGC_GAIN3 data starts at Bit 16 within assigned slot. 11 AGC_GAIN3 data starts at Bit 24 within assigned slot. 100 AGC_GAIN3 data starts at Bit 32 within assigned slot. 101 AGC_GAIN3 data starts at Bit 40 within assigned slot. 110 AGC_GAIN3 data starts at Bit 48 within assigned slot. 111 AGC_GAIN3 data starts at Bit 54 within assigned slot. 0 AGC_GAIN data placed in Slot 1. 1 AGC_GAIN data placed in Slot 2. 10 AGC_GAIN data placed in Slot 3. 11 AGC_GAIN data placed in Slot 4. 100 AGC_GAIN data placed in Slot 5. 101 AGC_GAIN data placed in Slot 6. 110 AGC_GAIN data placed in Slot 7. 111 AGC_GAIN data placed in Slot 8. 1000 AGC_GAIN data placed in Slot 9. 1001 AGC_GAIN data placed in Slot 10. 1010 AGC_GAIN data placed in Slot 11. 1011 AGC_GAIN data placed in Slot 12. 1100 AGC_GAIN data placed in Slot 13. 1101 AGC_GAIN data placed in Slot 14. 1110 AGC_GAIN data placed in Slot 15. 1111 AGC_GAIN data placed in Slot 16.

1111: AGC_GAIN data placed in Slot 16. 1110: AGC_GAIN data placed in Slot 15. 1101: AGC_GAIN data placed in Slot 14. 10: AGC_GAIN data placed in Slot 3. 1: AGC_GAIN data placed in Slot 2. 0: AGC_GAIN data placed in Slot 1. Table 55. Bit Descriptions for AGC_PLACE4 0 AGC_GAIN4 data starts at Bit 0 within assigned slot. 1 AGC_GAIN4 data starts at Bit 8 within assigned slot. 10 AGC_GAIN4 data starts at Bit 16 within assigned slot. 11 AGC_GAIN4 data starts at Bit 24 within assigned slot. 100 AGC_GAIN4 data starts at Bit 32 within assigned slot. 101 AGC_GAIN4 data starts at Bit 40 within assigned slot. 110 AGC_GAIN4 data starts at Bit 48 within assigned slot. 111 AGC_GAIN4 data starts at Bit 54 within assigned slot. 0 AGC_GAIN data placed in Slot 1. 1 AGC_GAIN data placed in Slot 2. 10 AGC_GAIN data placed in Slot 3. 11 AGC_GAIN data placed in Slot 4. 100 AGC_GAIN data placed in Slot 5. 101 AGC_GAIN data placed in Slot 6. 110 AGC_GAIN data placed in Slot 7. 111 AGC_GAIN data placed in Slot 8. 1000 AGC_GAIN data placed in Slot 9. 1001 AGC_GAIN data placed in Slot 10. 1010 AGC_GAIN data placed in Slot 11. 1011 AGC_GAIN data placed in Slot 12. 1100 AGC_GAIN data placed in Slot 13. 1101 AGC_GAIN data placed in Slot 14. 1110 AGC_GAIN data placed in Slot 15. 1111 AGC_GAIN data placed in Slot 16.

1: Reset all blocks and I2C registers. Table 56. Bit Descriptions for SOFT_RESET

0 S_RST Full Software Reset 0x0 W

1 Reset all blocks and I2C registers.

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