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31 W, Filterless, Class-D Digital Input
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Filterless digital input, mono Class-D amplifier Operates from a single 4.5 V to 17 V supply
31.3 W output power, 17 V supply, and 4 Ω load at 1% THD + N
107 dB A-weighted signal-to-noise ratio 93.3% efficiency into 8 Ω load at 12 V I2C control with up to 4 pin selectable slots/addresses Supports multiple serial data formats up to TDM16 Digital interface supports sample rates from 8 kHz to 192 kHz Flexible digital and analog gain adjustment Flexible supply monitoring AGC function 6.55 mA quiescent current with single 17 V PVDD supply Short-circuit and thermal protection, thermal warning 20-ball, 1.8 mm × 2.2 mm, 0.4 mm pitch WLCSP Pop and click suppression User selectable ultralow EMI emissions mode Power-on reset
APPLICATIONS
The SSM3515 is a fully integrated, high efficiency, mono Class-D audio amplifier with digital inputs. The application circuit requires a minimum of external components and can operate from a single 4.5 V to 17 V supply. It can deliver 8.4 W of output power into an 8 Ω load or 15.8 W into an 4 Ω load from a 12 V power supply, or 31.3 W into an 4 Ω load from a 17 V power supply, all with 1% THD + N. The SSM3515 features a high efficiency, low noise modulation scheme that requires no external LC output filters. This scheme provides high efficiency even at low output power. It operates with 92% efficiency at 7 W into an 8 Ω load or 88% efficiency at 15 W into 4 Ω from a 12 V supply. Spread spectrum pulse density modulation provides lower EMI radiated emissions compared with other Class-D architectures, particularly above 100 MHz. The digital input eliminates the need for an external digital-to- analog converter (DAC). The SSM3515 has a micropower shutdown mode with a typical shutdown current of 39 nA at the 12 V PVDD supply. The device also includes pop and click suppression circuitry that minimizes voltage glitches at the output during turn on and turn off. The SSM3515 operates with or without an I2C control interface. The SSM3515 is specified over the commercial temperature range (−40°C to +85°C). It has built in thermal shutdown and output short-circuit protection. It is available in a halide-free, 20-ball, 1.8 mm × 2.2 mm wafer-level chip scale package (WLCSP). FUNCTIONAL BLOCK DIAGRAM BCLK FSYNC SDATA OUT+ OUT– VREG50/AVDD VREG18/DVDD AGND REG_EN PVDD PGND SCL SDA ADDR I2C TDM I2S INPUT VOLUME DAC FULL BRIDGE POWER STAGE Σ-Δ CLASS-D MODULATOR BST– BST+ SSM3515 1.8V 13327-001 Figure 1.
Rev. 0| Page 2 of 41 TABLE OF CONTENTS
REVISION HISTORY
6/15—Revision 0: Initial Version
Rev. 0| Page 3 of 41 SPECIFICATIONS PVDD = 12 V, VREG50/AVDD = 5 V (internal), VREG18/DVDD = 1.8 V (external), RL = 8 Ω + 33 μH, BCLK = 3.072 MHz and FSYNC = 48 kHz, TA = −40°C to +85°C, unless otherwise noted. The measurements are with a 20 kHz AES17 low-pass filter. The other load impedances used are 4 Ω + 15 μH and 3 Ω +10 μH. Measurements are with a 20 kHz AES17 low-pass filter, unless otherwise noted. The sine wave output powers above 20 W in 4 Ω cannot be continuous and may invoke the thermal limit indicator based on the power dissipation capability of the board. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit DEVICE CHARACTERISTICS Output Power/Channel POUT f = 1 kHz RL = 8 Ω THD + N = 1%, PVDD = 17 V 16 W THD + N = 1%, PVDD = 12 V 8.4 W THD + N = 1%, PVDD = 7 V 2.8 W THD + N = 1%, PVDD = 5 V 1.4 W THD + N = 10%, PVDD = 17 V 19.7 W THD + N = 10%, PVDD = 12 V 10.5 W THD + N = 10%, PVDD = 7 V 3.5 W THD + N = 10%, PVDD = 5 V 1.8 W RL = 4 Ω THD + N = 1%, PVDD = 17 V 31.3 W THD + N = 1%, PVDD = 12 V 15.8 W THD + N = 1%, PVDD = 7 V 5.4 W THD + N = 1%, PVDD = 5 V 2.8 W THD + N = 10%, PVDD = 17 V 39.3 W THD + N = 10%, PVDD = 12 V 19.7 W THD + N = 10%, PVDD = 7 V 6.7 W THD + N = 10%, PVDD = 5 V 3.4 W Efficiency η POUT = 9 W, RL = 8 Ω, PVDD = 12 V 93.3 % POUT = 9 W, RL = 8 Ω, PVDD = 12 V (low EMI mode) 93.2 % POUT = 30 W, RL = 4 Ω, PVDD = 17 V 88 % POUT = 30 W, RL = 4 Ω, PVDD = 17 V (low EMI mode) 87.8 % Total Harmonic Distortion + Noise THD + N POUT = 5 W into RL = 8 Ω, f = 1 kHz, PVDD = 16 V 0.004 % Load Resistance 3 Ω Load Inductance 5 10 μH Output FET On Resistance RON 110 mΩ Overcurrent Protection Trip Point IOC 5.8 A peak Average Switching Frequency fSW 300 kHz Differential Output DC Offset Voltage VOOS Gain = 12.6 V ±1 ±5.0 mV POWER SUPPLIES Supply Voltage Range PVDD Guaranteed from PSRR test 4.5 17 V VREG50/AVDD Internal 4.5 5.0 5.5 V VREG18/DVDD Internal or external 1.62 1.80 1.98 V AC Power Supply Rejection Ratio PSRRAC VRIPPLE = 1 V rms at 1 kHz 87 73 dB GAIN CONTROL Measured with 0 dBFS input at 1 kHz Output Voltage Peak Analog gain setting = 8.4 V/V with PVDD = 17 V 8.4 V peak Analog gain setting = 12.6 V/V with PVDD = 17 V 12.6 V peak Analog gain setting = 14.0 V/V with PVDD = 17 V 14 V peak Analog gain setting = 15.0 V/V with PVDD = 17 V 15 V peak
Rev. 0| Page 4 of 41 Parameter Symbol Test Conditions/Comments Min Typ Max Unit SHUTDOWN CONTROL1 Turn On Time, Volume Ramp Disabled tWU Time from SPWDN = 0 to output switching, DAC_HV = 1 or DAC_MUTE = 1, tWU = 4 FSYNC cycles to 7 FSYNC cycles + 7.68 ms fS = 12 kHz 8.01 8.27 ms fS = 24 kHz 7.84 7.98 ms fS = 48 kHz 7.76 7.83 ms fS = 96 kHz 7.72 7.76 ms fS = 192 kHz 7.70 7.72 ms Turn On Time, Volume Ramp Enabled tWUR Time from SPWDN = 0 to full volume output switching, DAC_HV = 0 and DAC_MUTE = 0, VOL = 0x40 fS = 12 kHz tWUR = tWU + 15.83 ms 23.84 24.10 ms fS = 24 kHz tWUR = tWU + 15.83 ms 23.67 23.81 ms fS = 48 kHz tWUR = tWU + 15.83 ms 23.59 23.66 ms fS = 96 kHz tWUR = tWU + 7.92 ms 15.64 15.68 ms fS = 192 kHz tWUR = tWU + 0.99 ms 8.69 8.71 ms Turn Off Time, Volume Ramp Disabled tSD Time from SPWDN = 1 to full power-down, DAC_HV = 1 or DAC_MUTE = 1 100 µs Turn Off Time, Volume Ramp Enabled tSDR Time from SPWDN = 1 to full power-down, DAC_HV = 0 and DAC_MUTE = 0, VOL = 0x40 fS = 12 kHz tSDR = tSD + 15.83 ms 15.932 ms fS = 24 kHz tSDR = tSD + 15.83 ms 15.932 ms fS = 48 kHz tSDR = tSD + 15.83 ms 15.932 ms fS = 96 kHz tSDR = tSD + 7.92 ms 8.016 ms fS = 192 kHz tSDR = tSD + 0.99 ms 1.09 ms Output Impedance ZOUT 100 kΩ NOISE PERFORMANCE2 Output Voltage Noise en f = 20 Hz to 20 kHz, A-weighted, PVDD = 12 V 37.5 µV rms f = 20 Hz to 20 kHz, A-weighted, PVDD = 17 V 48 µV rms Signal-to-Noise Ratio SNR POUT = 8.2 W, RL = 8 Ω, A-weighted, PVDD = 12 V 107 dB POUT = 31 W, RL = 4 Ω, A-weighted, PVDD = 17 V 107 dB PVDD ADC PERFORMANCE PVDD Sense Full-Scale Range PVDD with full-scale ADC out 3.8 16.2 V PVDD Sense Absolute Accuracy PVDD = 15 V −8 +8 LSB PVDD = 5 V −6 +6 LSB Resolution Unsigned 8-bit output with 3.8 V offset 8 Bits DIE TEMPERATURE Overtemperature Warning 117 °C Overtemperature Protection 145 °C 1 Guaranteed by design. 2 Noise performance is based on the bench data for TA = −40°C to +85°C.
zero input signal. All specifications are typical, with a 48 kHz sample rate, unless otherwise noted. Table 2. Power Supply Current Consumption1 Table 3. Power-Down Current Table 4. Digital Input/Output 1 The pull-up resistor for SCL and SDA must be scaled according to the external pull-up voltage in the system. The typical value for a pull-up resistor for 1.8 V is 2.2 kΩ.
All timing specifications are given for the default setting (I2S mode) of the serial input port. Table 5. I2C Port Timing Table 6. Digital Input Timing Figure 2. I2C Port Timing
printed circuit board (PCB) with natural convection cooling. Table 8. Thermal Resistance
Figure 6. Pin Configuration (Top Side View) Table 9. Pin Function Descriptions A1 VREG50/AVDD AOUT 5 V Regulator Output. A2 AGND PWR Analog Ground. It is recommended to connect the AGND pin to a single ground plane on the board. single ground plane on the board. A4 BST− AIN Bootstrap Capacitor for OUT−. B1 SDA DIO I 2C Serial Data. B2 ADDR DIN I 2C Address Selection. B3 OUT− AOUT Power Stage Inverting Output. B4 OUT− AOUT Power Stage Inverting Output. C2 REG_EN AIN Regulator Enable Tie to PVDD to Enable Regulators. C3 PVDD PWR Power Stage Supply. C4 PVDD PWR Power Stage Supply. D1 VREG18/DVDD PWR 1.8 V Regulator Output/DVDD Input. D2 FSYNC DIN TDM Frame Sync Input. D3 OUT+ AOUT Power Stage Noninverting Output. D4 OUT+ AOUT Power Stage Noninverting Output. E1 SDATA DIO Serial Data Input to DAC. E2 BCLK DIN TDM Bit Clock Input. single ground plane on the board. E4 BST+ AIN Bootstrap Capacitor for OUT+. 1 AOUT is analog output; PWR is power supply or ground pin; AIN is analog input; DIO is digital input/output; DIN is digital input.
nated for designs incorporating multiple SSM3515 amplifiers. supply regulation in the system. ground using the 100 nF and 10 µF capacitor. external 1.8 V supply can be used to save the power dissipation. 100 nF and 10 µF MLCC capacitors close to the pin. VREG18/DVDD voltage (generated internally) also ramps up. the device depends on the PVDD supply ramp-up time. I2C commands to enable the device. The SSM3515 offers several power down options via I2C. the I2C, 1.8 V regulator is kept alive. its usual power up sequence. Table 10. Regulator Enable Pin Function the 1.8 V supply must be stable.
The ADDR pin sets the device I2C address. See Table 11 for details. Table 11. Pin Setup List
Table 12. Operating Modes register control uses an I2C port. data format is determined by the SDATA_FMT register setting. 192 kHz are accepted. The maximum BCLK rate is 24.576 MHz. serial interface bus for audio data. latches on the rising edge of BCLK. The input data width to the DAC can be either 16-bit or 24-bit. a data transfer. Each slave device is recognized by a unique address. listed in Table 11. The address byte format is shown in Table 13. state of the ADDR pin. See Table 11 for four available addresses. 2C port is shown in Figure 61. one of two actions is taken.
The available options are as shown in Table 16. Table 16. Analog Gain Options
13 V to 14 V 10 14 V full-scale gain mapping
14 V to 16 V 11 15 V full-scale gain mapping
control in 0.375 dB steps from −70 dB to +24 dB. as small as 10 mV can be heard as an audible pop in the speaker. power-down can be sources of audible transients. removed to ensure a pop free power-down. situation, there are always noise sources present. current flowing through the inductive load is small.
- VOUT = (OUT+) – (OUT−) MEASURED ACROSS THE LOAD.
Figure 66. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus
faults at the outputs and reporting to help with system design. The faults listed in Table 17 are reported using the status registers. Table 17. Register 0x0A, Faults
5 V Regulator UV 5 V regulator voltage at
can be read via I2C by the microcontroller in the system. faults can be controlled by using Register 0x0B. Table 18. Register 0x0B, Fault Recovery repeats until the fault is resolved. information is stored in Register 0x06 as an 8-bit unsigned format.
- Convert the hex value to decimal. For example, if the hex
value is 0xA9, the decimal value = 169.
- Calculate the voltage using the following equation:
be enabled or disabled using LIM_EN, Bits[1:0] in Register 0x07. the LIM_THRES register setting, in Register 0x08, Bits[7:3]. threshold can be set from 1 V peak to 15 V peak. the power supply voltage and not the limiter. battery voltage via the VBAT_TRACK bit (Register 0x07, Bit 2). to 15 V peak using the LIM_THRES bit (see Figure 68). based on the VBAT supply voltage. inflection point, the VBAT_INF bits (Register 0x09, Bits[7:0]).
Rev. 0| Page 28 of 41 LAYOUT As output power increases, care must be taken to lay out PCB traces and wires properly among the amplifier, load, and power supply; a poor layout increases voltage drops, consequently decreasing efficiency. A good practice is to use short, wide PCB tracks to decrease voltage drops and minimize inductance. For lowest dc resistance (DCR) and minimum inductance, ensure that track widths are at least 200 mil for every inch of length and use 1 oz or 2 oz copper. Use large traces for the power supply inputs and amplifier outputs. Proper grounding guidelines improve audio performance, minimize crosstalk between channels, and prevent switching noise from coupling into the audio signal. To maintain high output swing and high peak output power, the PCB traces that connect the output pins to the load and supply pins must be as wide as possible to maintain the minimum trace resistances. It is also recommended that a large ground plane be used for minimum impedances. In addition, good PCB layout isolates critical analog paths from sources of high interference. Separate high frequency circuits (analog and digital) from low frequency circuits. Properly designed multilayer PCBs can reduce EMI emission and increase immunity to the RF field by a factor of 10 or more, compared with double-sided boards. A multilayer board allows a complete layer to be used for the ground plane, whereas the ground plane side of a double-sided board is often disrupted by signal crossover. If the system has separate analog and digital ground and power planes, the analog ground plane must be directly beneath the analog power plane, and, similarly, the digital ground plane must be directly beneath the digital power plane. There must be no overlap between analog and digital ground planes or between analog and digital power planes. BOOTSTRAP CAPACITORS The output stage of the SSM3515 uses a high-side NMOS driver, rather than PMOS. Therefore, a bootstrap supply is needed to drive the high-side NMOS. To generate the boosted gate driver voltage for the high-side NMOS, a 0.22 μF bootstrap capacitor is used from each output pin to BST± pins. This capacitor boosts the voltage at BST± pins when the high-side NMOS turns on and acts as a floating power supply for that particular switching cycle. The bootstrap capacitor is charged during the low-side NMOS active period. POWER SUPPLY DECOUPLING To ensure high efficiency, low total harmonic distortion (THD), and high power supply rejection ratio (PSRR), proper power supply decoupling is necessary. Noise transients on the power supply lines are short duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. The power supply input must be decoupled with a good quality, low ESL, low ESR bulk capacitor larger than 220 µF . This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, place 1 µF capacitors as close as possible to the PVDD pins of the device.
Table 20. Register Summary
Table 21. Bit Descriptions for Power Control power state when 2048 consecutive zero input samples have been received. 0 Battery Voltage Sense Powered On. 1 Battery Voltage Sense Powered Off. 1 Reset all Blocks and I 2C Registers. interface in a low-power state. 1 Software Master Power-Down. Table 22. Bit Descriptions for Gain and Edge Control 00: 8.4V Full-Scale Gain Mapping. 01: 12.6V Full-Scale Gain Mapping. 10: 14V Full-Scale Gain Mapping. 11: 15V Full-Scale Gain Mapping. 0: Auto Power-Down Disabled. 1: Software Master Power-Down. 0: Battery Voltage Sense Powered On. 1: Battery Voltage Sense Powered Off. 1: Reset all blocks and I2C registers.
00 8.4 V Full-Scale Gain Mapping. 01 12.6 V Full-Scale Gain Mapping. 10 14 V Full-Scale Gain Mapping. 11 15 V Full-Scale Gain Mapping. Table 23. Bit Descriptions for DAC Control 1 Hard/Immediate Volume Change. 1: Hard/Immediate Volume Change. 000: 8 kHz to 12 kHz Sample Rate. 001: 16 kHz to 24 kHz Sample Rate. 010: 32 kHz to 48 kHz Sample Rate. 011: 64 kHz to 96 kHz Sample Rate. 100: 128 kHz to 192 kHz Sample Rate. 101: 48 kHz to 72 kHz Sample Rate. 0: DAC High Pass Filter Off.
000 8 kHz to 12 kHz Sample Rate. 001 16 kHz to 24 kHz Sample Rate. 010 32 kHz to 48 kHz Sample Rate. 011 64 kHz to 96 kHz Sample Rate. 100 128 kHz to 192 kHz Sample Rate. 101 48 kHz to 72 kHz Sample Rate. Table 24. Bit Descriptions for DAC Volume Control
Table 25. Bit Descriptions for SAI Control 1 1 Invert the Audio Output Signal. 0 Rising Edge of BCLK is Used to Register SDATA. 1 Falling Edge of BCLK is Used to Register SDATA. 000 16 BCLKs per Chip in TDM. 001 24 BCLKs per Chip in TDM. 010 32 BCLKs per Chip in TDM. 011 48 BCLKs per Chip in TDM. 100 64 BCLKs per Chip in TDM.
0 Low FSYNC is Left Channel in Stereo Modes or Pulsed FSYNC Mode in TDM
1 High FSYNC is Left Channel in Stereo Modes or 50% FSYNC Mode in TDM Modes. 0 I2S/Delay by One from FSYNC Edge. 1 Left Justified/No Delay from FSYNC Edge. 1: Invert the Audio Output Signal. 0: I2S/Delay by one from FSYNC edge. 1: Left Justified/No delay from FSYNC edge. Modes or Pulsed FSYNC Mode in TDM Modes. Modes or 50% FSYNC Mode in TDM Modes. 000: 16 BCLKs per chip in TDM. 001: 24 BCLKs per chip in TDM. 010: 32 BCLKs per chip in TDM. 011: 48 BCLKs per chip in TDM. 100: 64 BCLKs per chip in TDM.
Table 26. Bit Descriptions for SAI Control 2 0 Audio Input on SDATA is 24 Bits. 1 Audio Input on SDATA is 16 Bits. 0 TDM Slot Determined by the TDM_SLOT Register. 1 TDM Slot Determined by the ADDR Pin. 0: Audio input on SDATA is 24 bits. 1: Audio input on SDATA is 16 bits. 0: TDM Slot determined by TDM_SLOT register. 1: TDM Slot determined by ADDR pin.
Table 27. Bit Descriptions for Battery Voltage Output Table 28. Bit Descriptions for Limiter Control 1 0 Limiter Attack Threshold Fixed. 1 Limiter Attack Threshold Varies or Gain Reduction with Battery Voltage. 00 Limiter and Mute Mode Off. 10 Output Mutes if VBAT is Below VBAT_INF. 11 Limiter On But Only Engages if VBAT is Below VBAT_INF. 00: Limiter and Mute Mode Off. 10: Output mutes if VBAT is below VBAT_INF. 0: Limiter Attack Threshold Fixed. reduction with Battery Voltage.
Table 29. Bit Descriptions for Limiter Control 2 00: 1:1 Threshold/Battery Reduction. 01: 2:1 Threshold/Battery Reduction. 10: 3:1 Threshold/Battery Reduction. 11: 4:1 Threshold/Battery Reduction.
00 1:1 Threshold/Battery Reduction. 01 2:1 Threshold/Battery Reduction. 10 3:1 Threshold/Battery Reduction. 11 4:1 Threshold/Battery Reduction. Table 30. Bit Descriptions for Limiter Control 3 Sensing section. Voltage = 3.8 + 12.4 × Decimal Value/255. Table 31. Bit Descriptions for Status 1 Voltage Regulator Fault Condition. 1 Limiter or Gain Reduction has Reduced Gain. 0: Battery Voltage above VBAT_INF. 1: Battery Voltage at or below VBAT_INF. 1: Over Temperature Warning Condition. 1: Amplifier Clipping Detected. 1: Amp Over-Current Fault Condition.
1 Amplifier Clipping Detected. 1 Amp Over-Current Fault Condition. 1 Overtemperature Fault Condition. 1 Overtemperature Warning Condition. 0 Battery Voltage Above VBAT_INF. 1 Battery Voltage at or Below VBAT_INF. Table 32. Bit Descriptions for Fault Control 00 No Gain Reduction in Thermal Warning. 01 1.5 dB Gain Reduction in Thermal Warning. 10 3 dB Gain Reduction in Thermal Warning. 11 5.625 dB Gain Reduction in Thermal Warning. 1 Writing of 1 Causes a Manual Fault Recovery Attempt when ARCV = 11. 00: No gain reduction in thermal warning. 01: 1.5dB gain reduction in thermal warning. 10: 3dB gain reduction in thermal warning. 11: 5.625dB gain reduction in thermal warning. recovery attempt when ARCV=11. 00: 1 Auto Recovery Attempt. 01: 3 Auto Recovery Attempts. 10: 7 Auto Recovery Attempts. 11: Unlimited Auto Recovery Attempts.
Rev. 0| Page 39 of 41 Bits Bit Name Settings Description Reset Access [4:3] MAX_AR Maximum Fault Recovery Attempts. The maximum autorecovery register determines how many attempts at autorecovery are performed. 0x3 R/W 00 1 Autorecovery Attempt. 01 3 Autorecovery Attempts. 10 7 Autorecovery Attempts. 11 Unlimited Autorecovery Attempts. 2 ARCV_UV Undervoltage Automatic Fault Recovery Control. 0x0 R/W 0 Automatic Fault Recovery for Undervoltage Fault. 1 Manual Fault Recovery for Undervoltage Fault. 1 ARCV_OT Overtemperature Automatic Fault Recovery Control. 0x0 R/W 0 Automatic Fault Recovery for Overtemperature Fault. 1 Manual Fault Recovery for Overtemperature Fault. 0 ARCV_OC Overcurrent Automatic Fault Recovery Control. 0x0 R/W 0 Automatic Fault Recovery for Overcurrent Fault. 1 Manual Fault Recovery for Overcurrent Fault.
1.60 REF
1.20 REF
Figure 76. 20-Ball Wafer Level Chip Scale Package [WLCSP] I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). registered trademarks are the property of their respective owners.