SSM3310GH SSC | Alldatasheet
Document overview
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Technical content
www.SiliconStandard.com 1 of 7 P-channel Enhancement-mode Power MOSFET 2.5V low gate drive capability BVDSS -20V Simple drive requirement R DS(ON) 150mΩ Fast switching ID -10A
DESCRIPTION
The SSM3310GH is in a TO-252 package, which is widely used for commercial and industrial surface mount applications, and is well suited for use in low voltage battery applications. The through-hole version, the SSM3310GJ in TO-251, is available for low-footprint vertical G D S TO-251 (J) G D S TO-252 (H) G D S mounting. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. ABSOLUTE MAXIMUM RATINGS Symbol Units VDS VGS V ID @ TC=25°C ID @ TC=100°C IDM PD @ TC=25°C W/°C TSTG TJ Symbol Value Unit Rthj-c Thermal Resistance Junction-case Max. 5 °C/W Rthj-a Thermal Resistance Junction-ambient Max. 110 °C/W Parameter Rating Drain-Source Voltage -20 V Gate-Source Voltage Continuous Drain Current -10 A Continuous Drain Current -6.2 A Pulsed Drain Current 1 -24 A Operating Junction Temperature Range -55 to 150 °C Linear Derating Factor 0.2 Storage Temperature Range Total Power Dissipation 25 W -55 to 150 °C THERMAL DATA Parameter ± 12 Pb-free; RoHS compliant. SSM3310GH,J 2/16/2005 Rev.2.1
www.SiliconStandard.com 2 of 7 SSM3310GH,J 2/16/2005 Rev.2.1 Electrical Characteristics @ Tj=25°C (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=-250uA -20 - - V Δ BVDSS/ ΔTj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=-1mA - -0.1 - V/°C RDS(ON) Static Drain-Source On-Resistance VGS=-4.5V, ID=-2.8A - - 150 mΩ VGS=-2.5V, ID=-2.0A - - 250 mΩ VGS(th) Gate Threshold Voltage VDS=VGS, ID=-250uA -0.5 - - V gfs Forward Transconductance VDS=-5V, ID=-2.8A - 4.4 - S IDSS Drain-Source Leakage Current (Tj=25oC) VDS=-20V, VGS=0V - - -1 uA Drain-Source Leakage Current (Tj=150oC) VDS=-16V, VGS=0V - - -25 uA IGSS Gate-Source Leakage VGS=- - nA Qg Total Gate Charge2 ID=-2.8A - 6 - nC Qgs Gate-Source Charge VDS=-6V - 1.5 - nC Qgd Gate-Drain ("Miller") Charge VGS=-5V - 0.6 - nC td(on) Turn-on Delay Time2 VDS=-6V - 25 - ns tr Rise Time ID=-1A - 60 - ns td(off) Turn-off Delay Time RG=6Ω, V GS=-5V - 70 - ns tf Fall Time RD=6Ω -60- ns Ciss Input Capacitance VGS=0V - 300 - pF Coss Output Capacitance VDS=-6V - 180 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 60 - pF Source-Drain Diode Symbol Parameter Test Conditions Min. Typ. Max. Units IS Continuous Source Current ( Body Diode ) VD=VG=0V , VS=-1.2V - - -10 A ISM Pulsed Source Current ( Body Diode )1 - - -24 A VSD Forward On Voltage2 Tj=25°C, IS=-10A, VGS=0V - - -1.2 V Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%. ± 12V ±100
www.SiliconStandard.com 3 of 7 SSM3310GH,J 2/16/2005 Rev.2.1 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 0.0 2.5 5.0 7.5 10.0 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T C =25 o C -4.5V -4.0V -3.5V -3.0V -2.5V V GS = -2.0V 02468 -V DS , Drain-to-Source Voltage (V) -ID , Drain Current (A) T C =150 o C -4.5V -4.0V -3.5V -3.0V -2.5V V GS = -2.0V 0.6 0.9 1.2 1.5 1.8 -50 100 150 T j , Junction Temperature ( o C) Normalized RDS(ON) I D = -2.8A V GS = -4.5V 200 400 600 800 024681 0 -V GS (V) RDS(ON) (mΩ ) I D = -2.8A T C =25°C
www.SiliconStandard.com 4 of 7 SSM3310GH,J 2/16/2005 Rev.2.1 Fig 5. Maximum Drain Current vs. Fig 6. Typical Power Dissipation Case Temperature Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance 25 50 75 100 125 150 T c , Case Temperature ( o C) -ID , Drain Current (A) 0 50 100 150 T c , Case Temperature ( o C) PD (W) 0.01 0.1 t , Pulse Width (s) Normalized Thermal Response (Rthjc) PDM Duty Factor = t/T Peak Tj = PDM x Rthjc + TC t T 0.02 0.01 0.05 0.1 0.2 Duty Factor = 0.5 Single Pulse 100 1 10 100 -V DS (V) -ID (A) 1ms 10ms 100ms T C =25 °C Single Pulse 100us
www.SiliconStandard.com 5 of 7 SSM3310GH,J 2/16/2005 Rev.2.1 Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics Fig 11. Forward Characteristic of Fig 12. Gate Threshold Voltage vs. Reverse Diode Junction Temperature 02468 Q G , Total Gate Charge (nC) -VGS , Gate to Source Voltage (V) I D =-2.8A V DS =-6V 100 1000 13579 1 1 1 3 -V DS (V) C (pF) f=1.0MHz Ciss Coss Crss -V SD (V) -IS(A) T j =25 o C Tj =150 o C 0.5 1.5 -50 0 50 100 150 T j , Junction Temperature ( o C) -VGS(th) (V)
www.SiliconStandard.com 6 of 7 SSM3310GH,J 2/16/2005 Rev.2.1 Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform td(on) tr td(off) tf VDS VGS 10% 90% Q VG QGS QGD QG Charge 0.3 x RATED VDS TO THE OSCILLOSCOPE -5 V D G S VDS VGS RG RD 0.3 x RATED VDS TO THE OSCILLOSCOPE D G S VDS VGS IDI G -1~-3mA -5V
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