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2 ×10 W Filterless Class-D Stereo Audio Amplifier Data Sheet SSM3302 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Filterless stereo Class-D amplifier with Σ-Δ modulation 2 × 10 W into 4 Ω load and 2 × 8 W into 8 Ω load at 12 V supply with <1% total harmonic distortion plus noise (THD + N) 91% efficiency at 12 V, 8 W into 8 Ω speaker 98 dB signal-to-noise ratio (SNR) Single-supply operation from 7 V to 18 V Flexible gain adjustment pin from 9 dB to 24 dB Fixed input impedance of 40 kΩ Mono output mode pin for 1 × 20 W output power into 2 Ω 10 µA shutdown current Short-circuit and thermal protection Available in a 40-lead, 6 mm × 6 mm LFCSP Pop-and-click suppression User-selectable ultralow EMI emissions mode Thermal warning indicator Power-on reset
APPLICATIONS
The SSM3302 is a fully integrated, high efficiency, stereo Class-D audio amplifier. The application circuit requires minimal external components and operates from a single 7 V to 18 V supply. The device is capable of delivering 2 × 10 W of continuous output power into a 4 Ω load (or 2 × 8 W into 8 Ω) with <1% THD + N from a 12 V supply. In addition, while mono mode is activated, the user can drive a load as small as 2 Ω up to 20 W continuous output power by stacking the stereo output terminals. The SSM3302 features a high efficiency, low noise modulation scheme that requires no external LC output filters. This scheme continues to provide high efficiency even at low output power. The SSM3302 operates with 90% efficiency at 7 W into an 8 Ω load or with 82% efficiency at 10 W into 4 Ω from a 12 V supply, and it has an SNR of >98 dB. Spread spectrum pulse density modulation (PDM) is used to provide lower EMI radiated emissions compared with other Class-D architectures. The SSM3302 includes an optional modulation select pin (ultralow EMI emission mode) that significantly reduces the radiated emissions at the Class-D outputs, particularly above 100 MHz. The SSM3302 can pass FCC Class-B emissions testing with an unshielded 20 inch cable using common-mode choke-based filtering. The fully differential input of the SSM3302 provides excellent rejection of common-mode noise on the input. The device also includes a highly flexible gain select pin that only requires one series resistor to choose a gain between 9 dB and 24 dB, with no change to the input impedance. The benefit of this is to improve gain matching between multiple SSM3302 devices within a single application compared with using external resistors to set gain. The SSM3302 includes an integrated voltage regulator that generates a 5 V rail. The SSM3302 has a micropower shutdown mode with a typical shutdown current of 10 µA. Shutdown is enabled by applying a logic low to the SD pin. The device also includes pop-and-click suppression circuitry that minimizes voltage glitches at the output during turn on and turn off, reducing audible noise during activation and deactivation. Other included features to simplify system level integration of the SSM3302 are input low-pass filtering to suppress out-of- band DAC noise interference to the pulse density modulator, fixed input impedance to simplify component selection across multiple platform production builds, and a thermal warning indicator pin. The SSM3302 is specified over the commercial temperature range (−40°C to +85°C). It has built-in thermal shutdown and output short-circuit protection. It is available in a halide-free, 40-lead, 6 mm × 6 mm lead frame chip scale package (LFCSP).
Rev. A | Page 2 of 20 TABLE OF CONTENTS
REVISION HISTORY
5/13—Rev. 0 to Rev. A Changed Voltage Rating from 6.3 V to 35 V in Bootstrap 2/12—Revision 0: Initial Version
Rev. A | Page 3 of 20 FUNCTIONAL BLOCK DIAGRAM Figure 1. SSM3302 10198-001 PVDD PGND THERM GAIN CONTROL 40kΩ 40kΩ MODULATOR (Σ-Δ) FET DRIVER INR+ INR– MONO INTERNAL OSCILLATOR BIAS BOOTR+ BOOTR– OUTR+ OUTR– EDGE CONTROL SDNR GAIN CONTROL 40kΩ 40kΩ MODULATOR (Σ-Δ) FET DRIVER INL+ INL– BOOTL+ EDGE BOOTL– OUTL+ OUTL– SDNL BIAS GAIN VREG VREG (AVDD) REGENAGND
Rev. A | Page 4 of 20 SPECIFICATIONS PVDD = 12 V, TA = 25oC, RL = 8 Ω + 64 μH, EDGE = AGND, gain = 9 dB, VREG = off, unless otherwise noted. Table 1. Parameter Symbol Test Conditions/Comments Min Typ Max Unit DEVICE CHARACTERISTICS Output Power/Channel PO RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 15 V 121 W RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 8 W RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 2.7 W RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 15 V 151 W RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 10 W RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 3.2 W RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 15 V 201 W RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 131 W RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 4.8 W RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 15 V 241 W RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V 161 W RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V 5.7 W RL = 2 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 12 V (mono mode) 292 W RL = 2 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, PVDD = 7 V (mono mode) 9.42 W RL = 2 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 12 V (mono mode) 36.62 W RL = 2 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, PVDD = 7 V (mono mode) 12.72 W Efficiency η PO = 7 W, 8 Ω, PVDD = 12 V, EDGE = low (normal operation) 91.5 % PO = 7 W, 8 Ω, PVDD = 12 V, EDGE = AVDD (ultralow EMI mode) 82 % Total Harmonic Distortion + Noise THD + N PO = 5 W into 8 Ω, f = 1 kHz, PVDD = 12 V 0.01 % Input Common-Mode Voltage Range VCM 1.0 AVDD − 1 V Common-Mode Rejection Ratio CMRR VCM = 2.5 V ± 100 mV at 1 kHz, output referred 43 dB Channel Separation XTALK PO = 0.5 W, f = 1 kHz 80 dB Average Switching Frequency fSW 300 kHz Differential Output Offset Voltage VOOS Gain = 9 dB 3.0 mV POWER SUPPLY Supply Voltage Range PVDD Guaranteed from PSRR test 7 18 V Power Supply Rejection Ratio PSRRDC PVDD = 7 V to 15 V, dc input floating 70 dB PSRRAC VRIPPLE = 100 mV at 1 kHz, inputs are ac grounded, CIN = 0.1 µF 80 dB Supply Current (Stereo) ISYPVDD VIN = 0 V, load = 8 Ω + 68 µH, PVDD = 15 V, VREGEN = AVDD (internal VREG active) 12.2 mA VIN = 0 V, load = 8 Ω + 68 µH, PVDD = 15 V, VREGEN = AGND (internal VREG disabled) 6.2 mA VIN = 0 V, load = 8 Ω + 68 µH, PVDD = 12 V, VREGEN = AGND (internal VREG disabled) 5 mA VIN = 0 V, load = 8 Ω + 68 µH, PVDD = 7 V, VREGEN = AGND (internal VREG disabled) 3 mA
Rev. A | Page 5 of 20 Parameter Symbol Test Conditions/Comments Min Typ Max Unit ISYAVDD VIN = 0 V, load = 8 Ω + 68 µH, PVDD = 15 V, VREGEN = AGND (internal VREG disabled) 5.85 mA VIN = 0 V, load = 8 Ω + 68 µH, PVDD = 12 V, VREGEN = AGND (internal VREG disabled) 5.8 mA VIN = 0 V, load = 8 Ω + 68 µH, PVDD = 7 V, VREGEN = AGND (internal VREG disabled) 5.6 mA Shutdown Current ISD SD = AGND 10 µA ANALOG SUPPLY External Supply Voltage AVDD Permissible range for external AVDD, VREGEN = AGND 4.5 5.5 V On-Board Regulator VVREG 5 V Regulator Current IVREG 20 mA Regulator Power Supply Rejection PSRRVREG 70 dB GAIN CONTROL Closed-Loop Voltage Gain AV See Table 5 for gain options 9 24 dB Input Impedance ZIN 40 kΩ SHUTDOWN CONTROL Input Voltage High VIH 1.35 V Input Voltage Low VIL 0.35 V Turn-On Time tWU SD rising edge from AGND to AVDD 40 ms Turn-Off Time tSD SD falling edge from AVDD to AGND 500 µs Output Impedance ZOUT SD = GND 56 kΩ AMPLIFIER PROTECTION Overcurrent Threshold IOC 6 A Overtemperature Warning TWARN 120 °C Overtemperature Shutdown TSD 145 °C Recovery Temperature TREC 85 °C NOISE PERFORMANCE Output Voltage Noise en PVDD = 12 V, f = 20 Hz to 20 kHz, inputs are ac grounded, gain = 9 dB, A-weighted 100 µV rms Signal-to-Noise Ratio SNR PO = 10 W, RL = 8 Ω 98 dB 1 Although the SSM3302 has good audio quality above 2 × 10 W into 4 Ω, continuous output power beyond 2 × 10 W into 4 Ω must be avoided due to device packaging limitations. 2 Mono mode. Output power beyond 20 W needs special care for thermally considered printed circuit board (PCB) design.
Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 3. Thermal Resistance
Figure 2. Pin Configuration (Top Side View) Table 4. Pin Function Descriptions 1 BOOTL+ Bootstrap Input/Output for Left Channel, Noninverting Output. 2, 3 OUTL+ Noninverting Output for Left Channel. 4, 5 OUTL− Inverting Output for Left Channel. 6 BOOTL− Bootstrap Input/Output for Left Channel, Inverting Output. 8 VREG/AVDD 5 V Regulator Output (if REGE N = high)/AVDD Input (if REGEN = low). 9 SDNL Shutdown, Left Channel. Active low digital input. 10 EDGE Edge Control (Low Emission Mode). Active high digital input. 11 INL+ Noninverting Input for Left Channel. 12 INL− Inverting Input for Left Channel. 13, 18 NC This pin is not connected internally (see Figure 2). 14, 15 TEST Test Pins. Tie to AGND. 16 MONO Mono Output Mode Enable. 17 THERM Overtemperature Warning (Open Collector). 19 INR− Inverting Input for Right Channel. 20 INR+ Noninverting Input for Right Channel. 21 GAIN Gain Select from 9 dB to 24 dB. 22 SDNR Shutdown, Right Channel. Active low digital input. 23 REGEN 5 V Regulator Enable, Active High. 25 BOOTR− Bootstrap Input/Output for Right Channel, Inverting Output. 26, 27 OUTR− Inverting Output for Right Channel. 28, 29 OUTR+ Noninverting Output for Right Channel. 30 BOOTR+ Bootstrap Input/Output for Ri ght Channel, Noninverting Output. 34, 35, 36, 37 PVDD Power Stage Power Supply. Exposed Pad Thermal Exposed Pad. Use multiple vias to connect this pad to the ground plane.
23 REGEN
24 AGND
25 BOOTR–
26 OUTR–
27 OUTR–
28 OUTR+
29 OUTR+
30 BOOTR+
22 SDNR
21 GAIN
- USE MULTIPLE VIAS TO CONNECT THE EXPOSED PAD
- PINS LABELED NC CAN BE ALLOWED TO FLOAT,
Figure 37. Stereo Mode Configuration
Figure 38. Mono Mode Configuration
inated for designs incorporating multiple SSM3302 amplifiers. protection, as well as an overtemperature warning indicator pin. capacitor from this pin to the AGND pin. limiter or other protection is provided. input coupling components can be used for all gain settings. Table 5. Gain Function Descriptions
24 Tie to AVDD
18 Tie to AVDD through 47 kΩ
15 Open
12 Tie to AGND through 47 kΩ
9 Tie to AGND
transistors do not switch until the fault is removed. rapid cycling of the output at high temperatures. small as 10 mV can be heard as an audible pop in the speaker. power-down can be sources of audible transients. the supply voltage greatly reduces radiated emissions. useful feature for driving the subwoofer in a 2.1 audio system.
situation, however, there are always noise sources present. current flowing through the inductive load is small. level, Σ-Δ output modulation with and without input stimulus. Figure 39. Three-Level, Σ-Δ Output Modulation With and large traces for the power supply inputs and amplifier outputs. noise from coupling into the audio signal. should be separated from low frequency circuits. without overtemperature issues. high-pass filtering is needed, or if a single-ended source is used. terminal acts as a floating power supply for the switching cycle.
Rev. A | Page 18 of 20 POWER SUPPLY DECOUPLING T o ensure high efficiency, low total harmonic distortion, and high power supply rejection ratio, proper power supply decoupling is necessary. Noise transients on the power supply lines are short-duration voltage spikes. These spikes can contain frequency components that extend into the hundreds of megahertz. Decouple the power supply input with a good quality, low ESL, low ESR bulk capacitor larger than 220 µF . This capacitor bypasses low frequency noises to the ground plane. For high frequency transient noises, place two separate 1 µF capacitors as close as possible to the PVDD pins of the device. Connect one of the 1 µF capacitors between the left-side PVDD terminals and PGND terminals, and connect the other 1 µF capacitor between the right-side PVDD terminals and PGND terminals. Placing the decoupling capacitor as close as possible to the SSM3302 helps to achieve the best performance.
Figure 40. 40-Lead Lead Free Chip Scale Package [LFCSP_WQ]
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Rev. A | Page 20 of 20 NOTES ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10198-0-5/13(A)