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The SSM2018T and SSM2118T represent continuing evolu- tion of the Frey Operational Voltage Controlled Element (OVCE) topology that permits flexibility in the design of high performance volume control systems. Voltage (SSM2018T) and differential current (SSM2118T) output versions are of- fered, both laser-trimmed for gain core symmetry and offset. As a result, the SSM2018T is the first professional audio quality VCA to offer trimless operation. The SSM2118T is ideal for low noise summing in large VCA based systems. Due to careful gain core layout, the SSM2018T/SSM2118T combine the low noise of Class AB topologies with the low dis- tortion of Class A circuits to offer an unprecedented level of sonic transparency. Additional features include differential in- puts, a 140 dB gain range, and a high impedance control port. The SSM2018T provides an internal current-to-voltage con- verter; thus no external active components are required. The SSM2118T has fully differential current outputs that permit high noise-immunity summing of multiple channels. Both devices are offered in 16-pin plastic DIP and SOIC pack- ages and guaranteed for operation over the extended industrial temperature range of –40°C to +85°C.
FEATURES
0.006% Typical THD+N (@ 1 kHz, Unity Gain) 140 dB Gain Range No External Trimming Required Differential Inputs Complementary Gain Outputs Buffered Control Port I–V Converter On-Chip (SSM2018T) Differential Current Outputs (SSM2118T) Low External Parts Count Low Cost Trimless Voltage Controlled Amplifiers SSM2018T/SSM2118T Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 REV. A a VC –IN +IN VG V1–G –IG –I1–G GAIN CORE G 1–G SSM-2018T VC –IN +IN G V1–G –IG –I1–G GAIN CORE G 1–G SSM-2118T OBSOLETE
REV. A–2– SSM1018T/SSM2118T–SPECIFICATIONS ELECTRICAL SPECIFICATIONS Parameter Conditions Min Typ Max Units AUDIO PERFORMANCE1 Noise V IN = GND, 20 kHz Bandwidth –95 –93 dBu Headroom Clip Point = 1% THD+N +22 dBu Total Harmonic Distortion plus Noise 2nd and 3rd Harmonics Only (+25 °C to +85°C) A V = 0 dB, VIN = +10 dBu 0.006 0.025 % AV = +20 dB, VIN = –10 dBu 0.013 0.04 % AV = –20 dB, VIN = +10 dBu2 0.013 0.04 % INPUT AMPLIFIER Bias Current V CM = 0 V 0.25 1 µA Offset Voltage V CM = 0 V 1 15 mV Offset Current V CM = 0 V 10 100 nA Input Impedance 4M Ω Common-Mode Range ± 13 V Gain Bandwidth VCA Configuration 0.7 MHz VCP Configuration 14 MHz Slew Rate 5V / µs OUTPUT AMPLIFIER (SSM2018T) Offset Voltage V IN = 0 V, VC = +4 V 1.0 15 mV Output Voltage Swing I OUT = 1.5 mA Positive +10 +13 V Negative –10 –14 V Minimum Load Resistance For Full Output Swing 9 k Ω CONTROL PORT Bias Current 0.36 1 µA Input Impedance 1M Ω Gain Constant Device Powered in Socket > 60 sec –30 mV/dB Gain Constant Temperature Coefficient –3500 ppm/ °C Control Feedthrough 0 dB to –40 dB Gain Range ± 1 ± 4m V Maximum Attenuation V C = +4 V 100 dB POWER SUPPLIES Supply Voltage Range ± 5 ± 18 V Supply Current 11 15 mA Power Supply Rejection Ratio 80 dB NOTES 1SSM2118T tested and characterized using OP275 as current-to-voltage converter, see figure next page. 2Guaranteed by characterization data and testing at A V = 0 dB. Specifications subject to change without notice. [VS = ±15 V, AV = 0 dB, RL = 100 kΩ , f = 1 kHz, 0 dBu = 0.775 V rms, simple VCA application circuit with 18 k Ω resistors, –V IN floating, and Class AB gain core bias (R B = 150 kΩ ), –40 °C < TA < +85°C, unless otherwise noted. Typical specifications apply at T A = +25°C.] OBSOLETE
REV. A –3– SSM2018T/SSM2118T ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage THERMAL CHARACTERISTICS Thermal Resistance2 16-Pin Plastic DIP 16-Pin SOIC TRANSISTOR COUNT Number of Transistors ESD RATINGS 1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maxi- mum rating conditions for extended periods may affect device reliability. 2θJA is specified for worst-case conditions, i.e., θJA is specified for device in socket for P-DIP and device soldered in circuit board for SOIC package. ORDERING GUIDE Model Temperature Range Package Option* SSM2018TP –40 °C to +85°C N-16 SSM2018TS –40 °C to +85°C R-16 SSM2118TP –40 °C to +85°C N-16 SSM2118TS –40 °C to +85°C R-16 *N = Plastic DIP; R = SOL. PIN CONFIGURATIONS 16-Lead Plastic DIP and SOL 16-Lead Plastic DIP and SOL +I1–G V+ BAL COMP 1 +IN –IN MODE VC –I1–G –IG VG GND COMP 2 COMP 3 TOP VIEW (Not to Scale) SSM2018T V1–G +I1–G V+BAL COMP 1 +IN –IN MODE VC –I1–G GND COMP 2 COMP 3 TOP VIEW (Not to Scale) SSM2118T V1–G –IG +IG SSM2018T Typical Application Circuit SSM2118T Typical Application Circuit 1mF 18k VIN+ 150k A1 10k 10k 18k 18k 500k 50pF VOUT GLOBAL SYMMETRY TRIM FROM ADDITIONAL SSM2118Ts 1mF 18k VIN– 47pF 1mF 3k VCONTROL 50pF* 470k OPTIONAL TRIM 47k 47k A1, A2: OP275 SSM2118T *FOR MORE THAN 2 SSM2118Ts WARNING! ESD SENSITIVE DEVICE CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SSM2018T/SSM2118T features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. V+1mF 150k 18k 18k VIN+ 1mF 18k VIN– 47pF 1mF 50pF VCONTROL3k VOUT V–1 SSM2018T OBSOLETE
0.001 THD + N – %
Figure 1. SSM2018T THD + N Frequency (80 kHz Low-Pass
300 UNITS
Figure 2. SSM2018T Distortion Distribution Figure 3. SSM2018T THD + N vs. Amplitude (Gain = 0 dB, Figure 4. SSM2018T THD + N vs. Amplitude Figure 5. SSM2018T THD + N vs. Gain (f IN = 1 kHz; Figure 6. SSM2018T THD + N vs. Supply Voltage
Figure 13. SSM2018T Gain vs. Frequency Figure 14. SSM2118T THD + N Frequency (80 kHz Figure 15. SSM2118T Distortion Distribution Figure 16. SSM2118T THD + N vs. Amplitude Figure 17. SSM2118T THD + N vs. Amplitude Figure 18. SSM2118T THD + N vs. Gain (f IN = 1 kHz;
Figure 25. SSM2118T Gain vs. Frequency Figure 26. SSM2018T and SSM2118T Distortion vs. Figure 27. SSM2018T and SSM2118T Output Noise vs. Figure 28. SSM2018T Control Feedthrough Distribution Figure 29. SSM2018T and SSM2118T Control Figure 30. SSM2018T and SSM2118T Control
VCA circuit or the OVCE circuit, COMP3 should be left open. transistor via the control voltage, the compensation is changed. additional output amplifier used in the OVCE configuration. results in a –28.8 mV/dB control law at room temperature. Figure 40. SSM2118T Detailed Functional Diagram
Dimensions shown in inches and (mm). G, this causes V1-G to attenuate (to keep the average the same). On the other hand, when V G is attenuated, V1-G is amplified. in this data sheet where Pin 9 is grounded. Figure 48. Basic VCP Connection