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Technical content
- General description The GreenChip is the latest generation of green Switched Mode Power Supply (SMPS) controller ICs. The SSL8516BT combines a controller for Power Factor Correction (PFC) and a flyback controller. Its high level of integration enables cost-effective LED lighting application power supply design using a very low number of external components. The PFC operates in Quasi-Resonant (QR) or Discontinuous Conduction Mode (DCM), with valley switching. The specially built-in green functions provide high efficiency at all power levels. At high power levels, the flyback operates in QR mode or DCM with valley detection. At medium power levels, the flyback controller switches to Frequency Reduction (FR) mode and limits the peak current to an adjustable minimum value. In low-power mode, the PFC switches off to maintain high efficiency. At very low power levels, when the flyback switching frequency drops to below 25 kHz, the flyback converter switches to burst mode. During the non-switching phase of the burst mode, the internal IC supply current is minimized to optimize efficiency further. Valley switching is used in all operating modes. The advanced burst mode ensures high efficiency at low power and good standby power performance while minimizing audible transformer noise. The SSL8516BT is a Multi-Chip Module (MCM), containing two chips. The proprietary high-voltage BCD800 process makes direct start-up possible from the rectified universal mains voltage in an effective and green way. The second low voltage Silicon-On-Insulator (SOI) is used for accurate, high-speed protection functions and control. The SSL8516BT enables easy design of highly efficient and reliable LED lighting application power supplies between 25 W and 300 W. LED drivers in particular benefit from the high level of integration. The IC meets the lighting class C requirements on mains current harmonics as specified by IEC 61000-3-2 over a wide input voltage range and a wide output power range. Remark: All values in this document are typical values unless otherwise stated. SSL8516BT Greenchip PFC and flyback controller Rev. 1 — 26 May 2015 Product data sheet
Product data sheet Rev. 1 — 26 May 2015 2 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller 2. Features and benefits
2.1 Distinctive features
Integrated PFC and flyback controller Universal mains supply operation between 90 V (AC) to 305 V (AC) Fixed boost PFC with accurate maximum output voltage (NXP Semiconductors patented) High level of integration, results in cost-effective designs with very low external component counts Adjustable PFC switch off delay External PFC switch on and switch off override Accurate PFC switch on and switch off control (NXP Semiconductors patents: EP2566024A1, US20130057170, CN102969909 A)
2.2 Green features
On-chip start-up current source Reduced IC supply current during burst mode Power-down functionality for very low standby power
2.3 PFC green features
Valley/Zero-Voltage Switching (ZVS) for minimum switching losses (NXP Semiconductors patented) Frequency limitation reduces switching losses PFC switched off when a low-load is detected at the flyback output
2.4 Flyback green features
Valley switching for minimum switching losses (NXP Semiconductors patented) Frequency reduction with adjustable minimum peak current at low-power operation maintains high-efficiency at low output power levels Burst mode operation at very low-power levels for high-efficiency operation
2.5 Protection features
Safe restart mode for system fault conditions Continuous mode protection using demagnetization detection for both converters (NXP Semiconductors patented) UnderVoltage Protection (UVP) (foldback during overload) Accurate OverVoltage Protection (OVP) for both converters (adjustable for flyback converter) Mains voltage independent OverPower Protection (OPP) Open control loop protection for both converters. The open-loop protection on the flyback converter is safe restart OverTemperature Protection (OTP) Low and adjustable OverCurrent Protection (OCP) trip level for both converters
AC-DC offline switch mode power solutions from 25 W to 300 W. Table 1. Ordering information
6.1 Pinning
6.2 Pin description
Table 2. Pin description
Product data sheet Rev. 1 — 26 May 2015 5 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller 7. Functional description
7.1 General control
The SSL8516BT contains a power factor correction circuit controller and a flyback circuit controller. A typical configuration is shown in Figure 3.
7.1.1 Start-up and UnderVoltage LockOut (UVLO)
Initially, the capacitor on the VCC pin is charged from the high-voltage mains using the HV pin. When VCC is less than Vtrip, the charge current is Ich(low). This low current protects the IC if the VCC pin is shorted to ground. To ensure a short start-up time, the charge current above the Vtrip level is increased to Ich(high), until VCC reaches Vstartup. Except during start-up, when VCC is between Vth(UVLO) and Vstartup, the charge current becomes Ich(low) to ensure a low safe restart duty cycle during fault conditions. When VCC is lowered to 2 V, the IC is reset. During the next start-up, the charge current between Vth(UVLO) and Vstartup is Ich(high). (1) The HV pin can either be connected to the center tap of the flyback transformer or to the drain of MOSFET S2. Fig 3. A typical SSL8516BT configuration DDD 5 & &9&& & 5 &7+' 5$8;5 9PDLQV 3)&&203 3)&$8; 9,16(16( )%&75/ )%$8; )%6(16( 9&& /$7&+ *1' 3)&7,0(5 3)&'5,9(5 3)&6(16( 926(16( )%'5,9(5 56(16( 5&203 &287 /2$' 566 5'59 &66 5'59 5)%$8; 56(16( 56 566 &66 5 & EXON
Product data sheet Rev. 1 — 26 May 2015 6 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller The control logic activates the internal circuitry and switches off the HV charge current when VCC passes the Vstartup level. First, the LATCH pin current source is activated and the soft-start capacitors on the PFCSENSE and FBSENSE pins are charged. Also the clamp circuit on the PFCCOMP pin is activated. The PFC circuit is activated when the following conditions are met:
- the LATCH pin voltage exceeds the Ven(LATCH) voltage
- the PFCCOMP pin charging current drops below the absolute value of the Ien(PFCCOMP) current
- the soft-start capacitor on the PFCSENSE pin is charged If the soft-start capacitor on the FBSENSE pin is charged, the flyback converter is activated. The flyback converter output voltage is then regulated to its nominal output voltage. The auxiliary winding of the flyback converter takes over the IC supply (see Figure 4 If during start-up, the LATCH pin does not reach the Ven(LATCH) level before VCC reaches Vth(UVLO), the LATCH pin output is deactivated. The charge current is switched on again. When the flyback converter is started, VFBCTRL is monitored. If the output voltage does not reach its intended regulation level within a specified time, VFBCTRL reaches the Vto(FBCTRL) level. An error is then assumed and a safe restart is initiated. When one of the safe restart or latched protection functions are triggered, both converters stop switching and the VCC voltage drops to Vth(UVLO). A latched protection recharges capacitor CVCC using Ich(low) from the HV pin, but does not restart the converters. To provide safe restart protection, the capacitor is recharged using Ich(low) from the HV pin and the device restarts (see Figure 1). If OVP is triggered on the PFC circuit (VVOSENSE >V OVP(VOSENSE)), the PFC controller stops switching until the VVOSENSE < VOVP(VOSENSE). If a mains UVP is detected, VVINSENSE <V stop(VINSENSE), the PFC controller stops switching until VVINSENSE >V start(VINSENSE) again. OVP and UVP of the PFC circuit do not disable flyback controller switching. When the VCC pin voltage drops under the UVLO level, both controllers stop switching and enter safe restart mode. In the safe restart mode, the VCC pin capacitor is recharged using Ich(low) from the HV pin. At very low burst mode repetition rates, VCC can drop to below the UVLO level. The UVLO protection feature Vprot(UVLO) prevents the decrease when the IC is in burst mode.
Product data sheet Rev. 1 — 26 May 2015 7 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.1.2 Power-down mode
The power-down mode can be activated for very low standby power applications by pulling the VVINSENSE < Vth(pd) level. The SSL8516BT stops switching and safe restart protection is activated. The high-voltage start-up current source is also disabled during power-down and the SSL8516BT does not restart until VVINSENSE is raised again. During Power-down mode, all internal circuitry is disabled except for a voltage detection circuit on the VINSENSE pin. This circuit is supplied by the HV pin and draws 12 A from the HV pin for biasing. The protection signal resembles an imaginary protection trigger. Fig 4. Start-up sequence, normal operation and restart sequence 9&& /$7&+ 3527(&7,21 3)&6(16( 3)&'5,9(5 )%6(16( )%'5,9(5 )%&75/ 926(16( FKDUJLQJ9&& FDSDFLWRU VWDUWLQJ FRQYHUWHUV QRUPDO RSHUDWLRQ SURWHFWLRQ UHVWDUW VRIWVWDUW VRIWVWDUW ,+9 9VWDUW 9,16(16( 9WR )%&75/ 9VWDUWXS 9WK 9WULS 9HQ /$7&+ 9WK VWDUW 926(16( 9,16(16( DDD 3)&&203 9HQ 3)&&203
Product data sheet Rev. 1 — 26 May 2015 8 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.1.3 Supply management
All internal reference voltages are derived from a temperature compensated and trimmed on-chip band gap circuit. Internal reference currents are derived from a temperature compensated and trimmed on-chip current reference circuit.
7.1.4 Latch input
The LATCH pin is a general-purpose input pin which is used to switch off both converters. The pin sources a current IO(LATCH) of 30.5 A. Switching of both converters is stopped when VLATCH is < 494 mV. A latched protection is triggered. It can be reset by removing the voltage from both the VCC and HV pins or by the fast latch reset function (see Section 7.1.5). At initial start-up, switching is prevented until the capacitor on the LATCH pin is charged above 582 mV. No internal filtering is performed on this pin. An internal 1.75 V clamp protects the pin from excessive voltages.
7.1.5 Fast latch reset
In a typical application, the mains can be interrupted briefly to reset the latched protection. The bulk capacitor C bulk does not have to discharge for this latched protection to reset. When the VINSENSE voltage drops below 750 mV and is then raised to 860 mV, the latched protection is reset. The latched protection is also reset by removing both the voltage on the V CC and HV pins.
7.1.6 Overtemperature protection
An accurate internal temperature protection is provided in the IC. When the junction temperature exceeds the thermal shut-down temperature, the IC stops switching. While OTP is active, the capacitor CVCC is not recharged from the HV mains. If the VCC supply voltage is not sufficient, the OTP circuit is supplied from the HV pin. OTP is a safe restart protection.
7.2 Power factor correction circuit
The Power Factor Correction (PFC) circuit operates in Quasi-Resonant (QR) or Discontinuous Conduction Mode (DCM) with valley switching. The next primary stroke is only started when the previous secondary stroke has ended and the voltage across the PFC MOSFET has reached the minimum value. VPFCAUX is used to detect transformer demagnetization and the minimum voltage across the external PFC MOSFET switch. 7.2.1 t on control (PFCCOMP pin) The power factor correction circuit is operated in ton control. The resulting mains harmonic reduction is well within the class-C lighting requirements. VPFCCOMP determines the on-time of the PFC. The VVOSENSE is the transconductance amplifier input which outputs current to the PFCCOMP pin. The regulation VVOSENSE = 2.5 V. The network connected to the PFCCOMP pin and the transconductance amplifier determine the dynamic behavior of the PFC control.
Product data sheet Rev. 1 — 26 May 2015 9 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller Operating near the PFC OVP level causes the PFC stage on-time to decrease rapidly to zero. To reduce the response time, in case of load variation, the PFCCOMP pin is clamped to a minimum level of 1.19 V during PFC operation. Clamping prevents the on-time increasing too much and improves the PFC response time when the load decreases again.
7.2.2 Valley switching and demagnetization (PFCAUX pin)
The PFC MOSFET is switched on after the transformer is demagnetized. Internal circuitry connected to the PFCAUX pin detects the end of the secondary stroke. It also detects the voltage across the PFC MOSFET. To reduce switching losses and ElectroMagnetic Interference (EMI), the next stroke is started when the voltage across the PFC MOSFET is at its minimum (valley switching). If a demagnetization signal is not detected on the PFCAUX pin, the controller generates a Zero-Current Signal (ZCS) 48 s after the last PFC MOSFET gate signal. If valley signal is not detected on the PFCAUX pin, the controller generates a valley signal 4.2 s after demagnetization is detected. To protect the internal circuitry during, for example, lightning events, add a 5 k series resistor to the PFCAUX pin. To prevent incorrect switching due to external interference, place the resistor close to the IC on the PCB.
7.2.3 Frequency limitation
To optimize the transformer and minimize switching losses, the switching frequency is limited to fsw(PFC)max. If the frequency for quasi-resonant operation is above the fsw(PFC)max limit, the system switches to DCM. The PFC MOSFET is only switched on at a minimum voltage across the switch (valley switching).
7.2.4 Mains voltage compensation (VINSENSE pin)
The equation for the transfer function of a power factor corrector contains the square of the mains input voltage. In a typical application, it results in a low bandwidth for low mains input voltages. To compensate for the influence of the mains input voltage, the SSL8516BT contains a correction circuit. The average input voltage is measured using the VINSENSE pin and the information is fed to an internal compensation circuit. Using this compensation, it is possible to keep the regulation loop bandwidth constant over the mains input range. This feature gives a fast transient response on load steps while complying with class-C MHR requirements. In a typical application, a resistor and two capacitors connected to the PFCCOMP pin set the regulation loop bandwidth.
Product data sheet Rev. 1 — 26 May 2015 10 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.2.5 Soft-start (PFCSENSE pin)
To prevent audible transformer noise at start-up or during hiccup, the soft-start function slowly increases the transformer peak current. To implement a soft-start function, place a capacitor CSS1 in parallel with resistor RSS1 (see Figure 5). An internal current source charges the capacitor to: (1) The voltage is limited to Vstart(soft)PFC. The start level and time constant of the increasing primary current level is externally adjusted by changing the RSS1 and CSS1 values. (2) The charging current Istart(soft)PFC flows while the PFCSENSE pin voltage is < 0.5 V. If VPFCSENSE exceeds 0.5 V, the soft-start current source starts limiting current Istart(soft)PFC. When the PFC starts switching, the Istart(soft)PFC current source is switched off; see Figure 5.
7.2.6 PFC switch-on/switch-off control
When the flyback converter output power (see Section 7.3) is low, the flyback converter switches to FR mode. When the switching frequency of the flyback in FR mode < fsw(fb)swoff(PFC) (53 kHz), the PFC circuit is switched off to maintain high efficiency. To delay the PFC switching off, connect a capacitor to the PFCTIMER pin (see Section 7.2.7). During low-power mode operation and start-up (when PFC is disabled, e.g. at no-load), the PFCCOMP pin is clamped to a minimum voltage of 3.32 V or 1.18 V and a maximum voltage of 3.75 V. The minimum clamp voltage depends on V VINSENSE. This voltage limits the maximum power that is delivered when the PFC switches on again. The upper clamp voltage ensures that the PFC returns from low-power mode to its normal regulation point in a limited time. In FR mode, when the flyback converter switching frequency exceeds fsw(fb)swon(PFC) (73 kHz), the PFC circuit is switched on. If the flyback converter duty cycle is > 50 % or VFBCTRL is > 3.75 V, the PFC circuit is also switched on. Fig 5. Soft start of the PFC VPFCSENSE Istart soft PFC RSS1= start soft PFC 3R SS1 CSS1 = 62)767$57 62)76723 &21752/ 2&3 3)&6(16( ,VWDUW VRIW 3)& $6 566 &66 56(16( DDD
Product data sheet Rev. 1 — 26 May 2015 11 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.2.7 PFC switch off delay (PFCTIMER pin)
When the flyback converter switching frequency in FR mode is < fsw(fb)swoff(PFC) (53 kHz), the IC then outputs a 4.7 A current to the PFCTIMER pin. When VPFCTIMER reaches 3 V, the PFC is switched off by performing a soft-stop. A switch discharges the PFCTIMER pin capacitor when the flyback controller operating frequency is > fsw(fb)swon(PFC) (73 kHz). At the same moment, the PFC stage is also switched on. To prevent that the PFC from switches off because of a dynamic load that leads to repetitive crossing of f sw(fb)swoff(PFC) and fsw(fb)swon(PFC), connect a capacitor to the PFCTIMER pin (see Section 7.2.7). A 1 nF minimum capacitor value is recommended to prevent noise influencing the PFC switch on/ switch off behavior. The PFCTIMER pin capacitor is also discharged when PFC is on and the flyback switching frequency is higher than 53 kHz. This feature prevents PFC on/off toggling during dynamic loads causing the flyback to operate repetitively near f sw(fb)swoff(PFC) and fsw(fb)swon(PFC). It is also possible to control PFC switch-on and switch off externally. When VPFCTIMER is driven below 1.03 V, the PFC stage is on. When the PFCTIMER pin voltage is driven above 4.4 V, the PFC stage is switched off. The external control overrides the PFC stage control by the flyback controller (see Figure 6 The PFCTIMER pin has an internal clamp circuit starting around 10 V with a current capability of 0.1 mA
7.2.8 Overcurrent protection (PFCSENSE pin)
The maximum peak current is limited cycle-by-cycle by sensing the voltage across an external sense resistor, RSENSE1, on the source of the external MOSFET. The voltage is measured using the PFCSENSE pin. Fig 6. PFC switch on and switch off using the PFCTIMER pin DDD $ORZSRZHU 3)&7,0(5 Nȍ ORZSRZHUGHOD\\ 3)&RQ
Product data sheet Rev. 1 — 26 May 2015 12 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.2.9 Mains undervoltage lockout/brownout protection (VINSENSE pin)
To prevent the PFC from operating at very low mains input voltages, VVINSENSE is sensed continuously. When VVINSENSE drops below the Vstop(VINSENSE) level, switching of the PFC is stopped.
7.2.10 Overvoltage protection (VOSENSE pin)
To prevent output overvoltage during load steps and mains transients, an overvoltage protection circuit is built in. When VVOSENSE exceeds the VOVP(VOSENSE) level, switching of the PFC circuit is prevented. Switching of the PFC restarts when the VOSENSE pin voltage drops below the VOVP(VOSENSE) level again. OVP is also triggered when the resistor between the VOSENSE pin and ground is open.
7.2.11 PFC open-loop protection (VOSENSE pin)
The PFC circuit does not start switching until the VVOSENSE pin is greater than the Vth(start)(VOSENSE) level. This feature protects the application from open-loop and VOSENSE short-circuit situations.
7.2.12 Driver (PFCDRIVER pin)
The driver circuit to the gate of the power MOSFET includes a current sourcing capability of 500 mA at 2 V on the PFCDRIVER pin. It also includes a current sink capability of 1.2 A at 10 V on the PFCDRIVER pin. These capabilities ensure fast switch-on and switch-off of the power MOSFET for efficient operation.
7.3 Flyback controller
The SSL8516BT includes a controller for a flyback converter. The flyback converter operates in quasi-resonant or discontinuous conduction mode or burst mode with valley switching. The auxiliary winding of the flyback transformer provides demagnetization detection and powers the IC after start-up.
7.3.1 Multimode operation
The SSL8516BT flyback controller can operate in several modes; see Figure 7.
Product data sheet Rev. 1 — 26 May 2015 13 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller At high output power the converter switches to quasi-resonant mode. The next converter stroke starts after demagnetization of the transformer and detection of the valley. In quasi-resonant mode, switching losses are minimized. This minimization is achieved by the converter only switching on when the voltage across the external MOSFET is at its minimum (see Section 7.3.2). Valley switching is active in all operating modes. To prevent high frequency operation at lower loads, the quasi-resonant operation switches to discontinuous mode operation with valley skipping. When the frequency limit is reached, the quasi-resonant operation changes to DCM with valley skipping. The frequency limit reduces the MOSFET switch-on losses and conducted EMI. At medium power levels, the controller enters Frequency Reduction (FR) mode. A Voltage Controlled Oscillator (VCO) controls the frequency. The minimum frequency in this mode is reduced to approximately 25 kHz. During frequency reduction mode, the primary peak current is kept at an adjustable minimum level to maintain a high efficiency. Valley switching is also active in this mode. At very low power and standby levels, for which the switching frequency drops to below 25 kHz, the converter enters the burst mode. In burst mode, the switching frequency is 36.5 kHz. The primary peak current is fixed in burst mode. In frequency reduction mode, the PFC controller switches off when the flyback switching frequency has dropped to below 53 kHz and VPFCTIMER has reached 3 V. The flyback maximum frequency changes linearly with the control VFBCTRL (see Figure 8). Hysteresis is added to ensure a stable PFC switch-on and switch-off. In no-load operation, the switching frequency is reduced to (almost) zero. Fig 7. Multimode operation flyback GLVFRQWLQXRXV ZLWKYDOOH\\ VZLWFKLQJ TXDVLUHVRQDQW IUHTXHQF\\ UHGXFWLRQ RXWSXWSRZHU IO\\EDFN VZLWFKLQJ IUHTXHQF\\ DDD 3)&RII 3)&RQ N+] N+] N+] N+] N+] ,SPLQ DGMXVW EXUVWPRGH
Product data sheet Rev. 1 — 26 May 2015 14 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.3.2 Valley switching (HV pin)
A new cycle starts when the external MOSFET is switched on. VFBSENSE and VFBCTRL determine the on-time. The MOSFET is then switched off and the secondary stroke starts (see Figure 9). After the secondary stroke, the drain voltage shows an oscillation with a frequency of approximately: (3) where Lp is the primary self-inductance of the flyback transformer and Cd is the capacitance on the drain node. When the secondary stroke ends and the internal oscillator voltage is high again, the circuit waits for the lowest drain voltage before starting a new primary stroke. Figure 9 shows the drain voltage, valley signal, secondary stroke signal and the internal oscillator signal. Valley switching allows high frequency operation because capacitive switching losses are reduced (see Equation 4 ). High frequency operation makes small and cost-effective magnetic components possible. (4) Fig 8. Flyback frequency control DDD 9)%&75/ 3)&RII 3)&RQ IO\\EDFN VZLWFKLQJ IUHTXHQF\\ IVZ IE PD[ EXUVWPRGH IUHTXHQF\\ )5PLQLPXP IUHTXHQF\\ )5 '&0 45 4XDVL5HVRQDQW '&0 'LVFRQWLQXRXV&RQGXFWLRQ0RGH )UHTXHQF\\5HGXFWLRQ %XUVW0RGH f 1 P 1 2--- Cd V2 f =
Product data sheet Rev. 1 — 26 May 2015 15 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.3.3 Current mode control (FBSENSE pin)
Current mode control is used for the flyback converter because of its good line regulation. The FBSENSE pin senses the primary current across an external resistor and compares it to an internal control voltage. The internal control voltage is proportional to VFBCTRL (see Figure 10). The FBSENSE pin outputs a current of 2.1 A. This current runs through the resistors from the FBSENSE pin to the sense resistor RSENSE2 and creates an offset voltage. Resistor RSS2 causes the offset voltage because RSENSE2 is relatively small. The minimum flyback peak current is adjusted using this offset voltage. Adjusting the minimum peak current level, changes the frequency reduction slope (see Figure 7). (1) Start of a new cycle at lowest drain voltage. (2) Start of a new cycle in a classical Pulse-Widt h Modulation (PWM) system without valley detection. Fig 9. Signals for valley switching GUDLQ VHFRQGDU\\ VWURNH DDD VHFRQGDU\\ ULQJLQJ SULPDU\\ VWURNH YDOOH\\ VHFRQGDU\\ VWURNH RVFLOODWRU
Product data sheet Rev. 1 — 26 May 2015 16 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.3.4 Demagnetization (FBAUX pin)
The system is always in QR or DCM. The internal oscillator does not start a new primary stroke until the previous secondary stroke has ended. Demagnetization features a cycle-by-cycle output short-circuit protection by immediately lowering the frequency (longer off-time) and reducing the power level. Demagnetization recognition is suppressed during the first tsup(xfmr_ring) time of 2.2 s. This suppression can be necessary at low output voltages, during start-up and in applications where the transformer has a large leakage inductance. If the FBAUX pin is open-circuit or not connected, a fault condition is assumed and the converter immediately stops. Operation restarts when the fault condition is removed.
7.3.5 Flyback control/time-out (FBCTRL pin)
The FBCTRL pin is connected to an internal voltage source of 7 V using an internal 13.2 k resistor. When VFBCTRL > 5.5 V, the resistor is disconnected. The pin is biased with a 29 A current. When VFBCTRL > 7.75 V, a fault is assumed, switching is stopped and a restart is made. If a capacitor and resistor are connected in series to the pin, a time-out function is created which protects against open control loop situations. See Figure 11 and Figure 12. The time-out function is disabled by connecting a resistor (200 k) to ground on the FBCTRL pin. If the pin is short-circuited to ground, switching of the flyback controller is stopped. Under normal operating conditions, the converter regulates the output voltage. V FBCTRL varies between 0.77 V at minimum output power and 4.9 V at maximum output power. Fig 10. Flyback part peak current control 9)%&75/ IO\\EDFN )5PRGH 3)&RII3)&RQ DDD 6(16(UHVLVWRU SHDNYROWDJH )%6(16( RIIVHWYROWDJH 9VHQVH IE PD[ EXUVWPRGH )%6(16( SHDNYROWDJH IO\\EDFN '&0RU45
Product data sheet Rev. 1 — 26 May 2015 17 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.3.6 Burst mode operation (FBCTRL pin)
The flyback controller enters the burst mode when the output power is very low and the switching frequency is < 25 kHz. In burst mode, the flyback converter switching frequency is 36.5 kHz. The minimum flyback sense voltage of 232 mV, in combination with an offset voltage (see Section 7.3.3), determines the peak current. A burst cycle starts when one of the following is made:
- VFBCTRL > 2.4 V
- VCC <V prot(UVLO). This voltage level is typically 0.8 V > Vth(UVLO) The burst cycle is stopped when VFBCTRL <0 . 7 7V . In burst mode, the internal IC supply current is reduced to improve the no-load and low-load input power. The burst mode is exited and normal operation resumes when the VFBCTRL >2 . 8V (see Figure 13). Fig 11. Time-out protection circuit Fig 12. SSL8516BT time-out protection (signals) and safe restart DDD )%&75/ Nȍ WLPHRXW DDD 9)%&75/ RXWSXW YROWDJH WDUJHWRXWSXW YROWDJHUHDFKHG ZLWKLQWLPHRXWWLPH UHVWDUWWDUJHWRXWSXW YROWDJHQRWUHDFKHG ZLWKLQWLPHRXWWLPH
Product data sheet Rev. 1 — 26 May 2015 18 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.3.7 Soft-start (FBSENSE pin)
To prevent audible transformer noise during start-up, the soft-start function slowly increases the transformer peak current. To implement the soft-start function, place a capacitor CSS2 in parallel with resistor RSS2 (see Figure 14). An internal current source charges the capacitor to: (5) with a maximum of 0.55 V. The start level and the time constant of the increasing primary current level can be adjusted externally by changing the values of RSS2 and CSS2. (6) The soft-start current Istart(soft)fb switches on when VCC reaches Vstartup. When the VFBSENSE reaches 0.55 V, the flyback converter starts switching. The charging current Istart(soft)fb flows when the VFBSENSE is < 0.55 V. If VFBSENSE exceeds 0.55 V, the soft-start current source starts limiting the current. After the flyback converter has started, the soft-start current source is switched off. When the IC is operating in the burst mode, the soft-start function is switched off. Fig 13. Burst mode operation DDD ORDG 9RXW )%&75/ IO\\EDFNDFWLYH EXUVWPRGH )%'5,9(5 N+] IO\\EDFNIUHTX HQF\\ VI start soft fb RSS2= start soft fb 3R SS2 CSS2 =
Product data sheet Rev. 1 — 26 May 2015 19 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.3.8 Maximum on-time
The flyback controller limits the on-time of the external MOSFET to 38.5 s. When the on-time is longer than 38.5 s, the IC stops switching and enters the safe restart state.
7.3.9 Overvoltage protection (FBAUX pin)
An output OVP is implemented in the GreenChip series. In the SSL8516BT, the auxiliary voltage is sensed using the current flowing into the FBAUX pin during the secondary stroke. The auxiliary winding voltage is a well-defined replica of the output voltage. An internal filter averages voltage spikes. An internal up-down counter prevents false OVP detection which can occur during ESD or lightning events. The internal counter counts up by one when the output voltage exceeds the OVP trip level within one switching cycle. The internal counter counts down by two when the output voltage has not exceeded the OVP trip level in one switching cycle. When the counter has reached six, the IC assumes a true overvoltage and triggers the safe start protection The demagnetization resistor, RFBAUX sets the output voltage Vo(OVP) at which the OVP function trips: (7) where Ns is the number of secondary windings and Naux is the number of auxiliary windings of the transformer. Current Iovp(FBAUX) is internally trimmed. Accurate OVP detection is made possible by adjusting the value of RFBAUX to the turns ratio of the transformer. Fig 14. Flyback soft-start DDD 62)767$57 &21752/ 2&3)%6(16( 566 &66 56(16( RFSOHYHO ,VWDUW VRIW IE $ VoO V P Ns Naux
Product data sheet Rev. 1 — 26 May 2015 20 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller
7.3.10 Overcurrent protection (FBSENSE pin)
The primary peak current in the transformer is measured accurately cycle-by-cycle using the external sense resistor RSENSE2. The OCP circuit limits VFBSENSE to a level set by VFBCTRL (see also Section 7.3.3). The OCP detection is suppressed during the leading-edge blanking period, tleb (equals ton(fb)min td(FBDRIVER)), to prevent false triggering due to switch-on spikes.
7.3.11 Overpower protection
During the flyback converter primary stroke, the flyback converter input voltage is measured by sensing the current that is drawn from the FBAUX pin. The current information is used to limit the maximum flyback converter peak current and is measured using the FBSENSE pin. The internal compensation is such, that a maximum output power is obtained which is almost independent of the PFC output voltage. The OPP curve is given in Figure 16.
7.3.12 Driver (FBDRIVER pin)
The driver circuit for the external power MOSFET gate includes a current sourcing capability of 500 mA at 2 V on the FBDRIVER pin. It also includes a current sink capability of 1.2 A at 10 V on the FBDRIVER pin. These capabilities ensure fast switch-on and switch-off of the power MOSFET for efficient operation. Fig 15. OCP leading-edge blanking WOHE 2&3OHYHO 9)%6(16( W DDD Fig 16. Overpower protection curve DDD ,)%$8; 9)%6(16(
[1] Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
Table 4. Thermal characteristics Table 5. Characteristics the IC; unless otherwise specified.
Table 5. Characteristics …continued the IC; unless otherwise specified.
start-up; lower clamp voltage. the IC; unless otherwise specified.
the IC; unless otherwise specified.
the IC; unless otherwise specified.
the IC; unless otherwise specified.
[1] A typical application with a compensation network on the PFCCOMP pin, such as the example in Figure 3. again, the low clamp level is active. the IC; unless otherwise specified.
Product data sheet Rev. 1 — 26 May 2015 29 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller 11. Application information An LED driver with the SSL8516BT consists of a PFC circuit and a flyback converter (see Figure 17). Capacitor CVCC buffers the IC supply voltage. The IC supply is charged from the high voltage rectified mains during start-up and the auxiliary winding of the flyback converter during operation. Sense resistors RSENSE1 and RSENSE2 convert the current through the MOSFETs S1 and S2 into a voltage on the PFCSENSE and FBSENSE pins. The RSENSE1 and RSENSE2 values define the maximum primary peak current in MOSFETs S1 and S2. In the example, the LATCH pin is connected to a Negative Temperature Coefficient (NTC) resistor. The protection is activated when the resistance drops below the value as calculated in Equation 8: (8) Capacitor CTIMEOUT is connected to the FBCTRL pin. RLOOP ensures that the time-out capacitor does not interfere with the flyback regulation control loop. RS1 and RS2 prevent that the soft-start capacitors CSS1 and CSS2 are charged during normal operation due to negative voltage spikes across the sense resistors. Resistor RAUX1 protects the IC from damage during lightning events. RS3 and RCOMP can be used to lower the PFC on/off power level. The minimum and maximum peak current ratio increase. So, the PFC switch-on and switch-off power level decreases. RDRV1 and RDRV2 prevent that the internal MOSET drivers are damaged due to, for example, power MOSFET avalanche. Depending on the drain voltage maximum rating of MOSFET S2, the HV pin of the IC can either be connected to the center tap of the flyback transformer or to the drain of MOSFET S2. Vprot LATCH IOL A T C H
Product data sheet Rev. 1 — 26 May 2015 30 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller (1) In the application, the HV pin of the IC can either be connect ed to the center tap of the flyback transformer or to the drain of MOSFET S2. Fig 17. SSL8516BT typical application diagram DDD 5 & &9&& & 5 &7+' 5$8;5 9PDLQV 3)&&203 3)&$8; 9,16(16( )%&75/ )%$8; )%6(16( 9&& /$7&+ *1' 3)&7,0(5 3)&'5,9(5 3)&6(16( 926(16( )%'5,9(5 56(16( 5&203 &287 /2$' 566 5'59 &66 5'59 5)%$8; 56(16( 56 566 &66 5 & EXON
Product data sheet Rev. 1 — 26 May 2015 31 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller 12. Package outline Fig 18. Package outline SOT109-1 (SO16) ș ES GHWDLO; H F Y 0 $ SLQLQGH[ 81,7 $ PD[ $ $ $ ES F ' H + ( / / S 4 =\\ZY ș 5()(5(1&(6287/,1( 9(56,21 (8523($1 ,(& -('(& -(,7$ PP LQFKHV R R ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG 627 ( 06 PP VFDOH SODVWLFVPDOORXWOLQHSDFNDJH OHDGV ERG\\ZLGWK PP 627
Table 6. Revision history
Product data sheet Rev. 1 — 26 May 2015 33 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller 14. Legal information
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[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
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14.3 Disclaimers
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NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. 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No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
Product data sheet Rev. 1 — 26 May 2015 34 of 35 NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. GreenChip — is a trademark of NXP Semiconductors N.V. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors SSL8516BT Greenchip PFC and flyback controller © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 May 2015 Document identifier: SSL8516BT Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 16. Contents 7.1.1 Start-up and UnderVoltage LockOut (UVLO) . . 5 7.2.1 t
7.2.2 Valley switchin g and demagnetization
7.2.4 Mains voltage compensation
7.2.9 Mains undervoltage lockout/brownout
7.2.11 PFC open-loop protection (VOSENSE pin) . . 12