SSF8N90A FAIRCHILD | Alldatasheet

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Avalanche Rugged Technology Rugged Gate Oxide Technology Lower Input Capacitance Improved Gate Charge Extended Safe Operating Area Lower Leakage Current : 25 µA (Max.) @ VDS = 900V Low RDS(ON) : 1.247 Ω (Typ.) Advanced Power MOSFET Thermal Resistance Junction-to-Case Junction-to-Ambient R θJC R θJA Ο C /W Characteristic Max. UnitsSymbol Typ.

FEATURES

Continuous Drain Current (TC=25 Ο Continuous Drain Current (TC=100 Ο Drain Current-Pulsed Gate-to-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (TC=25 Ο Linear Derating Factor Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8 “ from case for 5-seconds Characteristic Value UnitsSymbol IDM VGS EAS IAR EAR dv/dt ID PD TJ , TSTG TL A V mJ A mJ V/ns W Ο C A Ο C VDSS V TO-3PF 1.Gate 2. Drain 3. Source SSF8N90A BVDSS = 900 V RDS(on) = 1.6 Ω ID = 5.5 A 900 5.5 3.5 801 5.5 9.5 1.5 0.76 - 55 to +150 300 1.32 30 +_ ©1999 Fairchild Semiconductor Corporation Rev. B

Electrical Characteristics (TC=25 Ο C unless otherwise specified) Drain-Source Breakdown Voltage Breakdown Voltage Temp. Coeff. Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse CharacteristicSymbol Max. UnitsTyp.Min. Test Condition Static Drain-Source On-State Resistance Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain(“Miller”) Charge gfs Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd BVDSS ΔBV/ΔTJ VGS(th) RDS(on) IGSS IDSS V Ο C V nA µA Ω Ω pF ns nC VGS=0V,ID=250µA ID=250µA See Fig 7 VDS=5V,ID=250µA VGS=30V VGS=-30V VDS=900V VDS=720V,TC=125 Ο C VGS=10V,ID=2.75A * VDS=50V,ID=2.75A VDD=450V,ID=8A, RG=10Ω See Fig 13 VDS=720V,VGS=10V, ID=8A See Fig 6 & Fig 12 Drain-to-Source Leakage Current VGS=0V,VDS=25V,f =1MHz See Fig 5 Source-Drain Diode Ratings and Characteristics Continuous Source Current Pulsed-Source Current Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge IS ISM VSD trr Qrr CharacteristicSymbol Max. UnitsTyp.Min. Test Condition A V ns µC Integral reverse pn-diode in the MOSFET TJ=25 Ο C ,IS=5.5A,VGS=0V TJ=25 Ο C ,IF=8A diF/dt=100A/µs O4 O5 O5O4 SSF8N90A 900 2.0 1.06 185 122 14.9 43.5 3.5 100 -100 250 1.6 2690 215 255 123 5.0 2070 620 9.3 5.5 1.4 Notes ; Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature L=50mH, IAS=5.5A, VDD=50V, RG=27Ω , Starting TJ =25 Ο C ISD 8A, di/dt 170A/ µs, VDD BVDSS , Starting TJ =25 Ο C Pulse Test : Pulse Width = 250 µs, Duty Cycle 2% Essentially Independent of Operating Temperature

Fig 1. Output Characteristics Fig 2. Transfer Characteristics Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drain-Source Voltage Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Current SSF8N90A 10-1 100 101 10-1 100 101 @ Notes : 1. 250 µs Pulse Test 2. TC = 25 oC VGS Top : 1 5 V 1 0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V ID , Drain Current [A] VDS , Drain-Source Voltage [V] 2 4 6 8 1010-1 100 101 25 oC 150 oC - 55 oC @ Notes : 1. VGS = 0 V 2. VDS = 50 V 3. 250 µs Pulse Test ID , Drain Current [A] VGS , Gate-Source Voltage [V] 100 101 150 oC 25 oC @ Notes : 1. VGS = 0 V 2. 250 µs Pulse Test IDR , Reverse Drain Current [A] VSD , Source-Drain Voltage [V] 0 5 10 15 20 25 30 35 @ Note : TJ = 25 oC VGS = 20 V VGS = 10 V RDS(on) , [Ω ] Drain-Source On-Resistance ID , Drain Current [A] 100 1010 1000 2000 3000 Ciss= Cgs+ Cgd (Cds= shorted) Coss= Cds+ Cgd Crss= Cgd @ Notes : 1. VGS = 0 V 2. f = 1 MHzC rss C oss C iss Capacitance [pF] VDS , Drain-Source Voltage [V] 0 20 40 60 80 100 VDS = 720 V VDS = 450 V VDS = 180 V @ Notes : ID = 8.0 A VGS , Gate-Source Voltage [V] QG , Total Gate Charge [nC]

Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature Fig 11. Thermal Response PDM SSF8N90A -75 -50 -25 0 25 50 75 100 125 150 175 0.8 0.9 1.0 1.1 1.2 @ Notes : 1. VGS = 0 V 2. ID = 250 µA BVDSS , (Normalized) Drain-Source Breakdown Voltage TJ , Junction Temperature [oC] -75 -50 -25 0 25 50 75 100 125 150 175 0.0 0.5 1.0 1.5 2.0 2.5 3.0 @ Notes : 1. VGS = 10 V 2. ID = 4.0 A RDS(on) , (Normalized) Drain-Source On-Resistance TJ , Junction Temperature [oC] 25 50 75 100 125 150 6ID , Drain Current [A] Tc , Case Temperature [oC] 101 102 10310-2 10-1 100 101 102 100 µs DC 10 µs 1 ms 10 ms @ Notes : 1. TC = 25 oC 2. TJ = 150 oC 3. Single Pulse Operation in This Area is Limited by R DS(on) ID , Drain Current [A] VDS , Drain-Source Voltage [V] 10-5 10-4 10-3 10-2 10-1 100 10110-2 10-1 100 single pulse 0.2 0.1 0.01 0.02 0.05 D=0.5 @ Notes : 1. ZθJC (t)=1.32 oC/W Max. 2. Duty Factor, D=t1/t2 3. TJM-TC=PDM *ZθJC(t) Z θJC(t) , Thermal Response t1 , Square Wave Pulse Duration [sec]

Fig 12. Gate Charge Test Circuit & Waveform Fig 13. Resistive Switching Test Circuit & Waveforms Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms EAS = LL IAS 2----2 BVDSS -- VDD BVDSS Vin Vout 10% 90% td(on) tr t on t off td(off) tf Charge VGS 10V Qg Qgs Qgd Vary tp to obtain required peak ID 10V VDDC LL VDS ID RG t p DUT BVDSS t p VDD IAS VDS (t) ID (t) Time VDD ( 0.5 rated VDS ) 10V Vout Vin RL DUT RG 3mA VGS Current Sampling (IG) Resistor Current Sampling (ID) Resistor DUT VDS 300nF 50K¥Ø 200nF12V Same Type as DUT * Current Regulator * R1 R2 SSF8N90A

Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT VDS L I S DriverVGS RG Same Type as DUT VGS • dv/dt controlled by “RG

  • IS controlled by Duty Factor “D” VDD 10V VGS ( Driver ) I S ( DUT ) VDS ( DUT ) VDD Body Diode Forward Voltage Drop Vf IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width SSF8N90A

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