SSF7N60A

SSF7N60A FAIRCHILD | Alldatasheet

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FEATURES

• Avalanche Rugged Technology  Rugged Gate Oxide Technology  Lower Input Capacitance  Improved Gate Charge  Extended Safe Operating Area  Lower Leakage Current: 25µA (Max.) @ V DS = 600V  Lower R DS(ON) : 0.977Ω (Typ.) ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Symbol Characteristics Value Units VDSS Drain-to-Source Voltage 600 V ID Continuous Drain Current (TC = 25°C) 5.4 A Continuous Drain Current (TC = 100°C) 3.4 IDM Drain Current-Pulsed 30 A VGS Gate-to-Source Voltage ±30 V EAS Single Pulsed Avalanche Energy 477 mJ IAR Avalanche Current 5.4 A EAR Repetitive Avalanche Energy 8.6 mJ dv/dt Peak Diode Recovery dv/dt 3.0 V/ns PD Total Power Dissipation (TC = 25°C) Linear Derating Factor 0.69 W W/°C TJ, TSTG Operating Junction and Storage Temperature Range −55 to +150 TL Maximum Lead Temp. for Soldering Purposes, 1/8” from case for 5-seconds 300 Symbol Characteristics Typ. Max. Units R θJC Junction-to-Case − 1.45 °C/W R θJA Junction-to-Ambient − 40 BV DSS = 600V R DS(ON) = 1.2Ω ID = 5.4A TO-3PF 1. Gate 2. Drain 3. Source N-CHANNEL POWER MOSFET SSF7N60A  1999 Fairchild Semiconductor Corporation REV. B x y x x z

SSF7N60A N-CHANNEL POWER MOSFET ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified) SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Notes: x Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature y L=30mH, IAS =5.4A, VDD =50V, RG =27Ω , Starting TJ =25°C z ISD ≤ 7A, di/dt ≤ 120A/µs, VDD ≤ BV DSS , Starting TJ =25°C { Pulse Test: Pulse Width ≤ 250µs, Duty Cycle ≤ 2% | Essentially Independent of Operating Temperature Symbol Characteristics Min. Typ. Max. Units Test Conditions BV DSS Drain-Source Breakdown Voltage 600 −− VV GS =0V, ID =250µA ∆BV/∆TJ Breakdown Voltage Temp. Coeff. − 0.65 − V/°CI D =250µA, See Fig 7 VGS(th) Gate Threshold Voltage 2.0 − 4.0 V V DS =5V, ID =250µA IGSS Gate-Source Leakage, Forward −− 100 nA VGS =30V Gate-Source Leakage, Reverse −− − 100 V GS = −30V IDSS Drain-to-Source Leakage Current −− 25 µA VDS =600V −− 250 V DS =480V, TC =125°C R DS(on) Static Drain-Source On-State Resistance −− 1.2 Ω VGS =10V, ID =2.7A { gfs Forward Transconductance − 4.74 − SV DS =50V, ID =2.7A { C iss Input Capacitance − 1150 1500 pF VGS =0V, VDS =25V f=1MHz See Fig 5 C oss Output Capacitance − 130 150 C rss Reverse Transfer Capacitance − 53 62 td(on) Turn-On Delay Time − 18 45 ns VDD =300V, ID =7A R G =9.1Ω See Fig 13 { | tr Rise Time − 19 50 td(off) Turn-Off Delay Time − 72 155 tf Fall Time − 28 65 Q g Total Gate Charge − 49 65 nC VDS =480V, VGS =10V ID =7A See Fig 6 & Fig 12 { | Q gs Gate-Source Charge − 8.4 − Q gd Gate-Drain (Miller) Charge − 22.1 − Symbol Characteristics Min. Typ. Max. Units Test Conditions IS Continuous Source Current −− 5.4 A Integral reverse pn-diode in the MOSFETISM Pulsed-Source Current x −− 30 VSD Diode Forward Voltage { −− 1.4 V T J=25°C, IS=5.4A, VGS =0V Trr Reverse Recovery Time − 415 − ns TJ=25°C, IF=7A diF/dt=100A/µs {Q rr Reverse Recovery Charge − 3.8 −µ C

@ Notes : 1. 250 µs Pulse Test 2. TC = 25 oC VGS Top : 1 5 V 1 0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V ID , Drain Current [A] VDS , Drain-Source Voltage [V] 24681 010-1 100 101 25 oC 150 oC - 55 oC @ Notes : 1. VGS = 0 V 2. VDS = 50 V 3. 250 µs Pulse Test ID , Drain Current [A] VGS , Gate-Source Voltage [V] 0 5 10 15 20 25 300.0 0.5 1.0 1.5 2.0 2.5 @ Note : TJ = 25 oC VGS = 20 V VGS = 10 V RDS(on) , [Ω ] Drain-Source On-Resistance ID , Drain Current [A] 100 101 150 oC 25 oC @ Notes : 1. VGS = 0 V 2. 250 µs Pulse Test IDR , Reverse Drain Current [A] VSD , Source-Drain Voltage [V] 100 1010 500 1000 1500 2000 Ciss= Cgs+ Cgd ( Cds= shorted ) Coss= Cds+ Cgd Crss= Cgd @ Notes : 1. VGS = 0 V 2. f = 1 MHz C rss C oss C iss Capacitance [pF] VDS , Drain-Source Voltage [V] 01 02 03 04 05 00 VDS = 480 V VDS = 300 V VDS = 120 V @ Notes : ID = 7.0 A VGS , Gate-Source Voltage [V] QG , Total Gate Charge [nC] Fig 1. Output Characteristics Fig 2. Transfer Characteristics Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drain-Source Voltage Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Current N-CHANNEL POWER MOSFET SSF7N60A

SSF7N60A N-CHANNEL POWER MOSFET -75 -50 -25 0 25 50 75 100 125 150 1750.8 0.9 1.0 1.1 1.2 @ Notes : 1. VGS = 0 V 2. ID = 250 µA BVDSS , (Normalized) Drain-Source Breakdown Voltage TJ , Junction Temperature [oC] -75 -50 -25 0 25 50 75 100 125 150 1750.0 0.5 1.0 1.5 2.0 2.5 3.0 @ Notes : 1. VGS = 10 V 2. ID = 3.5 A RDS(on) , (Normalized) Drain-Source On-Resistance TJ , Junction Temperature [oC] 25 50 75 100 125 1500 6ID , Drain Current [A] Tc , Case Temperature [oC] 10-5 10-4 10-3 10-2 10-1 100 101 10-2 10-1 100 single pulse 0.2 0.1 0.01 0.02 0.05 D=0.5 @ Notes : 1. Zθ JC(t)=1.45 oC/W Max. 2. Duty Factor, D=t1/t2 3. TJM-TC=PDM*Zθ JC(t) Z θJC(t) , Thermal Response t1 , Square Wave Pulse Duration [sec] 100 101 102 10310-2 10-1 100 101 102 10 µs DC 100 µs 1 ms 10 ms @ Notes : 1. TC = 25 oC 2. TJ = 150 oC 3. Single Pulse Operation in This Area is Limited by R DS(on) ID , Drain Current [A] VDS , Drain-Source Voltage [V] Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature Fig 11. Thermal Response PDM

Fig 12. Gate Charge Test Circuit & Waveform Fig 13. Resistive Switching Test Circuit & Waveforms Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms EAS =L L IAS 2----2 BV DSS -- VDD BV DSS V in V out 10% 90% td(on) tr t on t off td(off) tf Charge V GS 10V Q g Q gs Q gd Vary tp to obtain required peak ID 10V V DDC LL V DS ID R G t p DUT BV DSS t p V DD IAS V DS (t) ID (t) Time V DD ( 0.5 rated VDS ) 10V V out V in R L DUT R G 3mA V GS Current Sampling (IG ) Resistor Current Sampling (ID ) Resistor DUT V DS 300nF 50K /G00 200nF12V Same Type as DUT Current Regulator R 1 R 2 N-CHANNEL POWER MOSFET SSF7N60A

SSF7N60A N-CHANNEL POWER MOSFET Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT V DS L I S DriverV GS R G Same Type as DUT V GS • dv/dt controlled by /G01G  IS controlled by Duty Factor /G02? V DD 10V V GS ( Driver ) I S ( DUT ) V DS ( DUT ) V DD Body Diode Forward Voltage Drop V f IFM , Body Diode Forward Current Body Diode Reverse Current IRM Body Diode Recovery dv/dt di/dt D = Gate Pulse Width

August 1999, Rev B 26.50 –0.20 4.50 –0.20 10° 16.50 –0.20 22.00 –0.20 23.00 –0.20 1.50 –0.20 14.50 –0.20 2.00 –0.20 2.00 –0.20 2.00 –0.20 0.85 –0.03 2.00 –0.20 5.50 –0.20 3.00 –0.20 (1.50) 3.30 –0.20 2.00 –0.20 4.00 –0.20 2.50 –0.20 14.80 –0.20 3.30 –0.20 2.00 –0.20 5.50 –0.20 0.75+0.20 –0.10 0.90+0.20 –0.10 5.45TYP [5.45 –0.30] 5.45TYP [5.45 –0.30] TO-3PF (FS PKG CODE AG)

ACEx™ CoolFET™ CROSSVOLT™ E 2CMOS TM FACT™ FACT Quiet Series™ FAST FASTr™ GTO™ HiSeC™ The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Preliminary No Identification Needed Obsolete This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Formative or In Design First Production Full Production Not In Production DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. TinyLogic™ UHC™ VCX™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8