SSEPAA5-02N

SSEPAA5-02N SSC | Alldatasheet

Document overview

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Technical content

Low Capacitance ESD Protection Array 11/08/2007 Rev.1.00 www.SiliconStandard.com 1 For High Speed Data InterfacesFeatures z ESD Protect for 2 high-speed I/O channels z Provide ESD protection for each channel to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (Lightning) 12A (8/20μs) z 5V operating voltage z Low capacitance : 2pF typical z Fast turn-on and Low clamping voltage z Array of surge rated diodes with internal equivalent TVS diode z Small package saves board space z Solid-state silicon-avalanche and active circuit triggering technology

Applications

z USB2.0 Power and Data lines protection z Notebook and PC Computers z Monitors and Flat Panel Displays z IEEE 1394 Firewire Ports z Video Graphics Cards z SIM ports

Description

SSEPAA5-02N is a high performance design which includes surge rated diode arrays to protect high speed dat a interfaces. The SSEPAA5-02N has been specifically designed to protect sensitive components, which are connected to data and transmission lines, from over-voltage caused by Electrostatic Discharging (ESD), Electrical Fast Transients (EFT), and Lightning. SSEPAA5-02N is a unique design which includes surge rated, low capacitance steering diodes and a unique design of clamping cell which is an equivalent TVS diode in a single package. During transient conditions, the steering diodes direct the transient to either the power supply line or to the ground line. The internal unique design of clamping cell prevents over-voltage on the power line, protecting any downstream components. SSEPAA5-02N may be used to meet the ESD immunity requirements of IEC 61000-4-2, Level 4 (± 15kV air, ±8kV contact discharge). Circuit Diagram 2 3 Pin Conf uration ig 4 3 1 2 VDD I/O 2 I/O 1GND JEDEC SOT143-4L (Top View) SSEPAA5-02N

11/08/2007 Rev.1.00 www.SiliconStandard.com 2 SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER PARAMETER RATING UNITS Peak Pulse Current (tp =8/20μs) IPP 13 A Operating Supply Voltage (VDD-GND) VDC 6 V ESD per IEC 61000-4-2 (Air) ESD per IEC 61000-4-2 (Contact) VESD 24 kV Lead Soldering Temperature TSOL 260 (10 sec.) oC Operating Temperature TOP -55 to +125 oC Storage Temperature TSTO -55 to +150 oC DC Voltage at any I/O pin VIO (GND – 0.5) to (VDD + 0.5) V

ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Reverse Stand-Off Voltage VRWM Pin 4 to pin 1, T=25 oC 5 V Reverse Leakage Current ILeak VRWM = 5V, T=25 oC, Pin 4 to pin 1 5 μA Channel Leakage Current ICH_Leak VPin 4 = 5V, VPin 1 = 0V, T=25 oC 1 μA Reverse Breakdown Voltage VBV IBV = 1mA, T=25 oC Pin 4 to Pin 1 6.1 V Forward Voltage VF IF = 15mA, T=25 oC Pin1 to Pin 4 0.7 1 V Clamping Voltage VCL IPP=5A, tp=8/20μs, T=25 oC Any Channel pin to Ground 8 9 V ESD Holding Voltage Vhold IEC 61000-4-2, +6kV, T=25 oC, Contact mode (Any Channel pin to Ground). 13.5 V Channel Input Capacitance CIN Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC, Any Channel pin to Ground 2 3 pF Channel to Channel Input Capacitance CCROSS Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC , Between Channel pins 0.08 0.15 pF Variation of Channel Input Capacitance C△ IN Vpin5 = 5V, Vpin2 = 0V, VIN = 2.5V, f = 1MHz, T=25 oC , Channel_x pin to Ground - Channel_y pin to Ground 0.03 0.06 pF SSEPAA5-02N

11/08/2007 Rev.1.00 www.SiliconStandard.com 3 Typical Characteristics Power Derating Curve Ambient Temperature, TA (oC) 0 255 07 5 100 125 150 % of Rated Power or IPP 100 110 Peak pulse Current (A) 45678 9 10 11 12 13 Clamping Voltage (V) Clamping Voltage vs. Peak Pulse Current Waveform Parameters: tr=8μs td=20μs I/O pin to GND pin Peak pulse Current (A) 4 567 89 10 11 12 13 Forward Voltage (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Forward Voltage vs. Forward Current Waveform Parameters: tr=8μs td=20μsI/O pin to GND pin Input Voltage (V) 0 123 45 Input Capacitance (pF) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Typical Variation of CIN vs. VIN VDD = 5V, GND = 0V, f = 1MHz, T=25 oC, Temperature (oC) 20 40 60 80 100 120 Input Capacitance (pF) 1.0 1.5 2.0 2.5 3.0 Typical Variation of CIN vs. Temp VDD = 5V, GND = 0V, VIN = 2.5V, f = 1MHz, Insertion Loss S21 Frequency (Hz) 1e+6 1e+7 1e+8 1e+9 S21 (dB) -15 -10 START 0.3MHz STOP 1000MHz Transmission Line Pulsing (TLP) Measurement Transmission Line Pulsing (TLP) Voltage (V) 02 468 10 12 14 Transmission Line Pulsing (TLP) Current (A) V_pulse 100ns Pulse from a transmission l ine DUT TLP_I TLP_V I/O to GND SSEPAA5-02N

11/08/2007 Rev.1.00 www.SiliconStandard.com 4 SSEPAA5-02N Applications Information A. Design Considerations The ESD protection scheme for system I/O connector is shown in the Fig. 1. I n Fig. 1, th e diodes D1 and D2 are general used to prote ct data line from ESD stre ss pulse. If the power-rail ESD clamping circuit is not placed between VDD and GND rails, the po sitive pulse ESD curre nt (IESD1) will p ass through the ESD current p ath1. Thus, the ESD clamping voltage VCL of data line can be described as follow: VCL = Fwd voltage drop of D1 + supply voltage of VDD rail + L1 × d(IESD1)/dt + L2 × d(IESD1)/dt Where L1 is the parasitic inductance of data line, and L2 is the parasitic inductance of VDD rail. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 cont act discharg e per the IE C61000-4-2 standard results in a current pulse that rises from zero to 30 A in 1ns. Here d(I ESD1)/dt can b e approximated by ΔIESD1/Δt, or 30/(1x10-9). So just 10nH of total parasitic inductance (L1 and L2 combined) will lead to over 300V increment in VCL! Besides, the ESD pulse current which is directed int o the VDD rail ma y potentially damage an y compone nts that are attached to that rail. Moreover, it is common for the forward voltage drop of discret e diodes to exceed th e damage threshold of the protected IC. This is due to the relatively small j unction are a of typical discrete co mponents. Of course, the discrete diode is also possible t o be destroyed due to its power dissipation capability is exceeded. The SSEPAA5-02N has an integrated power-rail ESD clamp ed circuit between VDD and GND rails. It can succe ssfully overcome previous disadvantages. During an ESD event, the posit ive ESD pulse current (I ESD2) will b e directed thr ough the integrated power-rail ESD clamped circuit to GND rail (ESD current path2 ). The clamping voltage VCL on the data line is small and protected IC will not be damage d because power-rail ESD clamped circuit offer a low impedance path t o discharge ESD pulse current. Protected IC VDD r ail GND r ail data line L 2 VCL VESD power-rail ESD clamp ing circuit Vp ESD2I ESD1I SSEPAA5-02N ESD current path 1 (IESD1) ESD current path 2 (IESD2) Fig. 1 Application of positive ESD pulse between data line and GND rail.

11/08/2007 Rev.1.00 www.SiliconStandard.com 5 SSEPAA5-02N B. Device Connection The SSEPAA5-02N is de signed to protect two data lines and power rails fr om transient over-voltage (such as ESD stress pulse). Th e device connection of SSEPAA5-02N is shown in the Fig. 2. I n Fig. 2, the two protected dat a lines are connect ed to the ESD protection pins (pin 2 and pin3) of SSEPAA5-02N. The ground pin (pin1) of SSEPAA5-02N is a neg ative reference pin. This pin should be directly co nnected to the GND rail of PCB (Pri nted Circuit Board). To get minimum parasitic inductance, the path length should keep as short as possible. I n addition, t he power pin (pin 4) of SSEPAA5-02N is a positive reference pin. This pin should directly connect to the VDD rail of PCB. When pin 4 of SSEPAA5-02N is connected to the VDD rail, the le akage current of ESD protection pin of SSEPAA5-02N becomes very small. Because the pin 4 of SSEPAA5-02N is directly connected to VDD rail, the VDD rail also can be protected by the power-rail ESD clamp ed circuit (not shown) of SSEPAA5-02N. SSEPAA5-02N can provide protection for 2 I/O signal lines simultaneously. If the n umber of I/ O signal lines is less than 2, the unu sed I/O pin s can be simply left as NC pins. In some ca ses, systems are not allo wed to be reset or rest art af ter the ESD stress directly appl ying at the I/O-port connector . Under this situation, in order to enhance the sustainable ESD Level, a 0.1μF chip capacitor can be added between the VDD and GND rails. The place of this chip cap acitor should be as close as possible to the SSEPAA5-02N. VDD rail SSEPAA5-02N To Protected IC I/O 1 I/O 2 To I/O-port Connector I/O 2 I/O 1 GND rail data line data line *Optional 0.1μF Chip Cap. Fig. 2 Data lines and power rails connection of SSEPAA5-02N.

11/08/2007 Rev.1.00 www.SiliconStandard.com 6 SSEPAA5-02N C. Applications 1. Universal Serial Bus (USB) ESD Protection The SSEPAA5-02N can be used to protect the USB port on the monitors, computers, peripherals or port able systems. The ESD protection scheme for single USB ports is shown in Fig. 3 . In the Fig.3, the voltage bus (V BUS) of USB port is connected to the power pin (pin 4) of SSEPAA5-02N. Each data line (D+/D-) of USB port is connected to the ESD protection pin (pin2/pin3) of SSEPAA5-02N. When ESD voltage pulse appears on the data line, the ESD pulse current will be conducted by SSEPAA5-02N away from the USB controller chip. In addition, the ESD pu lse current also can be conducted by SSEPAA5-02N away from the USB controller chip when the ESD voltage pulse appears on the volt age bus (VBUS) of USB port . Therefore, the data lines (D+/D-) and voltage bus (VBUS) of t wo USB p orts are complement ally protected with an SSEPAA5-02N. USB Controller USB Port VBUS GND VBUS GND RT RT CT CT SSEPAA5-02N Fig. 3 ESD Protection scheme for single USB ports by using SSEPAA5-02N.

11/08/2007 Rev.1.00 www.SiliconStandard.com 7 2. Audio Interface ESD Protection For the audio interf ace, the Right/Lef t channels should be protected from the ESD stress. T he SSEPAA5-02N can be used for th e audio inter face ESD protection . The ES D protection scheme for audio interface is shown in the Fig. 4. In the Fig . 4, the Right and Le ft channels of audio con nector are connected t o ESD protection pins (su ch as pin 2 and pin 3) of SSEPAA5-02N. For the power pin (pin 4) of SSEPAA5-02N, it shou ld directly connect to t he VDD power supply . As well, for th e ground pin (pin 1) of SSEPA5-02N, it should directly connect to the Ground plate. When ESD volt age pulse appea rs on the Right/Left channel of audio connector , the ESD pulse current will be discharged by SSEPAA5-02N. Therefore, the Right/Lef t channels of audio chip are comp lementally protected with an SSEPAA5-02N. GND VDD1 Audio Chip Audio Conne ctor Right Channel Left Channel SSEPAA5-02N Fig. 4 ESD Protection scheme for audio interface by using SSEPAA5-02N. SSEPAA5-02N

11/08/2007 Rev.1.00 www.SiliconStandard.com 8 Mechanical Details SOT143-4L PACKAGE DIAGRAMS PACKAGE DIMENSIONS TOP VIEW SIDE VIEW END VIEW SSEPAA5-02N

11/08/2007 Rev.1.00 www.SiliconStandard.com 9 LAND LAYOUT A B DEF A A C Dimensions Index Millimeter Inches A 1.00 0.039 A1 1.40 0.055 B 1.40 0.055 C 1.92 0.076 C1 1.72 0.068 D 2.20 0.087 E 0.80 0.031 F 3.60 0.141 Notes: This LAND LA YOUT is for reference purposes only . Please c onsult your manufacturing p artners to ensure your company’s PCB design guidelines are met. MARKING CODE Part Number Marking Code SSEPAA5-02N 102XY 4 3 1 2 102X 102 = Device Code X = Date Code Y = Control Code SSEPAA5-02N

11/08/2007 Rev.1.00 www.SiliconStandard.com 10 Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.

Revision History

Revision Modification Description Revision 2006/11/10 Original Release. Revision 2007/01/19 1. Change the clamping cell symbol for easy understanding. 2. Change the expression of CIN from @ VIN=0V to @ VIN=2.5V. 3. Add the TLP characterization. 4. Add the ESD holding volt age characterization under IEC 61000-4-2 +6kV contact mode at I/O channel to GND. 5. Correct typos. 6. Update the Mechanical Details. Revision 2007/02/27 Update the spec. of VF, VCL, and Vhold. Revision 2007/05/15 Update the Marking Code from 102X to 102XY.