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N-Ch Enhancement Mode Power MOSFET 53A, 40V , RDS(ON) 12mΩ Elektronische Bauelemente 10-Jun-2010 Rev.A Page 1 of 2 http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. A C D N O P G E FHK JM B TO-252(D-Pack) RoHS Compliant Product A suffix of “-C” specifies halogen free
DESCRIPTION
These miniature surface mount MOSFETs utilize a high cell density trench process to provide low RDS(on) and to ensure minimal power loss and heat dissipation. Typical applications are DC-DC converters and power management in portable And battery-powered products such as computers, printers, PCMCIA cards, cellular and cordless telephones.
FEATURES
Low RDS(on) provides higher efficiency and extends battery life. Low thermal impedance copper leadframe DPAK saves board space. Fast switching speed. High performance trench technology. PRODUCT SUMMARY PRODUCT SUMMARY VDS(V) RDS(on) m( ID(A) 40 12@VGS= 10V 53 14@VGS= 4.5V 49 ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified) PARAMETER SYMBOL RATINGS UNIT Drain-Source Voltage VDS 40 V Gate-Source Voltage V GS ±20 V Continuous Drain Current a ID @TA=25℃ 53 A Pulsed Drain Current b IDM 40 A Continuous Source Current (Diode Conduction) a I S 30 A Total Power Dissipation a P D @TA=25℃ 50 W Operating Junction and Storage Temperature Range TJ, TSTG -55 ~ 175 °C THERMAL RESISTANCE RATINGS Maximum Thermal Resistance Junction-Ambient a R θJA 50 °C / W Maximum Thermal Resistance Junction-Case R θJC 3.0 °C / W Notes： a. Surface Mounted on 1” x 1” FR4 Board. b. Pulse width limited by maximum junction temperature. REF. Millimeter REF. Millimeter Min. Max. Min. Max. A 6.4 6.8 J 2.30 REF. B 5.20 5.50 K 0.70 0.90 C 2.20 2.40 M 0.50 1.1 D 0.45 0.58 N 0.9 1.6 E 6.8 7.3 O 0 0.15 F 2.40 3.0 P 0.43 0.58 G 5.40 6.2 H 0.8 1.20 Gate Source Drain
N-Ch Enhancement Mode Power MOSFET 53A, 40V , RDS(ON) 12mΩ Elektronische Bauelemente 10-Jun-2010 Rev.A Page 2 of 2 http://www.SeCoSGmbH.com/ Any changes of specification will not be informed individually. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) PARAMETER SYMBO MIN. TYP. MAX. UNIT TEST CONDITIONS Static Gate-Threshold Voltage V GS(th) 1.0 - - V V DS= VGS, ID = 250 μA Gate-Body Leakage I GSS - - ±100 nA V DS = 0V, VGS= 20V Zero Gate Voltage Drain Current I DSS - - 1 μA VDS= 32V, VGS= 0V - - 25 V DS= 32V, VGS= 0V, TJ=55°C On-State Drain Current a I D(on) 34 - - A V DS = 5V, VGS= 10V Drain-Source On-Resistance a R DS(ON) - - 12 mΩ VGS= 10V, ID= 53 A - - 14 V GS= 4.5V, ID= 49 A Forward Transconductance a g fs - 22 - S V DS= 15V, ID= 53 A Diode Forward Voltage V SD - 1.1 - V I S= 34 A, VGS= 0 V Dynamic b Total Gate Charge Q g - 4.0 - nC VDS = 15 V VGS = 4.5 V ID = 53 A Gate-Source Charge Q gs - 1.1 - Gate-Drain Charge Q gd - 1.4 - Turn-on Delay Time T d(on) - 16 - nS VDD= 25 V ID= 34 A VGEN = 10 V RL= 25 Rise Time T r - 5 - Turn-off Delay Time T d(off) - 23 - Fall Time T f - 3 - Notes a. Pulse test ：Pulse width ≦ 300 μs, duty cycle ≦ 2 ％. b. Guaranteed by design, not s ubject to production testing.