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ISO7240_1 TI | Alldatasheet

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A GND1 VCC1 GND1 GND2 GND2 INB INC OUTA OUTC OUTB EN VCC2 IND OUTD ISO7241 IN A GND1 VCC1 GND1 GND2 GND2 INB INC OUTA OUTC OUTB VCC2 INDOUTD EN2EN1 ISO7242 IN A GND1 VCC1 GND1 GND2 GND2 INB OUTA OUTB VCC2 INDOUTD EN2EN1 OUTC INC ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 www.ti.com QUAD DIGITAL ISOLATORS 25, and 150-Mbps Signaling Rate Options High Electromagnetic Immunity (see application report SLLA181 Low Channel-to-Channel Output Skew; C to 125 C Operating Range ns Max Low Pulse-Width Distortion (PWD); ns Max Industrial Fieldbus Low Jitter Content; ns Typ at 150 Mbps Computer Peripheral Interface Typical 25-Year Life at Rated Working Voltage Servo Control Interface (see application note SLLA197 and Figure Data Acquisition 4000-V peak Isolation, 560-V peak Working Voltage UL 1577 Certified kV ESD Protection Operate With 3.3-V or 5-V Supplies The ISO7240, ISO7241 and ISO7242 are quad-channel digital isolators with multiple channel configurations and output enable functions. These devices have logic input and output buffers separated by TI s silicon dioxide (SiO isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents from entering the local ground and interfering with or damaging sensitive circuitry. The ISO7240 has all four channels in the same direction while the ISO7241 has three channels the same direction and one channel in opposition. The ISO7242 has two channels in each direction. The A and C option devices have TTL input thresholds and a noise-filter at the input that prevents transient pulses from being passed to the output of the device. The M option devices have CMOS Vcc/2 input thresholds and do not have the input noise-filter or the additional propagation delay. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. (Contact TI for a logic low failsafe option). These devices may be powered from either 3.3-V or 5-V supplies on either side in any 3.3-V 3.3-V, 5-V 5-V, 5-V 3.3-V, or 3.3-V 5-V combination. Note that the signal input pins are 5-V tolerant regardless of the voltage supply level being used. These devices are characterized for operation over the ambient temperature range of C to 125 Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com FUNCTION DIAGRAM Input Filter Galvanic□Isolation Barrier Vref Vref Data□MUX EN IN OSC PWM AC□Detect Output□Buffer DC□Channel AC□Channel Filter Pulse□Width Demodulation Carrier□Detect OUT ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table Device Function Table ISO724x (1) INPUT OUTPUT ENABLE OUTPUT V CC1 V CC2 (IN) (EN) (OUT) H H or Open H L H or Open L PU PU X L Z Open H or Open H PD PU X H or Open H PD PU X L Z (1) PU Powered Up; PD Powered Down X Irrelevant; H High Level; L Low Level Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 AVAILABLE OPTIONS SIGNALING INPUT CHANNEL MARKED ORDERING PRODUCT RATE THRESHOLD CONFIGURATION AS NUMBER (1) ISO7240ADW (rail) ~1.5 V (TTL) ISO7240ADW Mbps ISO7240A (CMOS compatible) ISO7240ADWR (reel) ISO7240CDW (rail) ~1.5 V (TTL) ISO7240CDW Mbps ISO7240C (CMOS compatible) ISO7240CDWR (reel) ISO7240MDW (rail) ISO7240MDW 150 Mbps Vcc/2 (CMOS) ISO7240M ISO7240MDWR (reel) ISO7241ADW (rail) ~1.5 V (TTL) ISO7241ADW Mbps ISO7241A (CMOS compatible) ISO7241ADWR (reel) ISO7241CDW (rail) ~1.5 V (TTL) ISO7241CDW Mbps ISO7241C (CMOS compatible) ISO7241CDWR (reel) ISO7241MDW (rail) ISO7241MDW 150 Mbps Vcc/2 (CMOS) ISO7241M ISO7241MDWR (reel) ISO7242ADW (rail) ~1.5 V (TTL) ISO7242ADW Mbps ISO7242A (CMOS compatible) ISO7242ADWR (reel) ISO7242CDW (rail) ~1.5 V (TTL) ISO7242CDW Mbps ISO7242C (CMOS compatible) ISO7242CDWR (reel) ISO7242MDW (rail) ISO7242MDW 150 Mbps Vcc/2 (CMOS) ISO7242M ISO7242MDWR (reel) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING CONDITIONS ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 VALUE UNIT V CC Supply voltage (2) V CC1 V CC2 0.5 to V V I Voltage at IN, OUT, EN 0.5 to V I O Output current mA Human Body Model JEDEC Standard 22, Test Method A114-C.01 kV Electrostatic Field-Induced-Charged Device ESD JEDEC Standard 22, Test Method C101 All pins discharge Model Machine Model ANSI/ESDS5.2-1996 200 V T J Maximum junction temperature 170 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal and are peak voltage values. MIN TYP MAX UNIT 4.5 5.5 V CC Supply voltage, V CC1 V CC2 V 3.15 3.45 I OH High-level output current mA I OL Low-level output current mA ISO724xA µ s t ui Input pulse width ISO724xC ns ISO724xM 6.67 ISO724xA 1500 (1) 1000 kbps 1/t ui Signaling rate ISO724xC (1) Mbps ISO724xM 200 (1) 150 V IH High-level input voltage (IN) 0.7 V CC V CC V ISO724xM V IL Low-level input voltage (IN) 0.3 V CC V V IH High-level input voltage (IN) (EN on all devices) V CC V ISO724xA, ISO724xC V IL Low-level input voltage (IN) (EN on all devices) 0.8 V T J Junction temperature 150 C H External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9 A/m 1000 certification (1) Typical value at room temperature and well-regulated power supply. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com ELECTRICAL CHARACTERISTICS ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 V CC1 and V CC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7240A/C/M Quiescent V I V CC or All channels, no load, ISO7240A Mbps mA EN at V ISO7240C/M Mbps 10.5 ISO7241A/C/M Quiescent 6.5 V I V CC or All channels, no load, I CC1 ISO7241A Mbps 6.5 mA EN at EN at V ISO7241C/M Mbps ISO7242A/C/M Quiescent V I V CC or All channels, no load, ISO7242A Mbps mA EN at EN at V ISO7242C/M Mbps ISO7240A/C/M Quiescent V I V CC or All channels, no load, ISO7240A Mbps mA EN at V ISO7240C/M Mbps ISO7241A/C/M Quiescent V I V CC or All channels, no load, I CC2 ISO7241A Mbps mA EN at EN at V ISO7241C/M Mbps ISO7242A/C/M Quiescent V I V CC or All channels, no load, ISO7242A Mbps mA EN at EN at V ISO7242C/M Mbps ELECTRICAL CHARACTERISTICS I OFF Sleep mode output current EN at VCC, Single channel µ A I OH mA, See Figure V CC 0.8 V OH High-level output voltage V I OH µ See Figure V CC 0.1 I OL mA, See Figure 0.4 V OL Low-level output voltage V I OL µ See Figure 0.1 V I(HYS) Input voltage hysteresis 150 mV I IH High-level input current IN from V to V CC µ A I IL Low-level input current C I Input capacitance to ground IN at V CC V I 0.4 sin (4E6 π pF CMTI Common-mode transient immunity V I V CC or See Figure kV/ µ s Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com SWITCHING CHARACTERISTICS ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 V CC1 and V CC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH t PHL Propagation delay ISO724xA PWD Pulse-width distortion (1) PHL t PLH ns t PLH t PHL Propagation delay ISO724xC See Figure PWD Pulse-width distortion (1) PHL t PLH 2.5 t PLH t PHL Propagation delay ISO724xM ns PWD Pulse-width distortion (1) PHL t PLH ISO724xA/C ns t sk(o) Channel-to-channel output skew (2) ISO724xM t r Output signal rise time See Figure ns t f Output signal fall time t PHZ Propagation delay, high-level-to-high-impedance output t PZH Propagation delay, high-impedance-to-high-level output See Figure ns t PLZ Propagation delay, low-level-to-high-impedance output t PZL Propagation delay, high-impedance-to-low-level output t fs Failsafe output delay time from input power loss See Figure µ s 150 Mbps NRZ data input, Same t jit(pp) Peak-to-peak eye-pattern jitter ISO724xM polarity input on all channels, See ns Figure (1) Also referred to as pulse skew. (2) t sk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com ELECTRICAL CHARACTERISTICS ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 V CC1 at 5-V, V CC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7240A/C/M Quiescent ISO7240A Mbps V I V CC or All channels, no load, EN at V mA ISO7240C/M Mbps 10.5 ISO7241A/C/M Quiescent 6.5 V I V CC or All channels, no load, EN at I CC1 ISO7241A Mbps 6.5 mA EN at V ISO7241C/M Mbps ISO7242A/C/M Quiescent V I V CC or All channels, no load, EN at ISO7242A Mbps mA EN at V ISO7242C/M Mbps ISO7240A/C/M Quiescent 9.5 ISO7240A Mbps V I V CC or All channels, no load, EN at V mA ISO7240C/M Mbps 10.5 ISO7241A/C/M Quiescent V I V CC or All channels, no load, EN at I CC2 ISO7241A Mbps mA EN at V ISO7241C/M Mbps 11.5 ISO7242A/C/M Quiescent V I V CC or All channels, no load, EN at ISO7242A Mbps mA EN at V ISO7242C/M Mbps ELECTRICAL CHARACTERISTICS I OFF Sleep mode output current EN at VCC, Single channel µ A ISO7240 V CC 0.4 I OH mA, See Figure ISO724x V OH High-level output voltage V CC 0.8 V (5-V side) I OH µ See Figure V CC 0.1 I OL mA, See Figure 0.4 V OL Low-level output voltage V I OL µ See Figure 0.1 V I(HYS) Input voltage hysteresis 150 mV I IH High-level input current IN from V to V CC µ A I IL Low-level input current C I Input capacitance to ground IN at V CC V I 0.4 sin (4E6 π pF CMTI Common-mode transient immunity V I V CC or See Figure kV/ µ s Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com SWITCHING CHARACTERISTICS ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 V CC1 at 5-V, V CC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH t PHL Propagation delay 100 ISO724xA PWD Pulse-width distortion (1) PHL t PLH ns t PLH t PHL Propagation delay ISO724xC See Figure PWD Pulse-width distortion (1) PHL t PLH t PLH t PHL Propagation delay ISO724xM ns PWD Pulse-width distortion (1) PHL t PLH ISO724xA/C ns t sk(o) Channel-to-channel output skew (2) ISO724xM t r Output signal rise time See Figure ns t f Output signal fall time t PHZ Propagation delay, high-level-to-high-impedance output t PZH Propagation delay, high-impedance-to-high-level output See Figure ns t PLZ Propagation delay, low-level-to-high-impedance output t PZL Propagation delay, high-impedance-to-low-level output t fs Failsafe output delay time from input power loss See Figure µ s 150 Mbps PRBS NRZ data input, t jit(pp) Peak-to-peak eye-pattern jitter ISO724xM Same polarity input on all ns channels, See Figure (1) Also known as pulse skew (2) t sk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com ELECTRICAL CHARACTERISTICS ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 V CC1 at 3.3-V, V CC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7240A/C/M Quiescent 0.5 ISO7240A Mbps V I V CC or All channels, no load, EN at V mA ISO7240C/M Mbps ISO7241A/C/M Quiescent V I V CC or All channels, no load, EN at I CC1 ISO7241A Mbps mA EN at V ISO7241C/M Mbps 6.5 ISO7242A/C/M Quiescent V I V CC or All channels, no load, EN at ISO7242A Mbps mA EN at V ISO7242C/M Mbps ISO7240A/C/M Quiescent ISO7240A Mbps V I V CC or All channels, no load, EN at V mA ISO7240C/M Mbps ISO7241A/C/M Quiescent V I V CC or All channels, no load, EN at I CC2 ISO7241A Mbps mA EN at V ISO7241C/M Mbps ISO7242A/C/M Quiescent V I V CC or All channels, no load, EN at ISO7242A Mbps mA EN at V ISO7242C/M Mbps ELECTRICAL CHARACTERISTICS I OFF Sleep mode output current EN at VCC, Single channel µ A ISO7240 V CC 0.4 I OH mA, See Figure ISO724x V CC 0.8 V OH High-level output voltage V (5-V side) I OH µ See Figure V CC 0.1 I OL mA, See Figure 0.4 V OL Low-level output voltage V I OL µ See Figure 0.1 V I(HYS) Input voltage hysteresis 150 mV I IH High-level input current IN from V to V CC µ A I IL Low-level input current C I Input capacitance to ground IN at V CC V I 0.4 sin (4E6 π pF Common-mode transient V I V CC or See Figure CMTI kV/ µ s immunity Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com SWITCHING CHARACTERISTICS ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 V CC1 at 3.3-V and V CC2 at 5-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH t PHL Propagation delay 100 ISO724xA PWD Pulse-width distortion (1) PHL t PLH ns t PLH t PHL Propagation delay ISO724xC See Figure PWD Pulse-width distortion (1) PHL t PLH t PLH t PHL Propagation delay ISO724xM ns PWD Pulse-width distortion (1) PHL t PLH ISO724xA/C 2.5 t sk(o) Channel-to-channel output skew (2) ns ISO724xM t r Output signal rise time See Figure ns t f Output signal fall time t PHZ Propagation delay, high-level-to-high-impedance output t PZH Propagation delay, high-impedance-to-high-level output See Figure ns t PLZ Propagation delay, low-level-to-high-impedance output t PZL Propagation delay, high-impedance-to-low-level output t fs Failsafe output delay time from input power loss See Figure µ s 150 Mbps NRZ data input, Same polarity t jit(pp) Peak-to-peak eye-pattern jitter ISO724xM ns input on all channels, See Figure (1) Also known as pulse skew (2) t sk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com ELECTRICAL CHARACTERISTICS ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 V CC1 and V CC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7240A/C/M Quiescent 0.5 V I V CC or all channels, no load, ISO7240A Mbps mA EN at V ISO7240C/M Mbps ISO7241A/C/M Quiescent V I V CC or all channels, no load, I CC1 ISO7241A Mbps EN at EN at V ISO7241C/M Mbps 6.5 mA ISO7242A/C/M Quiescent V I V CC or all channels, no load, ISO7242A Mbps EN at EN at V ISO7242C/M Mbps ISO7240A/C/M Quiescent 9.5 V I V CC or all channels, no load, ISO7240A Mbps mA EN at V ISO7240C/M Mbps 10.5 ISO7241A/C/M Quiescent V I V CC or all channels, no load, I CC2 ISO7241A Mbps EN at EN at V ISO7241C/M Mbps 11.5 mA ISO7242A/C/M Quiescent V I V CC or all channels, no load, ISO7242A Mbps EN at EN at V ISO7242C/M Mbps ELECTRICAL CHARACTERISTICS I OFF Sleep mode output current EN at V CC single channel µ A I OH mA, See Figure V CC 0.4 V OH High-level output voltage V I OH µ See Figure V CC 0.1 I OL mA, See Figure 0.4 V OL Low-level output voltage V I OL µ See Figure 0.1 V I(HYS) Input voltage hysteresis 150 mV I IH High-level input current IN from V or V CC µ A I IL Low-level input current C I Input capacitance to ground IN at V CC V I 0.4 sin (4E6 π pF CMTI Common-mode transient immunity V I V CC or See Figure kV/ µ s Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com SWITCHING CHARACTERISTICS ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 V CC1 and V CC2 at 3.3-V operation, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH t PHL Propagation delay 110 ISO724xA PWD Pulse-width distortion PHL t PLH (1) ns t PLH t PHL Propagation delay ISO724xC See Figure PWD Pulse-width distortion PHL t PLH (1) t PLH t PHL Propagation delay ISO724xM ns PWD Pulse-width distortion PHL t PLH (1) ISO724xA/C 3.5 t sk(o) Channel-to-channel output skew (2) ns ISO724xM t r Output signal rise time See Figure t f Output signal fall time t PHZ Propagation delay, high-level-to-high-impedance output t PZH Propagation delay, high-impedance-to-high-level output See Figure ns t PLZ Propagation delay, low-level-to-high-impedance output t PZL Propagation delay, high-impedance-to-low-level output t fs Failsafe output delay time from input power loss See Figure µ s 150 Mbps PRBS NRZ data input, same t jit(pp) Peak-to-peak eye-pattern jitter ISO724xM ns polarity input on all channels, See Figure (1) Also referred to as pulse skew. (2) t sk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com PARAMETER MEASUREMENT INFORMATION IN OUT VO CL Input Generator 50 /c87VI NOTE A NOTE□B V 1/2CC t ft r 10% 90% 50% 0□V 50% VI tPLH tPHL VOH VOL ISOLATION□BARRIER VO V 1/2CC V 1CC Input Generator 50 /c87 OUT EN VO VI IN0V ISOLATION BARRIER CL NOTE A NOTE B Vcc Input Generator OUT R =□1□k ±1%L /c87 EN VO VI IN3V ISOLATION BARRIER CL NOTE A NOTE B Vcc/2 Vcc 0 V 0 V V I Vcc/2 50% 0.5 V tPHZ tPZH VO VOH Vcc Vcc 0 V tPLZ t VO VI Vcc/2 Vcc/2 0.5 V VOL 50% PZL R =□1□k ±1%L /c87 50 /c87 ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 The input pulse is supplied by a generator having the following characteristics: PRR kHz, 50% duty cycle, t r ns, t f ns, Z O Ω C L pF and includes instrumentation and fixture capacitance within 20%. Figure Switching Characteristic Test Circuit and Voltage Waveforms The input pulse is supplied by a generator having the following characteristics: PRR kHz, 50% duty cycle, t r ns, t f ns, Z O Ω C L pF and includes instrumentation and fixture capacitance within 20%. Figure Enable/Disable Propagation Delay Time Test Circuit and Waveform Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com tfs IN OUT ISOLA TION□BARRIER 0□V or V 1CC V 1CC VI CL NOTE□B VO VI VO 50% V 1CC 0□V VOH VOL 2.7□V VCM IN OUT GND1 NOTE□B V or□VOH OLISOLATION□BARRIER V 1CC V 2CC GND2 Pass-fail□criteria: Output□must remain□stable OUT Tektronix HFS9009 PATTERN GENERATOR IN DUT Tektronix 784D V 1CC 0□V V / 2C C Jitter ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) C L pF and includes instrumentation and fixture capacitance within 20%. The input pulse is supplied by a generator having the following characteristics: PRR kHz, 50% duty cycle, t r ns, t f ns, Z O Ω Figure Failsafe Delay Time Test Circuit and Voltage Waveforms C L pF and includes instrumentation and fixture capacitance within 20%. The input pulse is supplied by a generator having the following characteristics: PRR kHz, 50% duty cycle, t r ns, t f ns, Z O Ω Figure Common-Mode Transient Immunity Test Circuit and Voltage Waveform NOTE: PRBS bit pattern run length is Transition time is 800 ps. NRZ data input has no more than five consecutive or 0s. Figure Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com DEVICE INFORMATION PACKAGE CHARACTERISTICS DEVICE I/O SCHEMATICS OUT 8 /c87 13 /c87 VCC Output IN VCCVCC VCC Input 1□M/c87 VCC 500 /c87 VCC EN Enable 500 /c87 1□M/c87 ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air 7.7 mm L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the 8.1 mm package surface Minimum Internal Gap (Internal Distance through the insulation 0.008 mm Clearance) Input to output, V IO 500 all pins on each side of the R IO Isolation resistance >10 Ω barrier tied together creating a two-terminal device C IO Barrier capacitance Input to output V I 0.4 sin (4E6 π pF C I Input capacitance to ground V I 0.4 sin (4E6 π pF Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com REGULATORY INFORMATION THERMAL CHARACTERISTICS TYPICAL CHARACTERISTIC CURVES 0 25 50 75 100 125 150 Signaling□Rate□-□Mbps I -□Supply□Current□-□mA/RMS CC T =□25°C, Load□=□15□pF, All□Channels A 5-V□I CC2 3.3-V□ICC2 3.3-V□ICC1 5-V□ICC1 0 25 50 75 100 125 150 Signaling□Rate□-□Mbps I -□Supply□Current□-□mA/RMS CC T =□25°C, Load□=□15□pF, All□Channels A 5-V□I CC2 3.3-V□ICC2 3.3-V□ICC1 5-V□ICC1 ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 VDE CSA UL Recognized under 1577 Certified according to IEC Approved under CSA Component Component Recognition 60747-5-2 Acceptance Notice Program (1) File Number: Pending File Number: Pending File Number: E181974 (1) Production tested 3000 Vrms for second in accordance with UL 1577. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low-K Thermal Resistance (1) 168 θ JA Junction-to-air C/W High-K Thermal Resistance 96.1 θ JB Junction-to-Board Thermal Resistance C/W θ JC Junction-to-Case Thermal Resistance C/W V CC1 V CC2 5.5 T J 150 C L pF, P D Device Power Dissipation 220 mW Input a 50% duty cycle square wave (1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. ISO7240C/M RMS SUPPLY CURRENT ISO7241C/M RMS SUPPLY CURRENT vs vs SIGNALING RATE SIGNALING RATE Figure Figure Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com 0 25 50 75 100 125 150 Signaling□Rate□-□Mbps I -□Supply□Current□-□mA/RMS CC T =□25°C, Load□=□15□pF, All□Channels A 5-V□I CC1,ICC2 3.3-V□ICC1,ICC2 -40 -25 -10 5 20 35 50 65 80 95 110 125 T -□Free-Air□Temperature□- CA ° Propagation□Delay□-□ns T =□25°C, Load□=□15□pF, All□Channels A C□3.3-V ,□t pHLtpLH M□3.3-V ,□t pHLtpLH C□5-V ,□t pHLtpLH M□5-V ,□t pHLtpLH 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 Input□Voltage□Threshold□-□V T -□Free-Air□Temperature□- CA ° 5□V□Vth+ 3.3□V□Vth+ 5□V□Vth- 3.3□V□Vth- Air□Flow□at□7□cf/m, Low_K□Board 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 -40 -25 -10 5 20 35 50 65 80 95 110 125 T -□Free-Air□Temperature□- CA ° V Failsafe□Threshold□-□V CC1 Vfs+ Vfs- Load□=□15□pF, Air□Flow□at□7/cf/m, Low-K□Board CC ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 TYPICAL CHARACTERISTIC CURVES (continued) ISO7242C/M RMS SUPPLY CURRENT PROPAGATION DELAY vs vs SIGNALING RATE FREE-AIR TEMPERATURE Figure Figure INPUT VOLTAGE THRESHOLD V CC1 FAILSAFE THRESHOLD vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE Figure 10. Figure 11. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com 0 1 2 3 4 5 I -□Output□Current□-□mAO V -□Output□Voltage□-□VO V =□5□VCC V =□3.3□VCC Load□=□15□pF, T =□25 C A ° 0 2 4 6 I -□Output□Current□-□mAO V -□Output□Voltage□-□VO V =□5□VCC V =□3.3□VCC Load□=□15□pF, T =□25 C A ° ISO7240 ISO7241 ISO7242 SLLS868A SEPTEMBER 2007 REVISED DECEMBER 2007 TYPICAL CHARACTERISTIC CURVES (continued) HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT vs vs HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE Figure 12. Figure 13. Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): ISO7240 ISO7241 ISO7242

www.ti.com APPLICATION INFORMATION ISO7240x NC IN A GND1 VCC1 GND1 GND2 GND2 IN B IN C OUTA OUTC OUTB EN IN D OUTD VCC2VCC1 VCC2 20□mm Max□From 20□mm Max□From 0.1 F/c109 0.1 F/c109 LIFE EXPECTANCY vs. WORKING VOLTAGE 100 0 250 500 750 1000 WORKING□VOLTAGE□(VIORM)□--□V WORKING□LIFE□-- YEARS VIORM at□560-V

28 Years

1. Typical ISO724x Application Circuit Figure 15. Time-Dependant Dielectric Breakdown Testing Results Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ISO7240 ISO7241 ISO7242

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) ISO7240ADW ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240ADWG4 ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240ADWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240ADWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CDW ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CDWG4 ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240MDW ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240MDWG4 ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240MDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7240MDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241ADW ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241ADWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241CDW ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241MDW ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7241MDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242ADW ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242ADWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242CDW ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242CDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242MDW ACTIVE SOIC DW 16 49 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ISO7242MDWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2007 Addendum-Page 1

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2007 Addendum-Page 2

TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant ISO7240ADWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 ISO7240CDWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 ISO7240MDWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 ISO7241ADWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 ISO7241CDWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 ISO7241MDWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 ISO7242ADWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 ISO7242CDWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 ISO7242MDWR DW 16 SITE 35 330 16 10.9 10.78 3.0 12 16 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Dec-2007 Pack Materials-Page 1

Device Package Pins Site Length (mm) Width (mm) Height (mm) ISO7240ADWR DW 16 SITE 35 406.0 348.0 63.0 ISO7240CDWR DW 16 SITE 35 406.0 348.0 63.0 ISO7240MDWR DW 16 SITE 35 406.0 348.0 63.0 ISO7241ADWR DW 16 SITE 35 406.0 348.0 63.0 ISO7241CDWR DW 16 SITE 35 406.0 348.0 63.0 ISO7241MDWR DW 16 SITE 35 406.0 348.0 63.0 ISO7242ADWR DW 16 SITE 35 406.0 348.0 63.0 ISO7242CDWR DW 16 SITE 35 406.0 348.0 63.0 ISO7242MDWR DW 16 SITE 35 406.0 348.0 63.0 PACKAGE MATERIALS INFORMATION www.ti.com 19-Dec-2007 Pack Materials-Page 2

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