SSC8036GQ4 AFSEMI | Alldatasheet

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http://www.afsemi.com SSC-2V0 Analog Future N-Channel Enhancement Mode MOSFET  Features  Applications VDS VGS RDSon TYP ID 30V ±20V 14 mR@10V 18A 20mR@4V5  Load Switch  PC/NB  DCDC conversion  Pin configuration Bottom View  General Description This device uses advanced trench technology to provide excellent RDS(ON) and low gate charge. This device is suitable for use as a load switch or in PWM applications.  Package Information

http://www.afsemi.com SSC-2V0 Analog Future  Absolute Maximum Ratings @ TA = 25° C unless otherwise specified Parameter Symbol Maximum Unit 10S Steady Drain-Source Voltage VDSS 30 V Gate-Source Voltage VGSS ±20 V Continuous Drain Current 1 VGS@10V TC = 25° C ID 18 A Continuous Drain Current 1 VGS@10V TC = 100°C 13 A Continuous Drain Current 2 VGS@10V TA = 25° C IDSM 10 8.6 A Continuous Drain Current 2 VGS@10V TA = 70°C 7.5 5.8 A Plused Drain Current 3 IDM 102 A Repetitive avalanche energy L=0.1mH 3 EAS 86 mJ Power Dissipation 1 TC = 25° C PD 24 W Power Dissipation 1 TC = 100°C 9.5 W Power Dissipation 2 TA = 25°C PDSM 3 W Power Dissipation 2 TA = 70°C 2 W Storage and Junction Temperature Range TJ, TSTG -55 to +150 °C  Thermal Characteristics Parameter Symbol Typ Max Units Maximum Junction-to-Ambient2 t≤10S RJA -- 42 ° C/W Maximum Junction-to-Ambient 2 4 Steady-State -- 62.5 ° C/W Maximum Junction-to-Case Steady-State RJC -- 5.2 ° C/W

http://www.afsemi.com SSC-2V0 Analog Future  Electrical Characteristics @ TA = 25° C unless otherwise specified Parameter Symbol Test Conditions Min Typ Max Unit Drain–Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250μA 30 -- -- V Gate Threshold Voltage VGS(TH) VDS = VGS, ID =250μA 1 -- 3 V Gate–Body Leakage Current IGSS VGS = ± 20 V, VDS = 0 V -- -- ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 24 V, VGS = 0 V -- -- 1 uA Drain–Source On–State Resistance RDS(ON) VGS = 10 V, ID = 15 A -- 14 21 mR VGS = 4.5 V, ID = 12 A -- 20 36 Forward Transconductance GFS VDS = 15 V, ID = 12 A 8 16 -- S Diode Forward Voltage VSD VGS = 0 V, IS = 1A -- 0.8 1.5 V Input Capacitance CISS VDS = 15 V, VGS = 0 V, f = 1.0 MHz -- 550 -- pF Output Capacitance COSS -- 98 -- Reverse Transfer Capacitance CRSS -- 75 -- Turn–On Delay Time TD(ON) VDS = 15 V, RL = 2.3R, VGS = 10V, RGEN=3R -- -- 18 ns Turn–Off Delay Tim TD(OFF) -- -- 70 Note : 1. The power dissipation P D is based on T J(MAX)=150°C, using junction -to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heat sinking is used. 2. The value of RJA is measured with the device mounted on 1in2 FR-4 board with 2oz. Copper, in a still air environment with TA =25°C. The Power dissipation PDSM is based on RJA t ≤ 10s value and the maximum allowed junction temperature of 150°C. The value in any given application depends on the user's specific board design. 3. Repetitive rating, pulse width limited by junction temperature T J(MAX)=150° C. Ratings are based on low frequency and duty cycles to keep initial TJ =25° C. 4. The RJA is the sum of the thermal impedence from junction to case RJC and case to ambient.

http://www.afsemi.com SSC-2V0 Analog Future Typical Performance Characteristics 0 1 2 3 4 5 VGS=10.0V VGS=4.5V VGS=3.5V VGS=3.0V ID, Drain Current (A) VDS, Drain-Source Voltage (V) Fig1. Output Characteristics o C o C -55 o C 125 o C ID, Drain current(A) VGS, Gate-to-source Voltage(V) Fig2. Transfer Characteristics 0 5 10 15 20 400 800 1200 1600 2000 C, Capacitance (pF) VDS, Drain-to-Source Voltage (V) Fig3. Capacitance -25 0 25 50 75 100 125 150 VGS=10V VGS=4.5V On Resistance (mR) Tj, Junction Temperature ( o Fig4. On Resistance vs. Temperature -25 0 25 50 75 100 125 0.0 0.5 1.0 1.5 2.0 2.5 ID=250uA Threshold Voltage (V) Tj, Junction Temperature ( o Fig5. Gate Threshold vs. Temperature 0.01 0.1 IS, Source-Drain Current (A) VDS, Drain-Source Voltage (V) Fig6. Diode Forward Characteristics

http://www.afsemi.com SSC-2V0 Analog Future DISCLAIMER AFSEMI RESERVES THE RIGHT TO MAKE CHANGES WITHOUT F URTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. AFSEMI DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICIENCE UNDER ITS PATENT RIG HTS, NOR THE RIGHTS OF OTHERS. THE GRAPHS PROVIDED IN THIS DOCUMENT ARE STATISTICAL SUMMARIES BASED ON A LIMITED NUMBER OF SAMPLES AN D ARE PROVIDED FOR I NFORMATIONAL PURPOSE ONLY. THE PERFORMANCE CHARACTERISTICS LISTED IN THEM ARE NOT TESTED OR GUARANTEED. IN SOME GRAPHS, THE DATA PRE SENTED MAY BE OUTSID E THE SPECIFIED OPER ATING RANGE (E.G,. OUTSIDE SPECIFIED PO WER SUPPLY RANGE ) A ND THEREFORE OUTSIDE THE WARRANTED RANGE.