SS810-23GU

SS809 SSC | Alldatasheet

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Technical content

www.SiliconStandard.com 1 of 8 SS809/810G 9/20/2006 Rev.3.01 3-Pi n Microprocessor Reset Circuits

FEATURES

Ultra-low supply current 1µA (typ.) Guaranteed reset valid to Vcc=0.9V Available in three output types: Open-drain active low (SS809N-xxGx) Push-pull active low (SS809-xxGx) Push-pull active high (SS810-xxGx) Power-on reset pulse width min. 140ms Internally fixed threshold 2.3V, 2.6V, 2.9V, 3.1V, 4.0V, 4.4V, 4.6V Tight voltage threshold tolerance: 1.5% Packaged in RoHS-compliant SOT-23-3

APPLICATIONS

l Critical Microprocessor Monitoring

DESCRIPTION

The SS809G and SS810G are low-power microprocessor (µP) supervisory circuits used to monitor power supplies in µP and digital systems. They improve circuit reliability and reduce cost by eliminating external components. These devices provide valid signals in applications with Vcc ranging from 6.0V down to 0.9V. The reset signal lasts for a minimum period of 140ms whenever the VCC supply voltage falls below a preset threshold. Both the SS809G and SS810G were designed with a reset comparator to help identify invalid signals lasting less than 140ms. The only difference between the two devices is that one has an active -low RESET output and the other an active -high RESET output . Low supply current (1µA) makes the SS809G and SS810G ideal for portable equipment. The devices are available in a SOT-23-3 package. TYPICAL APPLICATION CIRCUIT Push -Pull Output VCC VCC GND GND µP RESET INPUT RESET (RESET) VCC SS809G ( SS810G)

www.SiliconStandard.com 2 of 8 SS809/810G 9/20/2006 Rev.3.01 ORDERING INFORMATION PIN CONFIGURATION SS809X-XXGU XX SS810 -XXGU XX Example: SS809 -31GU TR à 3.1V , push- pull version in RoHS-compliant SOT -23-3 , shipped in tape and reel SOT- 23-3 TOP VIEW 1: GND 2: RESET (RESET) 3: VCC 2 1

3 Packing type

TR: Tape and reel Package type GU: RoHS-compliant Pb-free SOT -2 3-3 Reset threshold voltage 23: 2.3V 26: 2.6V 29: 2.9V 31: 3.1V 40: 4.0V 44: 4.4V 46: 4.6V Output type Default: Push-Pull type N: N-ch open-drain type SOT -23 Part Marking Part No. Marking Part No. Marking Part No. Marking SS809-23GU RA23P SS809N-23GU RB23P SS810-23GU RD23P SS809-26GU RA26P SS809N-26GU RB26P SS810-26GU RD26P SS809-29GU RA29P SS809N-29GU RB29P SS810-29GU RD29P SS809-31GU RA31P SS809N-31GU RB31P SS810-31GU RD31P SS809-40GU RA40P SS809N-40GU RB40P SS810-40GU RD40P SS809-44GU RA44P SS809N-44GU RB44P SS810-44GU RD44P SS809-46GU RA46P SS809N-46GU RB46P SS810-46GU RD46P

www.SiliconStandard.com 3 of 8 SS809/810G 9/20/2006 Rev.3.01 ABSOLUTE MAXIMUM RATINGS VCC -0.3V ~6. 5V RESET, RESET -0.3V ~ (VCC+0.3V) Input Current (VCC) 20mA Output Current (RESET or RESET ) 20mA Continuous Power Dissipation (TA = +70°C) 320mW Operating Junction Temperature Range -40°C ~ 85°C Storage Temperature Range - 65°C ~ 125°C Lead Temperature (Soldering) 10 sec 260°C Note1: Any stress beyond the Absolute Maximum Ratings above may cause permanent damage to the device. TEST CIRCUIT RESET 2VCC3 GND 1SS809G Vin Iin

www.SiliconStandard.com 4 of 8 SS809/810G 9/20/2006 Rev.3.01

ELECTRICAL CHARACTERISTICS

(Typical values are at T A=25°C, unless otherwise specified .) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Operating Voltage Range VCC 0.9 6 V Supply Current ICC VCC = VTH +0.1V 1 3 µA TA=+25°C 2.265 2.3 2.335 SS809-23 TA= -40°C to +85°C 2.254 2.346 TA=+25°C 2.561 2.6 2.639 SS809-26 TA= -40°C to +85°C 2.548 2.652 TA=+25°C 2.857 2.9 2.944 SS809-29 TA= -40°C to +85°C 2.842 2.958 TA=+25°C 3.054 3.1 3.147 SS809-31 TA= -40°C to +85°C 3.038 3.162 TA=+25°C 3.940 4.0 4.060 SS809-40 TA= -40°C to +85°C 3.920 4.080 TA=+25°C 4.334 4.4 4.466 SS809-44 TA= -40°C to +85°C 4.312 4.488 TA=+25°C 4.531 4.6 4.669 Reset Threshold VTH SS809-46 TA=-40°C to +85°C 4.508 4.692 V VCC to Reset Delay TRD VCC=VTH to (VTH -0.1V), VTH=3.1V 20 µS TA=+25°C 140 230 560 Reset Active Timeout Period TRP VCC = VTH (MAX) TA= -40°C to +85°C 100 1030 mS VOH VCC=VTH+0.1V, ISOURCE=1mA 0.8VCC RESET Output Voltage VOL VCC=VTH - 0.1V, ISINK=1mA 0.2Vcc V VOH VCC=VTH-0.1V, ISOURCE=1mA 0.8VCC RESET Output Voltage VOL VCC=VTH+0.1V, ISINK=1mA 0.2Vcc V Note2: RESET output is for the SS809G; RESET output is for the SS810G. Note3: Specifications for operating temperature ranges from -40°C to 85°C are guaranteed by Statistical Quality Controls (SQC), with no production testing.

www.SiliconStandard.com 5 of 8 SS809/810G 9/20/2006 Rev.3.01 TYPICAL PERFORMANCE CHARACTERISTICS -40 -20 0 20 40 60 80 100 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 VTH=2.3V VTH=3.1V VTH=4.6V Supply Current (µA) Temperature (°C) Fig 1 Supply Current vs. Temperature Power -Down Reset Delay (µs) Fig 2 Power-Down Reset Delay vs. Temperature -60 -40 -20 0 20 40 60 80 100 100 110 120 VOD=200mV VOD=100mV VOD=50mV Temperature (°C) VTH=2.3V VOD=VTH-VCC Power -Down Reset Delay (µs) Temperature (°C) Fig 3 Power-Down Reset Delay vs. Temperature -60 -40 -20 0 20 40 60 80 100 100 120 140 160 180 200 220 240 VOD=200mV VOD=100mV VOD=50mV VTH=3.1V VOD=VTH-VCC Power -Down Reset Delay (µs) Temperature (°C) Fig 4 Power-Down Reset Delay vs. Temperature -60 -40 -20 0 20 40 60 80 100 100 200 300 400 VOD=200mV VOD=100mV VOD=50mV VTH=4.6V VOD=VTH-VCC Normalized Reset Threshold (V) Temperature (°C) Fig 5 Normalized Reset Threshold vs. Temperature -40 -20 0 20 40 60 80 100 0.985 0.990 0.995 1.000 1.005 1.010 1.015 VTH=3.1V VTH=2.3V VTH=4.6V Power -Up Reset Timeout (ms) Temperature (°C) Fig 6 Power-Up Reset Timeout vs. Temperature -60 -40 -20 0 20 40 60 80 100 100 200 300 400 500 600 VTH=2.3V VTH=3.1V VTH=4.6V

www.SiliconStandard.com 6 of 8 SS809/810G 9/20/2006 Rev.3.01 BLOCK DIAGRAM NMOS Reset Generator Bandgap RESET GND VCC N-ch Open-Drain Type Reset Generator - Bandgap RESET (RESET) GND VCC Pus h-Pull Type PIN DESCRIPTIONS GND Pin : Ground. RESET Pin (SS809G) : Active low output pin. RESET Output remains low while Vcc is below the reset threshold. RESET P in (SS810G) : Active high output pin. RESET output remains high while Vcc is below the reset threshold. Vcc Pin : Supply voltage.

www.SiliconStandard.com 7 of 8 SS809/810G 9/20/2006 Rev.3.01 DETAIL ED DESCRIPTIONS OF TECHNICAL TERMS RESET OUTPUT The µP will be activated at a valid reset state. These µP supervisory circuits assert reset to prevent code execution errors during power-up, power-down, or brownout conditions. RESET is guaranteed to be a logic low for VTH>VCC>0.9V. Once V CC exceeds the reset threshold, an internal timer keeps RESET low for the reset timeout period; after this interval, RESET goes high. If a brownout condition occurs (VCC drops below the reset threshold), RESET goes low. Any time V CC goes below the reset threshold, the internal timer resets to zero, and RESET goes low. The internal timer is activated after VCC returns above the reset threshold, and RESET remains low for the reset timeout period. BENEFITS OF HIGHLY A CCURATE RESET THRESHOLD The SS809G and SS810G with specified voltage as 5V ± 10% or 3V ±10% are ideal for systems using a 5V ±5% or 3V ±5% power supply. The reset is guaranteed to assert after the power supply falls out of regulation, but before the power drops below the minimum specified operating voltage range of the system ICs. The pre-trimmed thresholds reduc e the range over which an undesirable reset may occur.

APPLICATION INFORMATION

NEGATIVE-GOING VCC TRANSIENTS In addition to issuing a reset to the µ P during power-up, power-down, and brownout conditions, the SS809G series are relatively resistant to short -duration negative-going VCC transients. ENSURING A VALID RESET OUTPUT DOWN TO VCC=0 When VCC falls below 0.9V, the SS809G RESET output no longer sinks current; it becomes an open circuit. In this case, high-impedance CMOS logic inputs connected to RESET can drift to undetermined voltages. Therefore, the SS809G/810G are perfect for most CMOS applications down to VCC of 0.9V. However in applications where RESET must be valid down to 0V, adding a pull-down resistor to RESET causes any leakage currents to flow to ground, holding RESET low. INTERFACING TO A MICROPROCESSOR WITH BIDIRECTIONAL RESET PINS The RESET output on the SS809N is open drain, and this device interfaces easily with µPs that have bidirectional reset pins. Connecting the µP supervisor’s RESET output directly to the microcontroller’s RESET pin with a single pull-up resistor allows either device to assert reset.

Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. www.SiliconStandard.com 8 of 8 SS809/810G 9/20/2006 Rev.3.01 PHYSICAL DIMENSIONS SOT -23-3 (unit: mm) SYMBOL MIN MAX A 1.00 1.30 A1 — 0.10 A2 0.70 0.90 b 0.35 0.50 C 0.10 0.25 D 2.70 3.10 E 1.40 1.80 e 1.90 (TYP) H 2.60 3.00 L 0.37 — H AA2 b θ 1 L CD E e θ1 1° 9°